Abstract: A two-phase liquid immersion cooling method is described in which heat generating computer components cause a dielectric fluid in its liquid phase to vaporize. The dielectric vapor is then condensed back into a liquid phase and used to cool the computer components. Using a pressure controlled vessel and pressure controller, a cooling system may be operated at less than ambient pressure. By controlling the pressure at which the system operates, the user may influence the temperature at which the dielectric fluid vaporizes and thereby achieve increased performance from a given computer component.

Abstract: A cooling subsystem is provided for dissipating heat from processor. The cooling subsystem includes a heat sink comprising an upper portion having a plurality of fins formed therein and a base portion fixed to the upper portion to form a vapor chamber in an enclosed volume between the upper portion and the base portion.

Abstract: Jet-impingement, two-phase cooling apparatuses and power electronics modules having a target surface with single- and two-phase surface enhancement features are disclosed. In one embodiment, a cooling apparatus includes a jet plate surface and a target layer. The jet plate surface includes a jet orifice having a jet orifice geometry, wherein the jet orifice is configured to generate an impingement jet of a coolant fluid. The target layer has a target surface, single-phase surface enhancement features, and two-phase surface enhancement features. The target surface is configured to receive the impingement jet, and the single-phase surface enhancement features and the two-phase enhancement features are arranged on the target surface according to the jet orifice geometry.

Abstract: A system for displaying images is disclosed. A display panel comprises a first substrate and a second substrate with a liquid crystal layer interposed therebetween. A sealant is interposed between the first substrate and a second substrate for sealing the liquid crystal layer. A dielectric layer is overlying the first substrate. Metal lines are overlying the dielectric layer under and/or near the sealant. A planarization layer covers and contacts the dielectric layer and the metal lines to form a first interface between the metal lines and the planarization layer and a second interface between the dielectric layer and the planarization layer. Bridge lines without contacting the planarization layer are disposed under and/or near the sealant, instead of at least a portion of the metal lines contacting the planarization layer.

Abstract: Electronic circuit boards are arranged as respective parallel pairs defining a narrow gap there between. One or more such pairs of boards are supported within a hermitically sealable housing and cooled by way of spraying an atomized liquid coolant from a plurality of nozzles into each narrow gap. Transfer of heat from the circuit boards results in vaporization of at least some of the atomized liquid within the narrow gap. The housing further serves to guide a circulation of vapors out of each narrow gap, back toward the nozzles, and back into each narrow gap. A heat exchanger exhausts heat from the housing and overall system, wherein vapor is condensed back to liquid phase during contact and heat transfer therewith. Condensed liquid is collected and re-pressurized for delivery back to the nozzles such that a sustained cooling operation is performed.

Abstract: A synthetic jet array in a computing device, such as a mobile computing device, to dissipate heat generated by a heat generating component of the mobile computer is described. In one embodiment, a microscale synthetic jet array is integrated within a heat generating component, either on the backside of the heat generating component itself or on a heat spreader coupled to the heat generating component. A method of fabricating a synthetic jet array as an integrated part of a computing device or as a heat spreader is described, as well as a method of use of the synthetic jet array, are described.

Abstract: An interface is formed by pressing a patterned first surface and a second surface together, with a particle-loaded interface material in between. The first surface is fabricated with a pattern of channels designed to redistribute the velocity gradients that occur in the interface material during interface formation in order to control the arrangement, orientation and concentration of particles at the end of the interface formation. The concept finds application in thermal interfaces and controlled placement of nano and micro particles and biological molecules.

Abstract: A semiconductor package includes a chip and a carrier. The chip has an active surface and a lateral surface. The active surface has a number of first bumps and a number of second bumps. The first bumps are spaced by the second bumps. The first bumps are farther from the lateral surface than the second bumps are. The carrier has a base and a number of first inner leads. Each first inner lead has a body portion and a distal end bonding portion. The width of the body portion is smaller than that of the distal end bonding portion. The distal end bonding portions are electrically bonded to the first bumps such that the chip is disposed on the carrier, and each of the body portions is located between the two adjacent second bumps.