Semiconductor Material, E.g., Amorphous Silicon (epo) Patents (Class 257/E23.122)
  • Patent number: 11380804
    Abstract: A semiconductor device including a first conductivity-type layer into which first conductivity-type impurities are introduced, a second conductivity-type layer into which second conductivity-type impurities are introduced, the second conductivity-type impurities being different in polarity from the first conductivity-type impurities, and an intermediate layer that is sandwiched between the first conductivity-type layer and the second conductivity-type layer, and does not include the first conductivity-type impurities or the second conductivity-type impurities, or includes the first conductivity-type impurities or the second conductivity-type impurities at a concentration lower than a concentration of the first conductivity-type impurities in the first conductivity-type layer or the second conductivity-type impurities in the second conductivity-type layer, the first conductivity-type layer, the intermediate layer, and the second conductivity-type layer being stacked in a thickness direction of a semiconductor
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: July 5, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Hitoshi Okano
  • Patent number: 8792060
    Abstract: A liquid crystal display device with a built-in touch screen, which uses a common electrode as a touch-sensing electrode including an intersection of a gate line and a data line to define a pixel region, a bridge line disposed in a central portion of the pixel, an insulating layer formed on the bridge line, a first contact hole disposed through the insulating layer to expose a predetermined portion of an upper surface of the bridge line, a contact metal on the insulating layer and inside the first contact hole, the contact metal electrically connected with the bridge line, a first passivation layer on the contact metal, a second contact hole disposed through the first passivation layer to expose a predetermined portion of an upper surface of the contact metal, a common electrode on the first passivation layer and inside the second contact hole, a conductive line electrically connected with the common electrode, and a second passivation layer on the first passivation layer and the conductive line, wherein the
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: July 29, 2014
    Assignee: LG Display Co., Ltd.
    Inventors: Kum Mi Oh, Jae Hoon Park, Han Seok Lee, Hee Sun Shin, Won Keun Park
  • Patent number: 7960256
    Abstract: In a first aspect, a method of forming an epitaxial film on a substrate is provided. The method includes (a) providing a substrate; (b) exposing the substrate to a silicon source and a carbon source so as to form a carbon-containing silicon epitaxial film; (c) encapsulating the carbon-containing silicon epitaxial film with an encapsulating film; and (d) exposing the substrate to Cl2 so as to etch the encapsulating film. Numerous other aspects are provided.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: June 14, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Zhiyuan Ye, Yihwan Kim, Xiaowei Li, Ali Zojaji, Nicholas C. Dalida, Jinsong Tang, Xiao Chen, Arkadii V. Samoilov
  • Patent number: 7790582
    Abstract: A method for fabricating a polysilicon liquid crystal display device includes: forming a first amorphous silicon layer on a substrate; forming a photoresist pattern on the first amorphous silicon layer; forming a second amorphous silicon layer over the photoresist pattern and the first amorphous silicon layer; defining a channel region on the first amorphous silicon layer; crystallizing the first and second silicon layers; forming an active layer by patterning the crystallized silicon layers; forming a first insulating layer on the active layer; forming a gate electrode on the first insulating layer; forming source and drain electrodes electrically connected to the active layer; and forming a pixel electrode electrically connected to the drain electrode.
    Type: Grant
    Filed: May 14, 2007
    Date of Patent: September 7, 2010
    Assignee: LG Display Co., Ltd.
    Inventor: Kum-Mi Oh
  • Patent number: 7759151
    Abstract: A solid state imaging apparatus comprises: a semiconductor substrate; a photoelectric converting portion on the semiconductor substrate; a light shielding film in a region excluding a light receiving surface of the photoelectric converting portion; and a P-type impurity layer between a lower surface of the light shielding film and the semiconductor substrate.
    Type: Grant
    Filed: January 17, 2008
    Date of Patent: July 20, 2010
    Assignee: Fujifilm Corporation
    Inventors: Jiro Matsuda, Masanori Nagase, Shu Takahashi
  • Patent number: 7750351
    Abstract: An epitaxial crystal for a field effect transistor which has a nitride-based III-V group semiconductor epitaxial crystal grown on a SiC single crystal base substrate having micropipes by use of an epitaxial growth method, wherein at least a part of the micropipes spreading from the SiC single crystal base substrate into the epitaxial crystal terminate between an active layer of the transistor and the SiC single crystal base substrate.
    Type: Grant
    Filed: March 23, 2006
    Date of Patent: July 6, 2010
    Assignees: Sumitomo Chemical Company, Limited, Toyoda Gosei Co., Ltd., National Institute of Advanced Industrial Science and Technology
    Inventors: Hiroyuki Sazawa, Koji Hirata, Masayoshi Kosaki, Hajime Okumura
  • Patent number: 7550778
    Abstract: A method for providing access to a feature on a device wafer, and located outside an encapsulation region is described. The method includes forming a cavity in the lid wafer, aligning the lid wafer with the device wafer so that the cavity is located substantially above the feature, and removing material substantially uniformly from the bottom surface of the lid wafer, until an aperture is formed at the cavity, over the feature on the device wafer. By removing material from the lid wafer in a substantially uniform manner, difficulties with the prior art procedure of saw cutting, such as alignment and debris generation, are avoided.
    Type: Grant
    Filed: May 17, 2006
    Date of Patent: June 23, 2009
    Assignee: Innovative Micro Technology
    Inventors: Douglas L. Thompson, Gregory A. Carlson, David M. Erlach
  • Patent number: 7397063
    Abstract: A semiconductor device comprises a glass substrate serving as a substrate having an insulated surface and a silicon layer located on a position overlapping with this glass substrate. The silicon layer includes an amorphous gettering region. Preferably, the silicon layer includes a main region serving as an active element region, and the gettering region is preferably included in the remaining portion of the silicon layer excluding the main region. Preferably, the silicon layer may include a portion serving as an active region of a thin-film transistor.
    Type: Grant
    Filed: July 26, 2004
    Date of Patent: July 8, 2008
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasuyoshi Itoh, Kaoru Motonami
  • Publication number: 20070284699
    Abstract: Microfabricated devices for operation in a fluid that include a substrate that has a first and second surface and a first electrode material layer located over the first surface of the substrate. The devices have a piezoelectric material layer located over the first electrode material layer and a second electrode material layer located over the piezoelectric material layer. The devices also include a layer of isolation material located over the second electrode material layer that at least one of chemically or electrically isolates a portion of the second electrode material layer from a fluid. Some devices include a layer of conductive material located over the layer of isolation material.
    Type: Application
    Filed: April 17, 2007
    Publication date: December 13, 2007
    Applicant: BioScale, Inc.
    Inventors: Michael Miller, Shivalik Bakshi
  • Patent number: 7081400
    Abstract: A method for manufacturing polysilicon layer is provided. At first, a substrate is provided. An amorphous silicon layer having a second region and a first region is formed on the substrate. The first region is thicker than the second region. The amorphous silicon layer is completely melted to form a melted amorphous silicon layer having a first melted region and a second melted region. The temperature of the bottom center of the first melted region is lower than that of the second melted region and that of the top of the first melted region. The melted amorphous silicon layer is crystallized to form a polysilicon layer. The crystallization begins from the bottom center of the first melted region to the second melted region and the top of the first melted region.
    Type: Grant
    Filed: January 26, 2005
    Date of Patent: July 25, 2006
    Assignee: Au Optronics Corp.
    Inventors: Yi-Wei Chen, Chih-Hsiung Chang, Tsung-Yi Hsu