Encapsulations, E.g., Encapsulating Layers, Coatings, E.g., For Protection (epo) Patents (Class 257/E23.116)
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Patent number: 11404336Abstract: A method of forming a power semiconductor module includes providing a substrate of planar sheet metal, forming channels in an upper surface of the substrate that partially extend through a thickness of the substrate and define a plurality of islands in the substrate, mounting a first semiconductor die on a first one of the islands, forming a molded body of encapsulant that covers the substrate, fills the channels, and encapsulates the semiconductor die, forming a hole in the molded body and a recess in the upper surface of the substrate beneath the hole, and arranging a press-fit connector in the hole and forming a mechanical and electrical connection between an interior end of the press-fit connector and the substrate.Type: GrantFiled: June 29, 2020Date of Patent: August 2, 2022Assignee: Infineon Technologies Austria AGInventors: Wu Hu Li, Raphael Hellwig, Olaf Hohlfeld, Martin Mayer, Ivan Nikitin
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Patent number: 11383429Abstract: Methods and systems for optofluidic device fabrication and design are herein disclosed. In examples, a user may manufacture the optofluidic device using stereolithography (SLA) three-dimensional (3D) printing, in which photosensitive resin is exposed to a focused laser, solidifying specific areas of resin. The optofluidic device may guide light for a broad wavelength range from a liquid or gas channel comprised within and may be used to guide the emission of light and particles of interest to a detector to identify the particles.Type: GrantFiled: January 30, 2020Date of Patent: July 12, 2022Assignee: Whitworth UniversityInventor: Philip S. Measor
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Patent number: 11342280Abstract: A module includes: a substrate having a main surface and a side surface; an electronic component mounted on the main surface; a sealing resin that covers the main surface and the electronic component; and a shield film that covers a surface of the sealing resin and the side surface of the substrate. The sealing resin includes: a resin component containing an organic resin as a main component; and a granular filler containing an inorganic oxide as a main component. On a surface of the sealing resin, which is in contact with the shield film, parts of some grains of the filler are exposed from the resin component, a surface of the resin component includes a nitrogen functional group, and the shield film is formed of a metal that is a passivation metal and a transition metal or an alloy containing the metal.Type: GrantFiled: March 24, 2021Date of Patent: May 24, 2022Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Tadashi Nomura, Shin Furuya, Toru Koidesawa, Motohiko Kusunoki, Tetsuya Oda
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Patent number: 10937760Abstract: A method for manufacturing chip package is disclosed. The method includes providing a wafer having an upper surface and a lower surface opposite thereto, in which the wafer comprises a plurality of conductive pads disposed on the upper surface; dicing the upper surface of the wafer to form a plurality of trenches; forming a patterned photoresist layer on the upper surface and in the trenches; forming a plurality of conductive bumps disposed correspondingly on the conductive pads; thinning the wafer from the lower surface toward the upper surface, such that the patterned photoresist layer in the trenches is exposed from the lower surface; forming an insulating layer under the lower surface; and dicing the patterned photoresist layer and the insulating layer along each trench to form a plurality of chip packages.Type: GrantFiled: May 7, 2019Date of Patent: March 2, 2021Assignee: COMCHIP TECHNOLOGY CO., LTD.Inventors: Chien-Chih Lai, Hung-Wen Lin
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Patent number: 9040352Abstract: A semiconductor device package having a cavity formed using film-assisted molding techniques is provided. Through the use of such techniques the cavity can be formed in specific locations in the molded package, such as on top of a device die mounted on the package substrate or a lead frame. In order to overcome cavity wall angular limitations introduced by conformability issues associated with film-assisted molding, a gel reservoir feature is formed so that gel used to protect components in the cavity does not come in contact with a lid covering the cavity or the junction between the lid and the package attachment region. The gel reservoir is used in conjunction with a formed level setting feature that controls the height of gel in the cavity. Benefits include decreased volume of the cavity, thereby decreasing an amount of gel-fill needed and thus reducing production cost of the package.Type: GrantFiled: June 28, 2012Date of Patent: May 26, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Shun Meen Kuo, Li Li
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Patent number: 9035446Abstract: Provided is a power module. The power module includes a power semiconductor chip. The power module further includes a case that accommodates the power semiconductor chip. A silicone gel seals the power semiconductor chip within the case. The silicone gel including a heat-resistant silicone gel containing 20 to 100 mass ppm of a metal complex comprising a metal selected from a group consisting of iron and platinum.Type: GrantFiled: April 25, 2014Date of Patent: May 19, 2015Assignee: Fuji Electric Co., Ltd.Inventors: Daisuke Kimijima, Yuji Ichimura
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Patent number: 9035472Abstract: In a semiconductor device, a conductor pattern is disposed in a position overlapped by a semiconductor chip in a thickness direction over the mounting surface (lower surface) of a wiring board. A solder resist film (insulating layer) covering the lower surface of the wiring board has apertures formed such that multiple portions of the conductor pattern are exposed. The conductor pattern has conductor apertures. The outlines of the apertures and the conductor apertures overlap with each other, in a plan view, respectively.Type: GrantFiled: November 15, 2013Date of Patent: May 19, 2015Assignee: Renesas Electronics CorporationInventor: Takaharu Nagasawa
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Patent number: 9018753Abstract: A method is described for making electronic modules includes molding onto a substrate panel a matrix panel defining a plurality of cavities, attaching semiconductor die to the substrate panel in respective cavities of the molded matrix panel, electrically connecting the semiconductor die to the substrate panel, affixing a cover to the molded matrix panel to form an electronic module assembly, mounting the electronic module assembly on a carrier tape, and separating the electronic module assembly into individual electronic modules. An electronic module is described which includes a substrate, a wall member molded onto the substrate, the molded wall member defining a cavity, at least one semiconductor die attached to the substrate in the cavity and electrically connected to the substrate, and a cover affixed to the molded wall member over the cavity.Type: GrantFiled: August 2, 2013Date of Patent: April 28, 2015Assignee: STMicroelectronics Pte LtdInventor: Wing Shenq Wong
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Patent number: 9018750Abstract: Disclosed is a package that includes a wafer substrate and a metal stack seed layer. The metal stack seed layer includes a titanium thin film outer layer. A resist layer is provided in contact with the titanium thin film outer layer of the metal stack seed layer, the resist layer forming circuitry. A method for manufacturing a package is further disclosed. A metal stack seed layer having a titanium thin film outer layer is formed. A resist layer is formed so as to be in contact with the titanium thin film outer layer of the metal stack seed layer, and circuitry is formed from the resist layer.Type: GrantFiled: August 10, 2012Date of Patent: April 28, 2015Assignee: Flipchip International, LLCInventors: Robert Forcier, Douglas Scott
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Patent number: 9013035Abstract: Methods and apparatuses for improved integrated circuit (IC) packages are described herein. In an aspect, an IC device package includes an IC die having a contact pad, where the contact pad is located on a hotspot of the IC die. The hotspot is thermally coupled to a thermal interconnect member. In an aspect, the package is encapsulated in a mold compound. In a further aspect, a heat spreader is attached to the mold compound, and is thermally coupled to the thermal interconnect member. In another aspect, a thermal interconnect member thermally is coupled between the heat spreader and the substrate.Type: GrantFiled: September 5, 2006Date of Patent: April 21, 2015Assignee: Broadcom CorporationInventors: Sam Ziqun Zhao, Rezaur Rahman Khan
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Patent number: 8993356Abstract: A method for constructing an electrical circuit that includes at least one semiconductor chip encapsulated with a potting compound is disclosed. The method includes applying a galvanic layer arrangement for forming an electrochemical element on an element of the electrical circuit including the at least one semiconductor chip.Type: GrantFiled: September 14, 2011Date of Patent: March 31, 2015Assignee: Robert Bosch GmbHInventors: Tjalf Pirk, Juergen Butz, Axel Franke, Frieder Haag, Heribert Weber, Arnim Hoechst, Sonja Knies
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Patent number: 8987921Abstract: A method for producing a component with at least one micro-structured or nano-structured element includes applying at least one micro-structured or nano-structured element to a carrier. The element has at least one area configure to make contact and the element is applied to the carrier such that the at least one area adjoins the carrier. The element is enveloped in an enveloping compound and the element-enveloping compound composite is detached from the carrier. A first layer comprising electrically conductive areas is applied to the side of the element-enveloping compound composite that previously adjoined the carrier. At least one passage is introduced into the enveloping compound. A conductor layer is applied to the surface of the passage and at least to a section of the layer comprising the first electrically conductive areas to generate a through contact, which enables space-saving contacting. A component is formed from the method.Type: GrantFiled: July 29, 2011Date of Patent: March 24, 2015Assignee: Robert Bosch GmbHInventors: Ulrike Scholz, Ralf Reichenbach
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Patent number: 8980696Abstract: A method of packaging a semiconductor die includes the use of an embedded ground plane or drop-in embedded unit. The embedded unit is a single, stand-alone unit with at least one cavity. The embedded unit is placed on and within an encapsulation area of a process mounting surface. The embedded unit may have different sizes and shapes and a number of different cavities that can be placed in a predetermined position on a substrate, panel or tape during processing of semiconductor dies that are embedded into redistributed chip package (RCP) or wafer level package (WFL) panels. The embedded unit provides the functionality and design flexibility to run a number of embedded units and semiconductor dies or components having different sizes and dimensions in a single processing panel or batch and reduces die drift, movement or skew during encapsulation and post-encapsulation cure.Type: GrantFiled: November 9, 2011Date of Patent: March 17, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Dominic Koey Poh Meng, Zhiwei Gong, Kesvakumar V. C. Muniandy, Weng Foong Yap
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Patent number: 8969140Abstract: A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer.Type: GrantFiled: August 14, 2013Date of Patent: March 3, 2015Assignee: Intel CorporationInventors: Robert L. Sankman, John S. Guzek
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Patent number: 8963345Abstract: An encapsulation device including two casings made of a flexible polymer material, each delimiting a sealed space, and at least one hydrophobic material filling each of the casings, the casings being stacked and sealingly interconnected at peripheral edges thereof, a sealed space then being defined between the two casings for receiving a device to be encapsulated.Type: GrantFiled: December 9, 2010Date of Patent: February 24, 2015Assignee: Commissariat à l'énergie atomique et aux énergies alternativesInventors: Stephane Cros, Nicole Alberola, Jean-Paul Garandet, Arnaud Morlier
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Patent number: 8963195Abstract: A lighting element, comprising: a first substrate; a first and second conductive elements located on the first substrate; a light-emitting element having first and second contacts that are both on a first surface of the light-emitting element, the first contact being electrically connected to the first conductive element, the second contact being electrically connected to the second conductive element, and the light-emitting element emitting light from a second surface opposite the first surface; a top layer adjacent to the second surface; and an affixing layer located between the first substrate and the top layer, the affixing layer affixing the top layer to the first substrate; and a heat spreading layer having a third surface and a fourth surface opposite the third surface, the heat spreading layer being affixed beneath the first flexible substrate at the third surface, wherein the flexible top layer is substantially transparent to light.Type: GrantFiled: July 23, 2013Date of Patent: February 24, 2015Assignee: Grote Industries, LLCInventors: Timothy Webster Brooks, Scott J. Jones, Martin J. Marx, Cesar Perez-Bolivar, James E. Roberts, George M. Richardson, II
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Patent number: 8956921Abstract: A method of molding a semiconductor package includes coating liquid molding resin or disposing solid molding resin on a top surface of a semiconductor chip arranged on a substrate. The solid molding resin may include powdered molding resin or sheet-type molding resin. In a case where liquid molding resin is coated on the top surface of the semiconductor chip, the substrate is mounted between a lower molding and an upper molding, and then melted molding resin is filled in a space between the lower molding and the upper molding. In a case where the solid molding resin is disposed on the top surface of the semiconductor chip, the substrate is mounted on a lower mold and then the solid molding resin is heated and melts into liquid molding resin having flowability. An upper mold is mounted on the lower mold, and melted molding resin is filled in a space between the lower molding and the upper molding.Type: GrantFiled: March 15, 2013Date of Patent: February 17, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-young Ko, Jae-yong Park, Heui-seog Kim, Ho-geon Song
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Patent number: 8957489Abstract: A component assembly including a carrier element including a first contact face and a semiconductor component disposed on the carrier element, wherein the semiconductor component includes a second contact face. The component assembly further includes a contact-making bonding wire, wherein one end of the contact-making bonding wire is connected to the first contact face and a second end of the contact-making bonding wire is connected to the second contact face. The component assembly includes a flow stop bonding wire positioned on the second contact face, wherein the flow stop bonding wire defines on the second contact face a first zone and a second zone. An encapsulation material is applied from the first zone to the first contact face so as to define an encapsulation for the flow stop bonding wire, wherein the flow stop bonding wire prevents an uncontrolled flow of the encapsulation material into the second zone.Type: GrantFiled: March 3, 2009Date of Patent: February 17, 2015Assignee: Dr. Johannes Heidenhain GmbHInventor: Roman Angerer
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Patent number: 8946886Abstract: An electronic component package includes a substrate having a first surface, an electronic component mounted to the substrate, traces on the first surface, a terminal on the first surface, and a solder mask on the first surface. The solder mask includes a solder mask opening exposing the terminal. An electrically conductive coating and/or conductive coating feature is formed on the solder mask and extends into the solder mask opening to contact and be electrically connected to the terminal. The conductive coating may be grounded to shield the electronic component from electromagnetic interference (EMI). Further, the conductive coating provides a ground plane for the traces facilitating impedance matching of signals on the traces. In addition, the conductive coating has a high thermal conductivity thus enhancing heat dissipation from the electronic component.Type: GrantFiled: May 13, 2010Date of Patent: February 3, 2015Inventors: Ruben Fuentes, August Joseph Miller, Jr.
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Patent number: 8946759Abstract: Disclosed is an organic light emitting display device which prevents or inhibits external gas, such as, oxygen or moisture, from penetrating into a display unit and reinforces a mechanical strength by providing a first sealant and a second sealant. The organic light emitting display device may include: a first substrate; a display unit on the first substrate; a second substrate covering the display unit; a first sealant adhering the first substrate to the second substrate; and a second sealant around the first sealant, the second sealant sealing the first substrate and the second substrate. A filler may be included in the second sealant, and a particle size of the filler may be larger than a gap between the first substrate and the second substrate.Type: GrantFiled: September 12, 2012Date of Patent: February 3, 2015Assignee: Samsung-Display Co., Ltd.Inventors: Jung Woo Moon, Hyun Joon Oh
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Patent number: 8916423Abstract: A method of manufacturing a semiconductor device includes: forming a first electrode on a first semiconductor substrate; coating the semiconductor substrate with an insulating material having a first viscosity at a first temperature, having a second viscosity lower than the first viscosity at a second temperature higher than the first temperature, and having a third viscosity higher than the second viscosity at a third temperature higher than the second temperature; and forming a first insulating film by curing the insulating material. In this method, the forming the first insulating film includes: bringing the insulating material to the second viscosity by heating the insulating material under a first condition; and bringing the insulating material to the third viscosity by heating the insulating material under a second condition. The first condition and the second condition are different in their temperature rising rate.Type: GrantFiled: March 8, 2013Date of Patent: December 23, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Tamotsu Owada, Hikaru Ohira, Hirosato Ochimizu
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Patent number: 8907437Abstract: A current sensor packaged in an integrated circuit package to include a magnetic field sensing circuit, a current conductor and an insulator that meets the safety isolation requirements for reinforced insulation under the UL 60950-1 Standard is presented. The insulator is provided as an insulation structure having at least two layers of thin sheet material. The insulation structure is dimensioned so that plastic material forming a molded plastic body of the package provides a reinforced insulation. According to one embodiment, the insulation structure has two layers of insulating tape. Each insulating tape layer includes a polyimide film and adhesive. The insulation structure and the molded plastic body can be constructed to achieve at least a 500 VRMS working voltage rating.Type: GrantFiled: July 22, 2011Date of Patent: December 9, 2014Assignee: Allegro Microsystems, LLCInventors: Shaun D. Milano, Weihua Chen
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Patent number: 8896135Abstract: Disclosed is an encapsulation film. An inorganic oxide film is formed on an organic sealing layer by an atomic layer deposition (ALD) to form the encapsulation film, wherein the organic sealing layer is a polymer containing hydrophilic groups. The organic sealing layer and the inorganic oxide layer have covalent bondings therebetween. The encapsulation film can solve the moisture absorption problem of conventional organic sealing layers, thereby being suitable for use as a package of optoelectronic devices.Type: GrantFiled: January 4, 2011Date of Patent: November 25, 2014Assignee: Industrial Technology Research InstituteInventors: Ching-Chiun Wang, Kang-Feng Lee, Feng-Yu Tsai, Ming Horn Zheng, Chih-Yung Huang, Shih-Chin Lin, Jen-Rong Huang
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Patent number: 8890316Abstract: A method and structures are provided for implementing decoupling capacitors within a DRAM TSV stack. A DRAM is formed with a plurality of TSVs extending completely through the substrate and filled with a conducting material. A layer of glass is grown on both the top and bottom of the DRAM providing an insulator. A layer of metal is grown on each glass layer providing a conductor. The metal and glass layers are etched through to TSVs with a gap provided around the perimeter of via pads. A respective solder ball is formed on the TSVs to connect to another DRAM chip in the DRAM TSV stack. The metal layers are connected to at least one TSV by one respective solder ball and are connected to a voltage source and a dielectric is inserted between the metal layers in the DRAM TSV stack to complete the decoupling capacitor.Type: GrantFiled: January 8, 2014Date of Patent: November 18, 2014Assignee: International Business Machines CorporationInventors: Joab D. Henderson, Kyu-hyoun Kim, Warren E. Maule, Kenneth L. Wright
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Patent number: 8872357Abstract: An anisotropic conductive film composition for bonding a semiconductor device, the composition including: a binder system including a urethane resin having a glass transition temperature of about 100° C. or higher, a radical polymerizable compound, an organic peroxide, and conductive particles.Type: GrantFiled: November 7, 2012Date of Patent: October 28, 2014Assignee: Cheil Industries, Inc.Inventor: Do Hyun Park
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Patent number: 8852999Abstract: A system-in-a-package based flash memory card including an integrated circuit package occupying a small overall area within the card and cut to conform to the shape of a lid for the card. An integrated circuit may be cut from a panel into a shape that fits within and conforms to the shape of lids for a finished memory card, such as for example an SD Card. The integrated circuit package may be a system-in-a-package, a multi-chip module, or other arrangement where a complete electronic system is formed in a single package.Type: GrantFiled: September 19, 2011Date of Patent: October 7, 2014Assignee: SanDisk Technologies Inc.Inventors: Hem Takiar, Robert C. Miller, Warren Middlekauff, Michael W. Patterson, Shrikar Bhagath
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Patent number: 8847372Abstract: An exposed die overmolded flip chip package includes a substrate. A die is flip chip mounted to an upper surface of the substrate. The package further includes a mold cap filling a space between an active surface of the die and the upper surface of the substrate. The mold cap includes a principal surface, sidewalls extending from the upper surface of the substrate to the principal surface, an annular surface coplanar with the inactive surface of the die and extending outward from a peripheral edge of the inactive surface of the die, and protruding surfaces extending between the principal surface and the annular surface. The mold cap does not cover the inactive surface of the die such that heat transfer from the die to the ambient environment is maximized and the package thickness is minimized.Type: GrantFiled: August 21, 2013Date of Patent: September 30, 2014Inventors: Robert Francis Darveaux, Michael Barrow, Miguel Angel Jimarez, Jae Dong Kim, Dae Keun Park, Ki Wook Lee, Ju Hoon Yoon
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Patent number: 8846456Abstract: A substrate which has at least one component, such as a semiconductor chip, arranged on it is manufactured from a film made of plastic material laminated onto a surface of the substrate and of the at least one component, where the surface has at least one contact area. First, the film to be laminated onto the surface of the substrate and the at least one component, or a film composite including the film, is arranged in a chamber such that the chamber is split by the film or film composite into a first chamber section and a second chamber section, which is isolated from the first chamber section so as to be gastight. A higher atmospheric pressure is provided or produced in the first chamber section than in the second chamber section; and contact is made between the surface of the substrate arranged in the second chamber section and the at least one component and the film or the film composite, which contact brings about the lamination of the film onto the surface.Type: GrantFiled: August 29, 2007Date of Patent: September 30, 2014Assignee: Siemens AktiengesellschaftInventor: Karl Weidner
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Patent number: 8841782Abstract: An integrated circuit package system includes: providing a substrate; forming a conductive layer over the substrate; forming a mold gate layer having an organic material without polymerization over the conductive layer; and attaching an integrated circuit over the substrate adjacent the mold gate layer.Type: GrantFiled: August 14, 2008Date of Patent: September 23, 2014Assignee: STATS ChipPAC Ltd.Inventors: DaeWook Yang, Youngcheol Kim, Tae Keun Lee
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Patent number: 8791561Abstract: A support substrate includes a first surface and a second surface located above the level of the first surface. Chips are mounted on the first surface. A first insulating film is disposed over each chip. First conductive plugs are connected to the chip extending through each first insulating film. Filler material made of resin filling a space between chips. Wirings are disposed over the first insulating film and the filler material for interconnecting different chips. The second surface, an upper surface of the first insulating film and an upper surface of the filler material are located at the same level.Type: GrantFiled: February 11, 2013Date of Patent: July 29, 2014Assignees: Fujitsu Limited, Shinko Electric Industries Co., Ltd.Inventors: Sadahiro Kishii, Tsuyoshi Kanki, Yoshihiro Nakata, Yasushi Kobayashi, Masato Tanaka, Akio Rokugawa
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Patent number: 8786059Abstract: A structure and method for producing the same is disclosed. The structure includes an organic passivation layer with solids suspended therein. Preferential etch to remove a portion of the organic material and expose portions of such solids creates enhanced surface roughness, which provides a significant advantage with respect to adhesion of that passivation layer to the packaging underfill material.Type: GrantFiled: May 10, 2012Date of Patent: July 22, 2014Assignee: International Business Machines CorporationInventors: Alexandre Blander, Jon A Casey, Timothy H Daubenspeck, Ian D Melville, Jennifer V Muncy, Marie-Claude Paquet
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Patent number: 8786102Abstract: A semiconductor device includes a first wiring board, a second semiconductor chip, and a second seal. The first wiring board includes a first substrate, a first semiconductor chip, and a first seal. The first semiconductor chip is disposed on the first substrate. The first seal is disposed on the first substrate. The first seal surrounds the first semiconductor chip. The first seal has the same thickness as the first semiconductor chip. The second semiconductor chip is stacked over the first semiconductor chip. The first semiconductor chip is between the second semiconductor chip and the first substrate. The second semiconductor chip is greater in size in plan view than the first semiconductor chip. The second seal seals at least a first gap between the first semiconductor chip and the second semiconductor chip.Type: GrantFiled: October 10, 2013Date of Patent: July 22, 2014Assignee: PS4 Luxco S.A.R.L.Inventors: Masanori Yoshida, Fumitomo Watanabe
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Patent number: 8766416Abstract: A semiconductor package includes a substrate having opposite first and second surfaces and a ground layer therein. Further, the second surface has at least a recessed portion for exposing portions of the ground layer. The semiconductor package further includes a semiconductor chip disposed on the first surface of the substrate; an encapsulant formed on the first surface of the substrate for encapsulating the semiconductor chip; and a metal layer covering the encapsulant and the substrate and extending to the recessed portion for electrically connecting the ground layer. As such, the space for circuit layout is increased and the circuit layout flexibility is improved.Type: GrantFiled: April 27, 2012Date of Patent: July 1, 2014Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Tsung-Hsien Hsu, Hao-Ju Fang, Hsin-Lung Chung
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Patent number: 8749031Abstract: According to one embodiment, a semiconductor device includes a semiconductor device body and an insulating adhesive layer. The semiconductor device body is formed with a square plate shape and has an element portion provided on a first major surface. The insulating adhesive layer is provided to cover a second major surface of the semiconductor device body and one or two of four side faces of the semiconductor device body.Type: GrantFiled: March 18, 2011Date of Patent: June 10, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Ryoji Matsushima
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Patent number: 8749074Abstract: Embodiments include but are not limited to apparatuses and systems including semiconductor packages, e.g. memory packages, having an interposer including at least one topological feature, such as a depression in a surface of the interposer, a die coupled to the surface of the interposer, and an encapsulant material formed over the die and the interposer, and disposed in the at least one depression to resist movement of the encapsulant material relative to the interposer. Other embodiments may be described and claimed.Type: GrantFiled: November 30, 2009Date of Patent: June 10, 2014Assignee: Micron Technology, Inc.Inventors: Steven Eskildsen, Aravind Ramamoorthy
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Patent number: 8749075Abstract: An integrated circuit is provided. The integrated circuit includes: a chip and encapsulation material covering at least three sides of the chip, the encapsulation material being formed from adhesive material. The integrated circuit includes a carrier adhered to the chip by means of the encapsulation material.Type: GrantFiled: September 4, 2012Date of Patent: June 10, 2014Assignee: Infineon Technologies AGInventors: Joachim Mahler, Lukas Ossowski, Khalil Hosseini, Ivan Nikitin
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Patent number: 8749056Abstract: A module and a method for manufacturing a module are disclosed. An embodiment of a module includes a first semiconductor device, a frame arranged on the first semiconductor device, the frame including a cavity, and a second semiconductor device arranged on the frame wherein the second semiconductor device seals the cavity.Type: GrantFiled: May 26, 2011Date of Patent: June 10, 2014Assignee: Infineon Technologies AGInventors: Daniel Kehrer, Stefan Martens, Tze Yang Hin, Helmut Wietschorke, Horst Theuss, Beng Keh See, Ulrich Krumbein
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Patent number: 8749055Abstract: An electronic device includes: a substrate having first and second surfaces, wherein the first surface is opposite to the second surface; a first electronic element mounted on the first surface of the substrate; a second electronic element mounted on the second surface of the substrate; and a resin mold sealing the first electronic element and the first surface of the substrate. The resin mold further seals the second electronic element on the second surface of the substrate. The second surface of the substrate has a portion, which is exposed from the resin mold. The second electronic element is not disposed on the portion of the second surface.Type: GrantFiled: April 18, 2012Date of Patent: June 10, 2014Assignee: DENSO CORPORATIONInventors: Tetsuto Yamagishi, Tohru Nomura, Norihisa Imaizumi, Yasutomi Asai
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Patent number: 8729693Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a first device having a first exposed side and a first inward side; connecting a second device having a second exposed side and a second inward side facing the first inward side to the first device, the second device having planar dimensions less than planar dimensions of the first device; connecting a system connector to a perimeter of the first inward side, the system connector having an exposed leg partially vertical and an exposed foot partially horizontal; and applying an encapsulant exposing the first exposed side, the second exposed side, the exposed leg, and the exposed foot, the exposed leg offset from the encapsulant, the exposed foot on an end of the system connector opposite the first device.Type: GrantFiled: September 23, 2009Date of Patent: May 20, 2014Assignee: Stats Chippac Ltd.Inventors: Zigmund Ramirez Camacho, Arnel Senosa Trasporto, Lionel Chien Hui Tay, Henry Descalzo Bathan
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Publication number: 20140124916Abstract: Presented herein are a package-on-package device having a molded underfill and a method for forming the same, the method comprising applying a package mount mounting a die to the first side of a carrier package. A molded underfill may be applied first side of the carrier package, and be in contact with a portion of the package mount a portion of a sidewall of the die. A top package having at least one land may be mounted to the first side of the carrier package above the die, and, optionally separated from the top of the die. The package mount may be coined prior to, during or after applying the molded underfill to optionally be level with the underfill surface. The underfill region contacting the package mount may be below or above the surface of the underfill region contacting the die sidewall.Type: ApplicationFiled: November 2, 2012Publication date: May 8, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Hua Yu, Chien-Hsun Lee, Jung Wei Cheng, Tsung-Ding Wang, Ming-Da Cheng, Yung Ching Chen
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Patent number: 8716875Abstract: A semiconductor package includes a substrate having a first surface, a second surface that is opposite to the first surface, and an opening formed between the first surface of the substrate and the second surface of the substrate. One or more bonding wires electrically couple a first surface of a semiconductor die included in the semiconductor package to the first surface of the substrate through an opening of the substrate. A first electrically insulative structure is disposed to substantially fill an area between the first surface of the semiconductor die, the second surface of the substrate, and one or more interconnect bumps that electrically couple the semiconductor die to the substrate. The first electrically insulative structure substantially encapsulates the one or more bonding wires and substantially fills the opening of the substrate.Type: GrantFiled: January 18, 2013Date of Patent: May 6, 2014Assignee: Marvell World Trade Ltd.Inventor: Sehat Sutardja
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Patent number: 8697567Abstract: A method and structures are provided for implementing decoupling capacitors within a DRAM TSV stack. A DRAM is formed with a plurality of TSVs extending completely through the substrate and filled with a conducting material. A layer of glass is grown on both the top and bottom of the DRAM providing an insulator. A layer of metal is grown on each glass layer providing a conductor. The metal and glass layers are etched through to TSVs with a gap provided around the perimeter of via pads. A respective solder ball is formed on the TSVs to connect to another DRAM chip in the DRAM TSV stack. The metal layers are connected to at least one TSV by one respective solder ball and are connected to a voltage source and a dielectric is inserted between the metal layers in the DRAM TSV stack to complete the decoupling capacitor.Type: GrantFiled: May 22, 2012Date of Patent: April 15, 2014Assignee: International Business Machines CorporationInventors: Joab D. Henderson, Kyu-hyoun Kim, Warren E. Maule, Kenneth L. Wright
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Publication number: 20140091454Abstract: A semiconductor device includes a semiconductor die. An encapsulant is formed around the semiconductor die. A build-up interconnect structure is formed over a first surface of the semiconductor die and encapsulant. A first supporting layer is formed over a second surface of the semiconductor die as a supporting substrate or silicon wafer disposed opposite the build-up interconnect structure. A second supporting layer is formed over the first supporting layer an includes a fiber enhanced polymer composite material comprising a footprint including an area greater than or equal to an area of a footprint of the semiconductor die. The semiconductor die comprises a thickness less than 450 micrometers (?m). The thickness of the semiconductor die is at least 1 ?m less than a difference between a total thickness of the semiconductor device and a thickness of the build-up interconnect structure and the second supporting layer.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Applicant: STATS ChipPAC, Ltd.Inventors: Yaojian Lin, Kang Chen, Yu Gu
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Publication number: 20140061932Abstract: A package-on-package (“PoP”) structure and a method of forming are provided. The PoP structure may be formed by forming a first set of electrical connections on a first substrate. A first material may be applied to the first set of electrical connections. A second substrate may be provided having a second set of electrical connections formed thereon. The first set of electrical connections of the first substrate having the epoxy flux applied may be contacted to the second electrical connections of the second substrate. A reflow process may be performed to electrically connect the first substrate to the second substrate. The epoxy flux applied to the first electrical connections of the first substrate may prohibit electrical bridges or shorts from forming during the reflow process.Type: ApplicationFiled: September 5, 2012Publication date: March 6, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Meng-Tse Chen, Yi-Da Tsai, Xi-Hong Chen, Tao-Hua Lee, Wei-Yu Chen, Ming-Da Cheng, Chung-Shi Liu
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Patent number: 8659129Abstract: A semiconductor device in accordance with an embodiment comprises a semiconductor chip; a die pad having a chip mount surface for mounting the semiconductor chip; first leads electrically connected to the semiconductor chip; a thermosetting resin part for securing end parts of the first leads to the die pad; and a thermoplastic resin part for sealing the semiconductor chip, the die pad, and the thermosetting resin part.Type: GrantFiled: March 14, 2012Date of Patent: February 25, 2014Assignee: Sumitomo Electric Industries, Ltd.Inventor: Jiro Shinkai
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Patent number: 8648479Abstract: According to the present invention, an epoxy resin composition for semiconductor encapsulant including (A) an epoxy resin, (B) a curing agent, (C) an inorganic filler, and (D) a compound in which a copolymer of a 1-alkene having 5 to 80 carbon atoms and maleic anhydride is esterified with an alcohol having 5 to 25 carbon atoms in the presence of a compound represented by General Formula (1), wherein R1 in General Formula (1) is selected from the group consisting of an alkyl group having 1 to 5 carbon atoms, a halogenated alkyl group having 1 to 5 carbon atoms, and an aromatic group having 6 to 10 carbon atoms is provided.Type: GrantFiled: May 25, 2011Date of Patent: February 11, 2014Assignee: Sumitomo Bakelite Co., Ltd.Inventor: Jun-ichi Tabei
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Publication number: 20140035154Abstract: A chip package is provided, the chip package including: a chip including at least one contact pad formed on a chip front side; an encapsulation material at least partially surrounding the chip and covering the at least one contact pad; and at least one electrical interconnect formed through the encapsulation material, wherein the at least one electrical interconnect is configured to electrically redirect the at least one contact pad from a chip package first side at the chip front side to at least one solder structure formed over a chip package second side at a chip back side.Type: ApplicationFiled: August 2, 2012Publication date: February 6, 2014Applicant: Infineon Technologies AGInventors: Ottmar Geitner, Walter Hartner, Maciej Wojnowski, Ulrich Wachter, Michael Bauer, Andreas Stueckjuergen
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Patent number: 8643199Abstract: Dendrimer/hyperbranched materials are combined with polyimide to form a low CTE material for use as a dielectric substrate layer or an underfill. In the alternative, ruthenium carbene complexes are used to catalyze ROMP cross-linking reactions in polyimides to produce a class of cross-linkable, thermal and mechanical stable material for use as a dielectric substrate or underfill. In another alternative, dendrimers/hyperbranched materials are synthesized by different methods to produce low viscosity, high Tg, fast curing, mechanically and chemically stable materials for imprinting applications.Type: GrantFiled: January 28, 2009Date of Patent: February 4, 2014Assignee: Intel CorporationInventors: Stephen E. Lehman, Jr., James C. Matayabas, Jr., Saikumar Jayaraman
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Patent number: 8637980Abstract: An assembly includes an integrated circuit die coupled to another component of the assembly with an alkali silicate glass material. The alkali silicate material may include particles for modifying the thermal, mechanical, and/or electrical characteristics of the material.Type: GrantFiled: December 18, 2007Date of Patent: January 28, 2014Assignee: Rockwell Collins, Inc.Inventors: Nathan P. Lower, Alan P. Boone, Ross K. Wilcoxon
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Publication number: 20140021638Abstract: A embedded integrated circuit package is provided, the embedded integrated circuit package including: at least one chip arranged over a chip carrier, the at least one chip including a plurality of chip contact pads; encapsulation material formed over the chip carrier and at least partially surrounding the at least one chip; a plurality of electrical interconnects formed through the encapsulation material, wherein each electrical interconnect is electrically connected to a chip contact pad; and a structure formed between the electrical interconnects of the embedded integrated circuit package, wherein the structure increases the creepage resistance between the electrical interconnects.Type: ApplicationFiled: July 18, 2012Publication date: January 23, 2014Applicant: INFINEON TECHNOLOGIES AGInventors: Joachim Mahler, Edward Fuergut, Khalil Hosseini, Georg Meyer-Berg