Encapsulations, E.g., Encapsulating Layers, Coatings, E.g., For Protection (epo) Patents (Class 257/E23.116)
  • Patent number: 10937760
    Abstract: A method for manufacturing chip package is disclosed. The method includes providing a wafer having an upper surface and a lower surface opposite thereto, in which the wafer comprises a plurality of conductive pads disposed on the upper surface; dicing the upper surface of the wafer to form a plurality of trenches; forming a patterned photoresist layer on the upper surface and in the trenches; forming a plurality of conductive bumps disposed correspondingly on the conductive pads; thinning the wafer from the lower surface toward the upper surface, such that the patterned photoresist layer in the trenches is exposed from the lower surface; forming an insulating layer under the lower surface; and dicing the patterned photoresist layer and the insulating layer along each trench to form a plurality of chip packages.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: March 2, 2021
    Assignee: COMCHIP TECHNOLOGY CO., LTD.
    Inventors: Chien-Chih Lai, Hung-Wen Lin
  • Patent number: 9040352
    Abstract: A semiconductor device package having a cavity formed using film-assisted molding techniques is provided. Through the use of such techniques the cavity can be formed in specific locations in the molded package, such as on top of a device die mounted on the package substrate or a lead frame. In order to overcome cavity wall angular limitations introduced by conformability issues associated with film-assisted molding, a gel reservoir feature is formed so that gel used to protect components in the cavity does not come in contact with a lid covering the cavity or the junction between the lid and the package attachment region. The gel reservoir is used in conjunction with a formed level setting feature that controls the height of gel in the cavity. Benefits include decreased volume of the cavity, thereby decreasing an amount of gel-fill needed and thus reducing production cost of the package.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: May 26, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Shun Meen Kuo, Li Li
  • Patent number: 9035472
    Abstract: In a semiconductor device, a conductor pattern is disposed in a position overlapped by a semiconductor chip in a thickness direction over the mounting surface (lower surface) of a wiring board. A solder resist film (insulating layer) covering the lower surface of the wiring board has apertures formed such that multiple portions of the conductor pattern are exposed. The conductor pattern has conductor apertures. The outlines of the apertures and the conductor apertures overlap with each other, in a plan view, respectively.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: May 19, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Takaharu Nagasawa
  • Patent number: 9035446
    Abstract: Provided is a power module. The power module includes a power semiconductor chip. The power module further includes a case that accommodates the power semiconductor chip. A silicone gel seals the power semiconductor chip within the case. The silicone gel including a heat-resistant silicone gel containing 20 to 100 mass ppm of a metal complex comprising a metal selected from a group consisting of iron and platinum.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: May 19, 2015
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Daisuke Kimijima, Yuji Ichimura
  • Patent number: 9018750
    Abstract: Disclosed is a package that includes a wafer substrate and a metal stack seed layer. The metal stack seed layer includes a titanium thin film outer layer. A resist layer is provided in contact with the titanium thin film outer layer of the metal stack seed layer, the resist layer forming circuitry. A method for manufacturing a package is further disclosed. A metal stack seed layer having a titanium thin film outer layer is formed. A resist layer is formed so as to be in contact with the titanium thin film outer layer of the metal stack seed layer, and circuitry is formed from the resist layer.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: April 28, 2015
    Assignee: Flipchip International, LLC
    Inventors: Robert Forcier, Douglas Scott
  • Patent number: 9018753
    Abstract: A method is described for making electronic modules includes molding onto a substrate panel a matrix panel defining a plurality of cavities, attaching semiconductor die to the substrate panel in respective cavities of the molded matrix panel, electrically connecting the semiconductor die to the substrate panel, affixing a cover to the molded matrix panel to form an electronic module assembly, mounting the electronic module assembly on a carrier tape, and separating the electronic module assembly into individual electronic modules. An electronic module is described which includes a substrate, a wall member molded onto the substrate, the molded wall member defining a cavity, at least one semiconductor die attached to the substrate in the cavity and electrically connected to the substrate, and a cover affixed to the molded wall member over the cavity.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: April 28, 2015
    Assignee: STMicroelectronics Pte Ltd
    Inventor: Wing Shenq Wong
  • Patent number: 9013035
    Abstract: Methods and apparatuses for improved integrated circuit (IC) packages are described herein. In an aspect, an IC device package includes an IC die having a contact pad, where the contact pad is located on a hotspot of the IC die. The hotspot is thermally coupled to a thermal interconnect member. In an aspect, the package is encapsulated in a mold compound. In a further aspect, a heat spreader is attached to the mold compound, and is thermally coupled to the thermal interconnect member. In another aspect, a thermal interconnect member thermally is coupled between the heat spreader and the substrate.
    Type: Grant
    Filed: September 5, 2006
    Date of Patent: April 21, 2015
    Assignee: Broadcom Corporation
    Inventors: Sam Ziqun Zhao, Rezaur Rahman Khan
  • Patent number: 8993356
    Abstract: A method for constructing an electrical circuit that includes at least one semiconductor chip encapsulated with a potting compound is disclosed. The method includes applying a galvanic layer arrangement for forming an electrochemical element on an element of the electrical circuit including the at least one semiconductor chip.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: March 31, 2015
    Assignee: Robert Bosch GmbH
    Inventors: Tjalf Pirk, Juergen Butz, Axel Franke, Frieder Haag, Heribert Weber, Arnim Hoechst, Sonja Knies
  • Patent number: 8987921
    Abstract: A method for producing a component with at least one micro-structured or nano-structured element includes applying at least one micro-structured or nano-structured element to a carrier. The element has at least one area configure to make contact and the element is applied to the carrier such that the at least one area adjoins the carrier. The element is enveloped in an enveloping compound and the element-enveloping compound composite is detached from the carrier. A first layer comprising electrically conductive areas is applied to the side of the element-enveloping compound composite that previously adjoined the carrier. At least one passage is introduced into the enveloping compound. A conductor layer is applied to the surface of the passage and at least to a section of the layer comprising the first electrically conductive areas to generate a through contact, which enables space-saving contacting. A component is formed from the method.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: March 24, 2015
    Assignee: Robert Bosch GmbH
    Inventors: Ulrike Scholz, Ralf Reichenbach
  • Patent number: 8980696
    Abstract: A method of packaging a semiconductor die includes the use of an embedded ground plane or drop-in embedded unit. The embedded unit is a single, stand-alone unit with at least one cavity. The embedded unit is placed on and within an encapsulation area of a process mounting surface. The embedded unit may have different sizes and shapes and a number of different cavities that can be placed in a predetermined position on a substrate, panel or tape during processing of semiconductor dies that are embedded into redistributed chip package (RCP) or wafer level package (WFL) panels. The embedded unit provides the functionality and design flexibility to run a number of embedded units and semiconductor dies or components having different sizes and dimensions in a single processing panel or batch and reduces die drift, movement or skew during encapsulation and post-encapsulation cure.
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: March 17, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Dominic Koey Poh Meng, Zhiwei Gong, Kesvakumar V. C. Muniandy, Weng Foong Yap
  • Patent number: 8969140
    Abstract: A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: March 3, 2015
    Assignee: Intel Corporation
    Inventors: Robert L. Sankman, John S. Guzek
  • Patent number: 8963345
    Abstract: An encapsulation device including two casings made of a flexible polymer material, each delimiting a sealed space, and at least one hydrophobic material filling each of the casings, the casings being stacked and sealingly interconnected at peripheral edges thereof, a sealed space then being defined between the two casings for receiving a device to be encapsulated.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: February 24, 2015
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventors: Stephane Cros, Nicole Alberola, Jean-Paul Garandet, Arnaud Morlier
  • Patent number: 8963195
    Abstract: A lighting element, comprising: a first substrate; a first and second conductive elements located on the first substrate; a light-emitting element having first and second contacts that are both on a first surface of the light-emitting element, the first contact being electrically connected to the first conductive element, the second contact being electrically connected to the second conductive element, and the light-emitting element emitting light from a second surface opposite the first surface; a top layer adjacent to the second surface; and an affixing layer located between the first substrate and the top layer, the affixing layer affixing the top layer to the first substrate; and a heat spreading layer having a third surface and a fourth surface opposite the third surface, the heat spreading layer being affixed beneath the first flexible substrate at the third surface, wherein the flexible top layer is substantially transparent to light.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: February 24, 2015
    Assignee: Grote Industries, LLC
    Inventors: Timothy Webster Brooks, Scott J. Jones, Martin J. Marx, Cesar Perez-Bolivar, James E. Roberts, George M. Richardson, II
  • Patent number: 8956921
    Abstract: A method of molding a semiconductor package includes coating liquid molding resin or disposing solid molding resin on a top surface of a semiconductor chip arranged on a substrate. The solid molding resin may include powdered molding resin or sheet-type molding resin. In a case where liquid molding resin is coated on the top surface of the semiconductor chip, the substrate is mounted between a lower molding and an upper molding, and then melted molding resin is filled in a space between the lower molding and the upper molding. In a case where the solid molding resin is disposed on the top surface of the semiconductor chip, the substrate is mounted on a lower mold and then the solid molding resin is heated and melts into liquid molding resin having flowability. An upper mold is mounted on the lower mold, and melted molding resin is filled in a space between the lower molding and the upper molding.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-young Ko, Jae-yong Park, Heui-seog Kim, Ho-geon Song
  • Patent number: 8957489
    Abstract: A component assembly including a carrier element including a first contact face and a semiconductor component disposed on the carrier element, wherein the semiconductor component includes a second contact face. The component assembly further includes a contact-making bonding wire, wherein one end of the contact-making bonding wire is connected to the first contact face and a second end of the contact-making bonding wire is connected to the second contact face. The component assembly includes a flow stop bonding wire positioned on the second contact face, wherein the flow stop bonding wire defines on the second contact face a first zone and a second zone. An encapsulation material is applied from the first zone to the first contact face so as to define an encapsulation for the flow stop bonding wire, wherein the flow stop bonding wire prevents an uncontrolled flow of the encapsulation material into the second zone.
    Type: Grant
    Filed: March 3, 2009
    Date of Patent: February 17, 2015
    Assignee: Dr. Johannes Heidenhain GmbH
    Inventor: Roman Angerer
  • Patent number: 8946886
    Abstract: An electronic component package includes a substrate having a first surface, an electronic component mounted to the substrate, traces on the first surface, a terminal on the first surface, and a solder mask on the first surface. The solder mask includes a solder mask opening exposing the terminal. An electrically conductive coating and/or conductive coating feature is formed on the solder mask and extends into the solder mask opening to contact and be electrically connected to the terminal. The conductive coating may be grounded to shield the electronic component from electromagnetic interference (EMI). Further, the conductive coating provides a ground plane for the traces facilitating impedance matching of signals on the traces. In addition, the conductive coating has a high thermal conductivity thus enhancing heat dissipation from the electronic component.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: February 3, 2015
    Inventors: Ruben Fuentes, August Joseph Miller, Jr.
  • Patent number: 8946759
    Abstract: Disclosed is an organic light emitting display device which prevents or inhibits external gas, such as, oxygen or moisture, from penetrating into a display unit and reinforces a mechanical strength by providing a first sealant and a second sealant. The organic light emitting display device may include: a first substrate; a display unit on the first substrate; a second substrate covering the display unit; a first sealant adhering the first substrate to the second substrate; and a second sealant around the first sealant, the second sealant sealing the first substrate and the second substrate. A filler may be included in the second sealant, and a particle size of the filler may be larger than a gap between the first substrate and the second substrate.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: February 3, 2015
    Assignee: Samsung-Display Co., Ltd.
    Inventors: Jung Woo Moon, Hyun Joon Oh
  • Patent number: 8916423
    Abstract: A method of manufacturing a semiconductor device includes: forming a first electrode on a first semiconductor substrate; coating the semiconductor substrate with an insulating material having a first viscosity at a first temperature, having a second viscosity lower than the first viscosity at a second temperature higher than the first temperature, and having a third viscosity higher than the second viscosity at a third temperature higher than the second temperature; and forming a first insulating film by curing the insulating material. In this method, the forming the first insulating film includes: bringing the insulating material to the second viscosity by heating the insulating material under a first condition; and bringing the insulating material to the third viscosity by heating the insulating material under a second condition. The first condition and the second condition are different in their temperature rising rate.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: December 23, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Tamotsu Owada, Hikaru Ohira, Hirosato Ochimizu
  • Patent number: 8907437
    Abstract: A current sensor packaged in an integrated circuit package to include a magnetic field sensing circuit, a current conductor and an insulator that meets the safety isolation requirements for reinforced insulation under the UL 60950-1 Standard is presented. The insulator is provided as an insulation structure having at least two layers of thin sheet material. The insulation structure is dimensioned so that plastic material forming a molded plastic body of the package provides a reinforced insulation. According to one embodiment, the insulation structure has two layers of insulating tape. Each insulating tape layer includes a polyimide film and adhesive. The insulation structure and the molded plastic body can be constructed to achieve at least a 500 VRMS working voltage rating.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: December 9, 2014
    Assignee: Allegro Microsystems, LLC
    Inventors: Shaun D. Milano, Weihua Chen
  • Patent number: 8896135
    Abstract: Disclosed is an encapsulation film. An inorganic oxide film is formed on an organic sealing layer by an atomic layer deposition (ALD) to form the encapsulation film, wherein the organic sealing layer is a polymer containing hydrophilic groups. The organic sealing layer and the inorganic oxide layer have covalent bondings therebetween. The encapsulation film can solve the moisture absorption problem of conventional organic sealing layers, thereby being suitable for use as a package of optoelectronic devices.
    Type: Grant
    Filed: January 4, 2011
    Date of Patent: November 25, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Ching-Chiun Wang, Kang-Feng Lee, Feng-Yu Tsai, Ming Horn Zheng, Chih-Yung Huang, Shih-Chin Lin, Jen-Rong Huang
  • Patent number: 8890316
    Abstract: A method and structures are provided for implementing decoupling capacitors within a DRAM TSV stack. A DRAM is formed with a plurality of TSVs extending completely through the substrate and filled with a conducting material. A layer of glass is grown on both the top and bottom of the DRAM providing an insulator. A layer of metal is grown on each glass layer providing a conductor. The metal and glass layers are etched through to TSVs with a gap provided around the perimeter of via pads. A respective solder ball is formed on the TSVs to connect to another DRAM chip in the DRAM TSV stack. The metal layers are connected to at least one TSV by one respective solder ball and are connected to a voltage source and a dielectric is inserted between the metal layers in the DRAM TSV stack to complete the decoupling capacitor.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: November 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Joab D. Henderson, Kyu-hyoun Kim, Warren E. Maule, Kenneth L. Wright
  • Patent number: 8872357
    Abstract: An anisotropic conductive film composition for bonding a semiconductor device, the composition including: a binder system including a urethane resin having a glass transition temperature of about 100° C. or higher, a radical polymerizable compound, an organic peroxide, and conductive particles.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: October 28, 2014
    Assignee: Cheil Industries, Inc.
    Inventor: Do Hyun Park
  • Patent number: 8852999
    Abstract: A system-in-a-package based flash memory card including an integrated circuit package occupying a small overall area within the card and cut to conform to the shape of a lid for the card. An integrated circuit may be cut from a panel into a shape that fits within and conforms to the shape of lids for a finished memory card, such as for example an SD Card. The integrated circuit package may be a system-in-a-package, a multi-chip module, or other arrangement where a complete electronic system is formed in a single package.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: October 7, 2014
    Assignee: SanDisk Technologies Inc.
    Inventors: Hem Takiar, Robert C. Miller, Warren Middlekauff, Michael W. Patterson, Shrikar Bhagath
  • Patent number: 8847372
    Abstract: An exposed die overmolded flip chip package includes a substrate. A die is flip chip mounted to an upper surface of the substrate. The package further includes a mold cap filling a space between an active surface of the die and the upper surface of the substrate. The mold cap includes a principal surface, sidewalls extending from the upper surface of the substrate to the principal surface, an annular surface coplanar with the inactive surface of the die and extending outward from a peripheral edge of the inactive surface of the die, and protruding surfaces extending between the principal surface and the annular surface. The mold cap does not cover the inactive surface of the die such that heat transfer from the die to the ambient environment is maximized and the package thickness is minimized.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: September 30, 2014
    Inventors: Robert Francis Darveaux, Michael Barrow, Miguel Angel Jimarez, Jae Dong Kim, Dae Keun Park, Ki Wook Lee, Ju Hoon Yoon
  • Patent number: 8846456
    Abstract: A substrate which has at least one component, such as a semiconductor chip, arranged on it is manufactured from a film made of plastic material laminated onto a surface of the substrate and of the at least one component, where the surface has at least one contact area. First, the film to be laminated onto the surface of the substrate and the at least one component, or a film composite including the film, is arranged in a chamber such that the chamber is split by the film or film composite into a first chamber section and a second chamber section, which is isolated from the first chamber section so as to be gastight. A higher atmospheric pressure is provided or produced in the first chamber section than in the second chamber section; and contact is made between the surface of the substrate arranged in the second chamber section and the at least one component and the film or the film composite, which contact brings about the lamination of the film onto the surface.
    Type: Grant
    Filed: August 29, 2007
    Date of Patent: September 30, 2014
    Assignee: Siemens Aktiengesellschaft
    Inventor: Karl Weidner
  • Patent number: 8841782
    Abstract: An integrated circuit package system includes: providing a substrate; forming a conductive layer over the substrate; forming a mold gate layer having an organic material without polymerization over the conductive layer; and attaching an integrated circuit over the substrate adjacent the mold gate layer.
    Type: Grant
    Filed: August 14, 2008
    Date of Patent: September 23, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: DaeWook Yang, Youngcheol Kim, Tae Keun Lee
  • Patent number: 8791561
    Abstract: A support substrate includes a first surface and a second surface located above the level of the first surface. Chips are mounted on the first surface. A first insulating film is disposed over each chip. First conductive plugs are connected to the chip extending through each first insulating film. Filler material made of resin filling a space between chips. Wirings are disposed over the first insulating film and the filler material for interconnecting different chips. The second surface, an upper surface of the first insulating film and an upper surface of the filler material are located at the same level.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: July 29, 2014
    Assignees: Fujitsu Limited, Shinko Electric Industries Co., Ltd.
    Inventors: Sadahiro Kishii, Tsuyoshi Kanki, Yoshihiro Nakata, Yasushi Kobayashi, Masato Tanaka, Akio Rokugawa
  • Patent number: 8786102
    Abstract: A semiconductor device includes a first wiring board, a second semiconductor chip, and a second seal. The first wiring board includes a first substrate, a first semiconductor chip, and a first seal. The first semiconductor chip is disposed on the first substrate. The first seal is disposed on the first substrate. The first seal surrounds the first semiconductor chip. The first seal has the same thickness as the first semiconductor chip. The second semiconductor chip is stacked over the first semiconductor chip. The first semiconductor chip is between the second semiconductor chip and the first substrate. The second semiconductor chip is greater in size in plan view than the first semiconductor chip. The second seal seals at least a first gap between the first semiconductor chip and the second semiconductor chip.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: July 22, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventors: Masanori Yoshida, Fumitomo Watanabe
  • Patent number: 8786059
    Abstract: A structure and method for producing the same is disclosed. The structure includes an organic passivation layer with solids suspended therein. Preferential etch to remove a portion of the organic material and expose portions of such solids creates enhanced surface roughness, which provides a significant advantage with respect to adhesion of that passivation layer to the packaging underfill material.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: July 22, 2014
    Assignee: International Business Machines Corporation
    Inventors: Alexandre Blander, Jon A Casey, Timothy H Daubenspeck, Ian D Melville, Jennifer V Muncy, Marie-Claude Paquet
  • Patent number: 8766416
    Abstract: A semiconductor package includes a substrate having opposite first and second surfaces and a ground layer therein. Further, the second surface has at least a recessed portion for exposing portions of the ground layer. The semiconductor package further includes a semiconductor chip disposed on the first surface of the substrate; an encapsulant formed on the first surface of the substrate for encapsulating the semiconductor chip; and a metal layer covering the encapsulant and the substrate and extending to the recessed portion for electrically connecting the ground layer. As such, the space for circuit layout is increased and the circuit layout flexibility is improved.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: July 1, 2014
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Tsung-Hsien Hsu, Hao-Ju Fang, Hsin-Lung Chung
  • Patent number: 8749031
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor device body and an insulating adhesive layer. The semiconductor device body is formed with a square plate shape and has an element portion provided on a first major surface. The insulating adhesive layer is provided to cover a second major surface of the semiconductor device body and one or two of four side faces of the semiconductor device body.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: June 10, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Ryoji Matsushima
  • Patent number: 8749074
    Abstract: Embodiments include but are not limited to apparatuses and systems including semiconductor packages, e.g. memory packages, having an interposer including at least one topological feature, such as a depression in a surface of the interposer, a die coupled to the surface of the interposer, and an encapsulant material formed over the die and the interposer, and disposed in the at least one depression to resist movement of the encapsulant material relative to the interposer. Other embodiments may be described and claimed.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: June 10, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Steven Eskildsen, Aravind Ramamoorthy
  • Patent number: 8749055
    Abstract: An electronic device includes: a substrate having first and second surfaces, wherein the first surface is opposite to the second surface; a first electronic element mounted on the first surface of the substrate; a second electronic element mounted on the second surface of the substrate; and a resin mold sealing the first electronic element and the first surface of the substrate. The resin mold further seals the second electronic element on the second surface of the substrate. The second surface of the substrate has a portion, which is exposed from the resin mold. The second electronic element is not disposed on the portion of the second surface.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: June 10, 2014
    Assignee: DENSO CORPORATION
    Inventors: Tetsuto Yamagishi, Tohru Nomura, Norihisa Imaizumi, Yasutomi Asai
  • Patent number: 8749056
    Abstract: A module and a method for manufacturing a module are disclosed. An embodiment of a module includes a first semiconductor device, a frame arranged on the first semiconductor device, the frame including a cavity, and a second semiconductor device arranged on the frame wherein the second semiconductor device seals the cavity.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: June 10, 2014
    Assignee: Infineon Technologies AG
    Inventors: Daniel Kehrer, Stefan Martens, Tze Yang Hin, Helmut Wietschorke, Horst Theuss, Beng Keh See, Ulrich Krumbein
  • Patent number: 8749075
    Abstract: An integrated circuit is provided. The integrated circuit includes: a chip and encapsulation material covering at least three sides of the chip, the encapsulation material being formed from adhesive material. The integrated circuit includes a carrier adhered to the chip by means of the encapsulation material.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: June 10, 2014
    Assignee: Infineon Technologies AG
    Inventors: Joachim Mahler, Lukas Ossowski, Khalil Hosseini, Ivan Nikitin
  • Patent number: 8729693
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a first device having a first exposed side and a first inward side; connecting a second device having a second exposed side and a second inward side facing the first inward side to the first device, the second device having planar dimensions less than planar dimensions of the first device; connecting a system connector to a perimeter of the first inward side, the system connector having an exposed leg partially vertical and an exposed foot partially horizontal; and applying an encapsulant exposing the first exposed side, the second exposed side, the exposed leg, and the exposed foot, the exposed leg offset from the encapsulant, the exposed foot on an end of the system connector opposite the first device.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: May 20, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Arnel Senosa Trasporto, Lionel Chien Hui Tay, Henry Descalzo Bathan
  • Publication number: 20140124916
    Abstract: Presented herein are a package-on-package device having a molded underfill and a method for forming the same, the method comprising applying a package mount mounting a die to the first side of a carrier package. A molded underfill may be applied first side of the carrier package, and be in contact with a portion of the package mount a portion of a sidewall of the die. A top package having at least one land may be mounted to the first side of the carrier package above the die, and, optionally separated from the top of the die. The package mount may be coined prior to, during or after applying the molded underfill to optionally be level with the underfill surface. The underfill region contacting the package mount may be below or above the surface of the underfill region contacting the die sidewall.
    Type: Application
    Filed: November 2, 2012
    Publication date: May 8, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Chien-Hsun Lee, Jung Wei Cheng, Tsung-Ding Wang, Ming-Da Cheng, Yung Ching Chen
  • Patent number: 8716875
    Abstract: A semiconductor package includes a substrate having a first surface, a second surface that is opposite to the first surface, and an opening formed between the first surface of the substrate and the second surface of the substrate. One or more bonding wires electrically couple a first surface of a semiconductor die included in the semiconductor package to the first surface of the substrate through an opening of the substrate. A first electrically insulative structure is disposed to substantially fill an area between the first surface of the semiconductor die, the second surface of the substrate, and one or more interconnect bumps that electrically couple the semiconductor die to the substrate. The first electrically insulative structure substantially encapsulates the one or more bonding wires and substantially fills the opening of the substrate.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: May 6, 2014
    Assignee: Marvell World Trade Ltd.
    Inventor: Sehat Sutardja
  • Patent number: 8697567
    Abstract: A method and structures are provided for implementing decoupling capacitors within a DRAM TSV stack. A DRAM is formed with a plurality of TSVs extending completely through the substrate and filled with a conducting material. A layer of glass is grown on both the top and bottom of the DRAM providing an insulator. A layer of metal is grown on each glass layer providing a conductor. The metal and glass layers are etched through to TSVs with a gap provided around the perimeter of via pads. A respective solder ball is formed on the TSVs to connect to another DRAM chip in the DRAM TSV stack. The metal layers are connected to at least one TSV by one respective solder ball and are connected to a voltage source and a dielectric is inserted between the metal layers in the DRAM TSV stack to complete the decoupling capacitor.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: April 15, 2014
    Assignee: International Business Machines Corporation
    Inventors: Joab D. Henderson, Kyu-hyoun Kim, Warren E. Maule, Kenneth L. Wright
  • Publication number: 20140091454
    Abstract: A semiconductor device includes a semiconductor die. An encapsulant is formed around the semiconductor die. A build-up interconnect structure is formed over a first surface of the semiconductor die and encapsulant. A first supporting layer is formed over a second surface of the semiconductor die as a supporting substrate or silicon wafer disposed opposite the build-up interconnect structure. A second supporting layer is formed over the first supporting layer an includes a fiber enhanced polymer composite material comprising a footprint including an area greater than or equal to an area of a footprint of the semiconductor die. The semiconductor die comprises a thickness less than 450 micrometers (?m). The thickness of the semiconductor die is at least 1 ?m less than a difference between a total thickness of the semiconductor device and a thickness of the build-up interconnect structure and the second supporting layer.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Kang Chen, Yu Gu
  • Publication number: 20140061932
    Abstract: A package-on-package (“PoP”) structure and a method of forming are provided. The PoP structure may be formed by forming a first set of electrical connections on a first substrate. A first material may be applied to the first set of electrical connections. A second substrate may be provided having a second set of electrical connections formed thereon. The first set of electrical connections of the first substrate having the epoxy flux applied may be contacted to the second electrical connections of the second substrate. A reflow process may be performed to electrically connect the first substrate to the second substrate. The epoxy flux applied to the first electrical connections of the first substrate may prohibit electrical bridges or shorts from forming during the reflow process.
    Type: Application
    Filed: September 5, 2012
    Publication date: March 6, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Tse Chen, Yi-Da Tsai, Xi-Hong Chen, Tao-Hua Lee, Wei-Yu Chen, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 8659129
    Abstract: A semiconductor device in accordance with an embodiment comprises a semiconductor chip; a die pad having a chip mount surface for mounting the semiconductor chip; first leads electrically connected to the semiconductor chip; a thermosetting resin part for securing end parts of the first leads to the die pad; and a thermoplastic resin part for sealing the semiconductor chip, the die pad, and the thermosetting resin part.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: February 25, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Jiro Shinkai
  • Patent number: 8648479
    Abstract: According to the present invention, an epoxy resin composition for semiconductor encapsulant including (A) an epoxy resin, (B) a curing agent, (C) an inorganic filler, and (D) a compound in which a copolymer of a 1-alkene having 5 to 80 carbon atoms and maleic anhydride is esterified with an alcohol having 5 to 25 carbon atoms in the presence of a compound represented by General Formula (1), wherein R1 in General Formula (1) is selected from the group consisting of an alkyl group having 1 to 5 carbon atoms, a halogenated alkyl group having 1 to 5 carbon atoms, and an aromatic group having 6 to 10 carbon atoms is provided.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: February 11, 2014
    Assignee: Sumitomo Bakelite Co., Ltd.
    Inventor: Jun-ichi Tabei
  • Publication number: 20140035154
    Abstract: A chip package is provided, the chip package including: a chip including at least one contact pad formed on a chip front side; an encapsulation material at least partially surrounding the chip and covering the at least one contact pad; and at least one electrical interconnect formed through the encapsulation material, wherein the at least one electrical interconnect is configured to electrically redirect the at least one contact pad from a chip package first side at the chip front side to at least one solder structure formed over a chip package second side at a chip back side.
    Type: Application
    Filed: August 2, 2012
    Publication date: February 6, 2014
    Applicant: Infineon Technologies AG
    Inventors: Ottmar Geitner, Walter Hartner, Maciej Wojnowski, Ulrich Wachter, Michael Bauer, Andreas Stueckjuergen
  • Patent number: 8643199
    Abstract: Dendrimer/hyperbranched materials are combined with polyimide to form a low CTE material for use as a dielectric substrate layer or an underfill. In the alternative, ruthenium carbene complexes are used to catalyze ROMP cross-linking reactions in polyimides to produce a class of cross-linkable, thermal and mechanical stable material for use as a dielectric substrate or underfill. In another alternative, dendrimers/hyperbranched materials are synthesized by different methods to produce low viscosity, high Tg, fast curing, mechanically and chemically stable materials for imprinting applications.
    Type: Grant
    Filed: January 28, 2009
    Date of Patent: February 4, 2014
    Assignee: Intel Corporation
    Inventors: Stephen E. Lehman, Jr., James C. Matayabas, Jr., Saikumar Jayaraman
  • Patent number: 8637980
    Abstract: An assembly includes an integrated circuit die coupled to another component of the assembly with an alkali silicate glass material. The alkali silicate material may include particles for modifying the thermal, mechanical, and/or electrical characteristics of the material.
    Type: Grant
    Filed: December 18, 2007
    Date of Patent: January 28, 2014
    Assignee: Rockwell Collins, Inc.
    Inventors: Nathan P. Lower, Alan P. Boone, Ross K. Wilcoxon
  • Publication number: 20140021638
    Abstract: A embedded integrated circuit package is provided, the embedded integrated circuit package including: at least one chip arranged over a chip carrier, the at least one chip including a plurality of chip contact pads; encapsulation material formed over the chip carrier and at least partially surrounding the at least one chip; a plurality of electrical interconnects formed through the encapsulation material, wherein each electrical interconnect is electrically connected to a chip contact pad; and a structure formed between the electrical interconnects of the embedded integrated circuit package, wherein the structure increases the creepage resistance between the electrical interconnects.
    Type: Application
    Filed: July 18, 2012
    Publication date: January 23, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Joachim Mahler, Edward Fuergut, Khalil Hosseini, Georg Meyer-Berg
  • Patent number: 8618645
    Abstract: A package process is provided. An adhesive layer is disposed on a carrier board and then plural first semiconductor devices are disposed on the adhesive layer. A first molding compound formed on the carrier board covers the sidewalls of the first semiconductor devices and fills the gaps between the first semiconductor devices so as to form a chip array board constructed by the first semiconductor devices and the first molding compound. Next, plural second semiconductor devices are flip-chip bonded to the first semiconductor devices respectively. Then, a second molding compound formed on the chip array board at least covers the sidewalls of the second semiconductor devices and fills the gaps between the second semiconductor devices. Subsequently, the chip array board is separated from the adhesive layer. Then, the first and the second molding compound are cut along the gaps between the second semiconductor devices.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: December 31, 2013
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chi-Chih Shen, Jen-Chuan Chen, Tommy Pan
  • Publication number: 20130341807
    Abstract: A semiconductor package structure includes a package substrate having a first surface, a second surface opposite to the first surface, and a sidewall surface between the first surface and the second surface. A semiconductor device is mounted on the first surface. A mold cap encapsulates the semiconductor device. The mold cap includes a vertical extension portion covering the sidewall surface and a horizontal extension portion covering a periphery of a solder ball implanting region on the second surface.
    Type: Application
    Filed: June 25, 2012
    Publication date: December 26, 2013
    Inventor: Po-Chun Lin
  • Publication number: 20130334714
    Abstract: A method of manufacture of an integrated circuit packaging system includes providing a substrate; connecting an integrated circuit die; forming a molding having a temperature-dependent characteristic directly on the top surface of the substrate; and forming a coupling encapsulation having a coupled characteristic different from the temperature-dependent characteristic directly on the molding forms an encapsulation boundary between the coupling encapsulation and the molding.
    Type: Application
    Filed: June 19, 2012
    Publication date: December 19, 2013
    Inventors: YiSu Park, KyungHoon Lee, JoungIn Yang, SangMi Park, DaeSik Choi