Encapsulations, E.g., Encapsulating Layers, Coatings, E.g., For Protection (epo) Patents (Class 257/E23.116)
  • Patent number: 11901115
    Abstract: Apparatuses, systems and methods associated with a substrate assembly with an encapsulated magnetic feature for an inductor are disclosed herein. In embodiments, a substrate assembly may include a base substrate, a magnetic feature encapsulated within the base substrate, and a coil, wherein a portion of the coil extends through the magnetic feature. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: February 13, 2024
    Assignee: Intel Corporation
    Inventors: Kyu-Oh Lee, Rahul Jain, Sai Vadlamani, Cheng Xu, Ji Yong Park, Junnan Zhao, Seo Young Kim
  • Patent number: 11869771
    Abstract: A manufacturing method of an anchorage element of a passivation layer, comprising: forming, in a semiconductor body made of SiC and at a distance from a top surface of the semiconductor body, a first implanted region having, along a first axis, a first maximum dimension; forming, in the semiconductor body, a second implanted region, which is superimposed to the first implanted region and has, along the first axis, a second maximum dimension smaller than the first maximum dimension; carrying out a process of thermal oxidation of the first implanted region and second implanted region to form an oxidized region; removing said oxidized region to form a cavity; and forming, on the top surface, the passivation layer protruding into the cavity to form said anchorage element fixing the passivation layer to the semiconductor body.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: January 9, 2024
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Simone Rascuna′, Mario Giuseppe Saggio
  • Patent number: 11869875
    Abstract: An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide various methods of manufacturing electronic devices, and electronic devices manufactured thereby, that comprise utilizing an adhesive layer to attach an upper electronic package to a lower die and/or utilizing metal pillars for electrically connecting the upper electronic package to a lower substrate, wherein the metal pillars have a smaller height above the lower substrate than the lower die.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: January 9, 2024
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Joon Young Park, Jung Soo Park, Ji Hye Yoon
  • Patent number: 11862577
    Abstract: Provided is a package structure, including a die, a plurality of through vias, an encapsulant, a plurality of first connectors, a warpage control material and a protection material. The plurality of through vias are disposed around the die. The encapsulant laterally encapsulate the die and the plurality of through vias. The plurality of first connectors are electrically connected to a first surface of the plurality of through vias. The warpage control material is disposed over a first surface of the die. The protection material is disposed over the encapsulant, around the plurality of first connectors and the warpage control material. A Young's modulus of the warpage control material is greater than a Young's modulus of the encapsulant, and the Young's modulus of the encapsulant is greater than a Young's modulus of the protection material.
    Type: Grant
    Filed: December 24, 2021
    Date of Patent: January 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Jan Pei, Ching-Hua Hsieh, Hsiu-Jen Lin, Wei-Yu Chen, Chia-Shen Cheng, Chih-Chiang Tsao, Jen-Jui Yu, Cheng-Shiuan Wong
  • Patent number: 11854837
    Abstract: Semiconductor devices and methods of manufactured are presented in which a first redistribution structure is formed, semiconductor devices are bonded to the first redistribution structure, and the semiconductor devices are encapsulated in an encapsulant. First openings are formed within the encapsulant, such as along corners of the encapsulant, in order to help relieve stress and reduce cracks.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Chen Lai, Ming-Chih Yew, Po-Yao Lin, Chien-Sheng Chen, Shin-Puu Jeng
  • Patent number: 11842987
    Abstract: A display panel including a circuit board having pads, light emitting devices electrically connected to the pads and arranged on the circuit board, each light emitting device having a first surface facing the circuit board and a second surface opposite to the first surface, a buffer material layer disposed between the circuit board and the light emitting devices to fill a space between the circuit board and the light emitting devices, and a cover layer covering the second surface of the light emitting devices, in which the buffer material layer is disposed under the first surfaces of the light emitting devices and has grooves in a region between adjacent light emitting devices, a portion of a top surface of the buffer material layer is disposed between adjacent light emitting devices, and the cover layer fills the grooves of the buffer material layer.
    Type: Grant
    Filed: July 15, 2022
    Date of Patent: December 12, 2023
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Seong Kyu Jang, Seom Geun Lee, Chan Seob Shin, Ho Joon Lee
  • Patent number: 11810839
    Abstract: One or more embodiments are directed to semiconductor packages and methods in which one or more electrical components are positioned between a semiconductor die and a surface of a substrate. In one embodiment, a semiconductor package includes a substrate having a first surface. One or more electrical components are electrically coupled to electrical contacts on the first surface of the substrate. A semiconductor die is positioned on the one or more electrical components, and the semiconductor die has an active surface that faces away from the substrate. An adhesive layer is on the first surface of the substrate and on the one or more electrical components, and the semiconductor die is spaced apart from the one or more electrical components by the adhesive layer. Wire bonds are provided that electrically couples the active surface of the semiconductor die to the substrate.
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: November 7, 2023
    Assignee: STMICROELECTRONICS S.r.l.
    Inventor: Cristina Somma
  • Patent number: 11804478
    Abstract: A semiconductor device A1 includes a substrate 3, a conductive section 5 formed on the substrate 3 and including a conductive material, a lead 1A located on the substrate 3, a semiconductor chip 4A located on the lead 1A, a control chip 4G located on the substrate 3 and electrically connected to the conductive section 5 and the semiconductor chip 4A for controlling an operation of the semiconductor chip 4A, and a resin 7 covering the semiconductor chip 4A, the control chip 4G, at least a part of the substrate 3 and a part of the lead 1A. This configuration contributes to achieving a higher level of integration of the semiconductor device.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: October 31, 2023
    Assignee: ROHM CO., LTD.
    Inventors: Yuji Ishimatsu, Ryuichi Furutani
  • Patent number: 11789366
    Abstract: A method for removing a resist layer including the following steps is provided. A patterned resist layer on a material layer is formed. A stripping solution is applied to the patterned resist layer to dissolve the patterned resist layer without dissolving the material layer, wherein the stripping solution comprises a non-dimethyl sulfoxide solvent and an alkaline compound, the non-dimethyl sulfoxide solvent comprises an aprotic solvent and a protic solvent.
    Type: Grant
    Filed: June 1, 2022
    Date of Patent: October 17, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Tai-Min Chang
  • Patent number: 11791300
    Abstract: An electronic package is provided, where a circuit layer and a metal layer having a plurality of openings are formed on a dielectric layer of a circuit portion to reduce the area ratio of the metal layer to the dielectric layer, so as to reduce stress concentration and prevent warping of the electronic package.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: October 17, 2023
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Fang-Lin Tsai, Chia-Yu Kuo, Pei-Geng Weng, Wei-Son Tsai, Yih-Jenn Jiang
  • Patent number: 11769756
    Abstract: Hybrid fanouts for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, at least one edge a first semiconductor die is attached to a molding including through mold vias (TMVs). Conductive traces may be formed on a first side of the first semiconductor die, where the first side includes integrated circuitry coupled to the conductive traces. Moreover, conductive pads may be formed on a surface of the molding, which is coplanar with the first side. The conductive pads are coupled to first ends of the TMVs, where second ends of the TMVs are coupled to bond wires connected to one or more second semiconductor dies that the first semiconductor die carries. Conductive bumps can be formed on the conductive traces and pads such that the first semiconductor die and the molding attached thereto can be directly attached to a printed circuit board.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: September 26, 2023
    Inventors: Bharat Bhushan, Pratap Murali, Raj K. Bansal
  • Patent number: 11764159
    Abstract: Structures and formation methods of chip packages are provided. The method includes disposing a semiconductor die over a carrier substrate. The method also includes disposing an interposer substrate over the carrier substrate. The interposer substrate has a recess that penetrates through opposite surfaces of the interposer substrate. The interposer substrate has interior sidewalls surrounding the semiconductor die, and the semiconductor die is as high as or higher than the interposer substrate. The method further includes forming a protective layer in the recess of the interposer substrate to surround the semiconductor die. In addition, the method includes removing the carrier substrate and stacking a package structure over the interposer substrate.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: September 19, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shin-Puu Jeng, Po-Hao Tsai, Po-Yao Chuang, Techi Wong
  • Patent number: 11764163
    Abstract: Provided are a semiconductor encapsulation structure and an encapsulation method. The structure includes a circuit board, which includes at least one electromagnetic shield area and a non-electromagnetic shield area located on one side of the electromagnetic shield area, where the circuit board internally includes a number N of metal line layers stacked in sequence and insulating layers located between adjacent metal line layers; a non-shield module and a shield module, where the non-shield module is located within the non-electromagnetic shield area, and the shield module is located within the electromagnetic shield area; a thin film encapsulation layer, located on a side of the circuit board adjacent to the first surface, where the thin film encapsulation layer covers the non-electromagnetic shield area and the electromagnetic shield area; an electromagnetic shield structure, which covers the electromagnetic shield area and forms the closed space with the circuit board.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: September 19, 2023
    Assignee: LUXSHARE ELECTRONIC TECHNOLOGY (KUNSHAN) LTD.
    Inventors: Xiaolei Zhou, Peng Liu, Wenbin Kang
  • Patent number: 11715727
    Abstract: Various packages and methods of forming packages are discussed. According to an embodiment, a package includes a processor die at least laterally encapsulated by an encapsulant, a memory die at least laterally encapsulated by the encapsulant, and a redistribution structure on the encapsulant. The processor die is communicatively coupled to the memory die through the redistribution structure. According to further embodiments, the memory die can include memory that is a cache of the processor die, and the memory die can comprise dynamic random access memory (DRAM).
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: August 1, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Der-Chyang Yeh, An-Jhih Su
  • Patent number: 11705432
    Abstract: Systems, apparatuses, and methods using wire bonds and direct chip attachment (DCA) features in stacked die packages are described. A stacked die package includes a substrate and at least a first semiconductor die and a second semiconductor die that are vertically stacked above the substrate. An active surface of the first semiconductor die faces an upper surface of the substrate and the first semiconductor die is operably coupled to the substrate by direct chip attachment DCA features. A back side surface of the second semiconductor die faces a back side surface of the first semiconductor die. The second semiconductor die is operably coupled to the substrate by wire bonds extending between an active surface thereof and the upper surface of the substrate.
    Type: Grant
    Filed: July 1, 2021
    Date of Patent: July 18, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Hiroki Fujisawa, Raj K. Bansal, Shunji Kuwahara, Mitsuaki Katagiri, Satoshi Isa
  • Patent number: 11705405
    Abstract: A packaged integrated circuit device includes a substrate having a spacer chip thereon, which is devoid of active integrated circuits therein but which has a stress-relieving pattern of grooves in an upper surface thereof. A first semiconductor chip is provided, which is bonded to the upper surface of the spacer chip. A molded region is provided, which includes a passivating resin that: (i) at least partially surrounds the first semiconductor chip and the spacer chip, and (ii) extends into at least a portion of the grooves within the upper surface of the spacer chip.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: July 18, 2023
    Inventor: Jiwoo Park
  • Patent number: 11698394
    Abstract: A current sensor is described comprising an integrated circuit for sensing electric currents comprising an active side, the active side comprising at least one sensing element and at least one contact pad and a housing comprising material embedding the integrated circuit arranged for allowing electric connection to the at least two contact pads of the active side of the integrated circuit. The housing comprises at least one conductive via disposed outside the integrated circuit and connected to the at least one contact pad, for distributing signals from the at least one contact pad through the housing away from the active side of the integrated circuit.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: July 11, 2023
    Assignee: MELEXIS TECHNOLOGIES SA
    Inventors: Tim Vangerven, Appolonius Jacobus Van Der Wiel
  • Patent number: 11685648
    Abstract: Microelectromechanical systems (MEMS) packages and methods of manufacture thereof are described. In an embodiment, a method of manufacturing a MEMS package may include attaching a MEMS structure having a capping structure thereon to a device wafer comprising a plurality of first devices formed therein to form a wafer level MEMS package; and singulating the device wafer having the MEMS structure attached thereto to form a plurality of chip scale MEMS packages.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: June 27, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Kuo-Chung Yee
  • Patent number: 11664325
    Abstract: A package structure including a first semiconductor die, a second semiconductor die, first conductive pillars and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure and a first redistribution circuit structure. The semiconductor substrate includes a first portion and a second portion disposed on the first portion. The interconnect structure is disposed on the second portion, the first redistribution circuit structure is disposed on the interconnect structure, and the lateral dimension of the first portion is greater than the lateral dimension of the second portion. The second semiconductor die is disposed on the first semiconductor die. The first conductive pillars are disposed on the first redistribution circuit structure of the first semiconductor die. The first insulating encapsulation is disposed on the first portion.
    Type: Grant
    Filed: February 8, 2022
    Date of Patent: May 30, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Sung Huang, Cheng-Chieh Hsieh, Hsiu-Jen Lin, Hui-Jung Tsai, Hung-Yi Kuo, Hao-Yi Tsai, Ming-Hung Tseng, Yen-Liang Lin, Chun-Ti Lu, Chung-Ming Weng
  • Patent number: 11664288
    Abstract: A method of manufacturing a semiconductor device includes providing, in a housing, an insulating substrate having a metal pattern, a semiconductor chip, a sinter material applied on the semiconductor chip, and a terminal, providing multiple granular sealing resins supported by a grid provided in the housing, heating an inside of the housing until a temperature thereof reaches a first temperature higher than a room temperature and thereby discharging a vaporized solvent of the sinter material out of the housing via a gap of the grid and a gap of the sealing resins, and heating the inside of the housing until the temperature thereof reaches a second temperature higher than the first temperature and thereby causing the melted sealing resins to pass the gap of the grid and form a resin layer covering the semiconductor chip.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: May 30, 2023
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenta Nakahara, Akitoshi Shirao
  • Patent number: 11637056
    Abstract: A chip package includes a first interconnection scheme; a plurality of first metal contacts under and on the first interconnection scheme and at a bottom surface of the chip package; a first semiconductor IC chip over the first interconnection scheme; a first connector over the first interconnection scheme and at a same horizontal level as the first semiconductor IC chip, wherein the first connector comprises a first substrate and a plurality of first through vias vertically extending through the first substrate of the first connector; a first polymer layer over the first interconnection scheme, wherein the first polymer layer has a top surface coplanar with a top surface of the first semiconductor IC chip, a top surface of the first substrate of the first connector and a top surface of each of the plurality of first through vias; and a second interconnection scheme on the top surface of the first polymer layer, the top surface of the first semiconductor IC chip, the top surface of the first connector and the
    Type: Grant
    Filed: September 19, 2020
    Date of Patent: April 25, 2023
    Assignee: iCometrue Company Ltd.
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee
  • Patent number: 11613652
    Abstract: Compositions are disclosed which include between about 0.05 to about 5 or less wt. % of at least one acrylate monomer based on the total weight of the composition. The acrylate monomer reduces the peak cure temperature, thereby accelerating the rate of cure, without sacrificing completeness of the cure or the release performance of the cured product. The addition of the acrylate monomer also enables a reduction in the amount of costly platinum catalyst required to effectively cure a composition. In addition to the acrylate monomer, the compositions also include a silicone base polymer, a crosslinking agent, and platinum catalyst. The cured compositions exhibit properties useful for incorporation into release liners, adhesive articles, medical products and gaskets.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: March 28, 2023
    Assignee: MORGAN ADHESIVES COMPANY, LLC
    Inventors: Timothy M. Smith, Joseph D. Gorczyca, Gary A. McMaster, Scott Moeller
  • Patent number: 11574890
    Abstract: In one example, a semiconductor device comprises a first base substrate comprising a first base conductive structure, a first encapsulant contacting a lateral side of the first base substrate, a redistribution structure (RDS) substrate over the base substrate and comprising an RDS conductive structure coupled with the first base conductive structure, a first electronic component over the RDS substrate and over a first component terminal coupled with the RDS conductive structure, and a second encapsulant over the RDS substrate and contacting a lateral side of the first electronic component. Other examples and related methods are also disclosed herein.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: February 7, 2023
    Assignee: Amkor Technology Singapore Holding Pte. Lte.
    Inventors: Yi Seul Han, Tae Yong Lee, Ji Yeon Ryu, Won Chul Do, Jin Young Khim, Shaun Bowers, Ron Huemoeller
  • Patent number: 11572619
    Abstract: Embodiments of the present disclosure generally relate to processing a workpiece containing a substrate during deposition, etching, and/or curing processes with a mask to have localized deposition on the workpiece. A mask is placed on a first layer of a workpiece, which protects a plurality of trenches from deposition of a second layer. In some embodiments, the mask is placed before deposition of the second layer. In other embodiments, the second layer is cured before the mask is deposited. In other embodiments, the second layer is etched after the mask is deposited. Methods disclosed herein allow the deposition of a second layer in some of the trenches present in the workpiece, while at least partially preventing deposition of the second layer in other trenches present in the workpiece.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: February 7, 2023
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Jinrui Guo, Ludovic Godet, Rutger Meyer Timmerman Thijssen, Yongan Xu, Jhenghan Yang, Chien-An Chen
  • Patent number: 11557524
    Abstract: In one example, a semiconductor device can comprise (a) an electronic device comprising a device top side, a device bottom side opposite the device top side, and a device sidewall between the device top side and the device bottom side, (b) a first conductor comprising, a first conductor side section on the device sidewall, a first conductor top section on the device top side and coupled to the first conductor side section, and a first conductor bottom section coupled to the first conductor side section, and (c) a protective material covering the first conductor and the electronic device. A lower surface of the first conductor top section can be higher than the device top side, and an upper surface of the first conductor bottom section can be lower than the device top side. Other examples and related methods are also disclosed herein.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: January 17, 2023
    Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.
    Inventors: Kyeong Tae Kim, Yi Seul Han, Jae Beom Shim, Tae Yong Lee
  • Patent number: 11524892
    Abstract: A first electronic component, such as a sensor having opposed first and second surfaces and a first thickness, is arranged on a support member with the second surface facing towards the support member. A second electronic component, such as an integrated circuit mounted on a substrate and having a second thickness less than the first thickness, is arranged on the support member with a substrate surface opposed the second electronic component facing towards the support member. A package molding material is molded onto the support member to encapsulate the second electronic component while leaving exposed the first surface of the first electronic component. The support member is then removed to expose the second surface of the first electronic component and the substrate surface of the substrate.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: December 13, 2022
    Assignees: STMicroelectronics (Malta) Ltd, STMicroelectronics S.r.l.
    Inventors: Kevin Formosa, Marco Del Sarto
  • Patent number: 11515239
    Abstract: A quad flat no-lead (QFN) package structure including a lead frame, a semiconductor die, and an encapsulating material. The lead frame includes a die pad and a plurality of contacts surrounding the die pad. The semiconductor die is disposed on the die pad and electrically connected to the plurality of contacts, wherein a shortest distance between the semiconductor die and a first side of the die pad is shorter than a shortest distance between the semiconductor die to a second side of the die pad, and the first side is opposite to the second side. The encapsulating material encapsulates the lead frame and the semiconductor die and partially exposing the plurality of contacts, wherein an aspect ratio of the QFN package is substantially equal to or greater than 3.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: November 29, 2022
    Assignee: Novatek Microelectronics Corp.
    Inventors: Hong-Dyi Chang, Tai-Hung Lin, Jhih-Siou Cheng
  • Patent number: 11424224
    Abstract: A display panel including a circuit board having pads, light emitting devices electrically connected to the pads and arranged on the circuit board, each light emitting device having a first surface facing the circuit board, and a buffer material layer disposed between the circuit board and the light emitting devices to fill a space between the circuit board and the light emitting devices, in which the buffer material layer is disposed under the first surfaces of the light emitting devices.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: August 23, 2022
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Seong Kyu Jang, Seom Geun Lee, Chan Seob Shin, Ho Joon Lee
  • Patent number: 11404336
    Abstract: A method of forming a power semiconductor module includes providing a substrate of planar sheet metal, forming channels in an upper surface of the substrate that partially extend through a thickness of the substrate and define a plurality of islands in the substrate, mounting a first semiconductor die on a first one of the islands, forming a molded body of encapsulant that covers the substrate, fills the channels, and encapsulates the semiconductor die, forming a hole in the molded body and a recess in the upper surface of the substrate beneath the hole, and arranging a press-fit connector in the hole and forming a mechanical and electrical connection between an interior end of the press-fit connector and the substrate.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: August 2, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Wu Hu Li, Raphael Hellwig, Olaf Hohlfeld, Martin Mayer, Ivan Nikitin
  • Patent number: 11383429
    Abstract: Methods and systems for optofluidic device fabrication and design are herein disclosed. In examples, a user may manufacture the optofluidic device using stereolithography (SLA) three-dimensional (3D) printing, in which photosensitive resin is exposed to a focused laser, solidifying specific areas of resin. The optofluidic device may guide light for a broad wavelength range from a liquid or gas channel comprised within and may be used to guide the emission of light and particles of interest to a detector to identify the particles.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: July 12, 2022
    Assignee: Whitworth University
    Inventor: Philip S. Measor
  • Patent number: 11342280
    Abstract: A module includes: a substrate having a main surface and a side surface; an electronic component mounted on the main surface; a sealing resin that covers the main surface and the electronic component; and a shield film that covers a surface of the sealing resin and the side surface of the substrate. The sealing resin includes: a resin component containing an organic resin as a main component; and a granular filler containing an inorganic oxide as a main component. On a surface of the sealing resin, which is in contact with the shield film, parts of some grains of the filler are exposed from the resin component, a surface of the resin component includes a nitrogen functional group, and the shield film is formed of a metal that is a passivation metal and a transition metal or an alloy containing the metal.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: May 24, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Tadashi Nomura, Shin Furuya, Toru Koidesawa, Motohiko Kusunoki, Tetsuya Oda
  • Patent number: 10937760
    Abstract: A method for manufacturing chip package is disclosed. The method includes providing a wafer having an upper surface and a lower surface opposite thereto, in which the wafer comprises a plurality of conductive pads disposed on the upper surface; dicing the upper surface of the wafer to form a plurality of trenches; forming a patterned photoresist layer on the upper surface and in the trenches; forming a plurality of conductive bumps disposed correspondingly on the conductive pads; thinning the wafer from the lower surface toward the upper surface, such that the patterned photoresist layer in the trenches is exposed from the lower surface; forming an insulating layer under the lower surface; and dicing the patterned photoresist layer and the insulating layer along each trench to form a plurality of chip packages.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: March 2, 2021
    Assignee: COMCHIP TECHNOLOGY CO., LTD.
    Inventors: Chien-Chih Lai, Hung-Wen Lin
  • Patent number: 9040352
    Abstract: A semiconductor device package having a cavity formed using film-assisted molding techniques is provided. Through the use of such techniques the cavity can be formed in specific locations in the molded package, such as on top of a device die mounted on the package substrate or a lead frame. In order to overcome cavity wall angular limitations introduced by conformability issues associated with film-assisted molding, a gel reservoir feature is formed so that gel used to protect components in the cavity does not come in contact with a lid covering the cavity or the junction between the lid and the package attachment region. The gel reservoir is used in conjunction with a formed level setting feature that controls the height of gel in the cavity. Benefits include decreased volume of the cavity, thereby decreasing an amount of gel-fill needed and thus reducing production cost of the package.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: May 26, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Shun Meen Kuo, Li Li
  • Patent number: 9035472
    Abstract: In a semiconductor device, a conductor pattern is disposed in a position overlapped by a semiconductor chip in a thickness direction over the mounting surface (lower surface) of a wiring board. A solder resist film (insulating layer) covering the lower surface of the wiring board has apertures formed such that multiple portions of the conductor pattern are exposed. The conductor pattern has conductor apertures. The outlines of the apertures and the conductor apertures overlap with each other, in a plan view, respectively.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: May 19, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Takaharu Nagasawa
  • Patent number: 9035446
    Abstract: Provided is a power module. The power module includes a power semiconductor chip. The power module further includes a case that accommodates the power semiconductor chip. A silicone gel seals the power semiconductor chip within the case. The silicone gel including a heat-resistant silicone gel containing 20 to 100 mass ppm of a metal complex comprising a metal selected from a group consisting of iron and platinum.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: May 19, 2015
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Daisuke Kimijima, Yuji Ichimura
  • Patent number: 9018750
    Abstract: Disclosed is a package that includes a wafer substrate and a metal stack seed layer. The metal stack seed layer includes a titanium thin film outer layer. A resist layer is provided in contact with the titanium thin film outer layer of the metal stack seed layer, the resist layer forming circuitry. A method for manufacturing a package is further disclosed. A metal stack seed layer having a titanium thin film outer layer is formed. A resist layer is formed so as to be in contact with the titanium thin film outer layer of the metal stack seed layer, and circuitry is formed from the resist layer.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: April 28, 2015
    Assignee: Flipchip International, LLC
    Inventors: Robert Forcier, Douglas Scott
  • Patent number: 9018753
    Abstract: A method is described for making electronic modules includes molding onto a substrate panel a matrix panel defining a plurality of cavities, attaching semiconductor die to the substrate panel in respective cavities of the molded matrix panel, electrically connecting the semiconductor die to the substrate panel, affixing a cover to the molded matrix panel to form an electronic module assembly, mounting the electronic module assembly on a carrier tape, and separating the electronic module assembly into individual electronic modules. An electronic module is described which includes a substrate, a wall member molded onto the substrate, the molded wall member defining a cavity, at least one semiconductor die attached to the substrate in the cavity and electrically connected to the substrate, and a cover affixed to the molded wall member over the cavity.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: April 28, 2015
    Assignee: STMicroelectronics Pte Ltd
    Inventor: Wing Shenq Wong
  • Patent number: 9013035
    Abstract: Methods and apparatuses for improved integrated circuit (IC) packages are described herein. In an aspect, an IC device package includes an IC die having a contact pad, where the contact pad is located on a hotspot of the IC die. The hotspot is thermally coupled to a thermal interconnect member. In an aspect, the package is encapsulated in a mold compound. In a further aspect, a heat spreader is attached to the mold compound, and is thermally coupled to the thermal interconnect member. In another aspect, a thermal interconnect member thermally is coupled between the heat spreader and the substrate.
    Type: Grant
    Filed: September 5, 2006
    Date of Patent: April 21, 2015
    Assignee: Broadcom Corporation
    Inventors: Sam Ziqun Zhao, Rezaur Rahman Khan
  • Patent number: 8993356
    Abstract: A method for constructing an electrical circuit that includes at least one semiconductor chip encapsulated with a potting compound is disclosed. The method includes applying a galvanic layer arrangement for forming an electrochemical element on an element of the electrical circuit including the at least one semiconductor chip.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: March 31, 2015
    Assignee: Robert Bosch GmbH
    Inventors: Tjalf Pirk, Juergen Butz, Axel Franke, Frieder Haag, Heribert Weber, Arnim Hoechst, Sonja Knies
  • Patent number: 8987921
    Abstract: A method for producing a component with at least one micro-structured or nano-structured element includes applying at least one micro-structured or nano-structured element to a carrier. The element has at least one area configure to make contact and the element is applied to the carrier such that the at least one area adjoins the carrier. The element is enveloped in an enveloping compound and the element-enveloping compound composite is detached from the carrier. A first layer comprising electrically conductive areas is applied to the side of the element-enveloping compound composite that previously adjoined the carrier. At least one passage is introduced into the enveloping compound. A conductor layer is applied to the surface of the passage and at least to a section of the layer comprising the first electrically conductive areas to generate a through contact, which enables space-saving contacting. A component is formed from the method.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: March 24, 2015
    Assignee: Robert Bosch GmbH
    Inventors: Ulrike Scholz, Ralf Reichenbach
  • Patent number: 8980696
    Abstract: A method of packaging a semiconductor die includes the use of an embedded ground plane or drop-in embedded unit. The embedded unit is a single, stand-alone unit with at least one cavity. The embedded unit is placed on and within an encapsulation area of a process mounting surface. The embedded unit may have different sizes and shapes and a number of different cavities that can be placed in a predetermined position on a substrate, panel or tape during processing of semiconductor dies that are embedded into redistributed chip package (RCP) or wafer level package (WFL) panels. The embedded unit provides the functionality and design flexibility to run a number of embedded units and semiconductor dies or components having different sizes and dimensions in a single processing panel or batch and reduces die drift, movement or skew during encapsulation and post-encapsulation cure.
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: March 17, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Dominic Koey Poh Meng, Zhiwei Gong, Kesvakumar V. C. Muniandy, Weng Foong Yap
  • Patent number: 8969140
    Abstract: A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: March 3, 2015
    Assignee: Intel Corporation
    Inventors: Robert L. Sankman, John S. Guzek
  • Patent number: 8963345
    Abstract: An encapsulation device including two casings made of a flexible polymer material, each delimiting a sealed space, and at least one hydrophobic material filling each of the casings, the casings being stacked and sealingly interconnected at peripheral edges thereof, a sealed space then being defined between the two casings for receiving a device to be encapsulated.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: February 24, 2015
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventors: Stephane Cros, Nicole Alberola, Jean-Paul Garandet, Arnaud Morlier
  • Patent number: 8963195
    Abstract: A lighting element, comprising: a first substrate; a first and second conductive elements located on the first substrate; a light-emitting element having first and second contacts that are both on a first surface of the light-emitting element, the first contact being electrically connected to the first conductive element, the second contact being electrically connected to the second conductive element, and the light-emitting element emitting light from a second surface opposite the first surface; a top layer adjacent to the second surface; and an affixing layer located between the first substrate and the top layer, the affixing layer affixing the top layer to the first substrate; and a heat spreading layer having a third surface and a fourth surface opposite the third surface, the heat spreading layer being affixed beneath the first flexible substrate at the third surface, wherein the flexible top layer is substantially transparent to light.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: February 24, 2015
    Assignee: Grote Industries, LLC
    Inventors: Timothy Webster Brooks, Scott J. Jones, Martin J. Marx, Cesar Perez-Bolivar, James E. Roberts, George M. Richardson, II
  • Patent number: 8956921
    Abstract: A method of molding a semiconductor package includes coating liquid molding resin or disposing solid molding resin on a top surface of a semiconductor chip arranged on a substrate. The solid molding resin may include powdered molding resin or sheet-type molding resin. In a case where liquid molding resin is coated on the top surface of the semiconductor chip, the substrate is mounted between a lower molding and an upper molding, and then melted molding resin is filled in a space between the lower molding and the upper molding. In a case where the solid molding resin is disposed on the top surface of the semiconductor chip, the substrate is mounted on a lower mold and then the solid molding resin is heated and melts into liquid molding resin having flowability. An upper mold is mounted on the lower mold, and melted molding resin is filled in a space between the lower molding and the upper molding.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-young Ko, Jae-yong Park, Heui-seog Kim, Ho-geon Song
  • Patent number: 8957489
    Abstract: A component assembly including a carrier element including a first contact face and a semiconductor component disposed on the carrier element, wherein the semiconductor component includes a second contact face. The component assembly further includes a contact-making bonding wire, wherein one end of the contact-making bonding wire is connected to the first contact face and a second end of the contact-making bonding wire is connected to the second contact face. The component assembly includes a flow stop bonding wire positioned on the second contact face, wherein the flow stop bonding wire defines on the second contact face a first zone and a second zone. An encapsulation material is applied from the first zone to the first contact face so as to define an encapsulation for the flow stop bonding wire, wherein the flow stop bonding wire prevents an uncontrolled flow of the encapsulation material into the second zone.
    Type: Grant
    Filed: March 3, 2009
    Date of Patent: February 17, 2015
    Assignee: Dr. Johannes Heidenhain GmbH
    Inventor: Roman Angerer
  • Patent number: 8946759
    Abstract: Disclosed is an organic light emitting display device which prevents or inhibits external gas, such as, oxygen or moisture, from penetrating into a display unit and reinforces a mechanical strength by providing a first sealant and a second sealant. The organic light emitting display device may include: a first substrate; a display unit on the first substrate; a second substrate covering the display unit; a first sealant adhering the first substrate to the second substrate; and a second sealant around the first sealant, the second sealant sealing the first substrate and the second substrate. A filler may be included in the second sealant, and a particle size of the filler may be larger than a gap between the first substrate and the second substrate.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: February 3, 2015
    Assignee: Samsung-Display Co., Ltd.
    Inventors: Jung Woo Moon, Hyun Joon Oh
  • Patent number: 8946886
    Abstract: An electronic component package includes a substrate having a first surface, an electronic component mounted to the substrate, traces on the first surface, a terminal on the first surface, and a solder mask on the first surface. The solder mask includes a solder mask opening exposing the terminal. An electrically conductive coating and/or conductive coating feature is formed on the solder mask and extends into the solder mask opening to contact and be electrically connected to the terminal. The conductive coating may be grounded to shield the electronic component from electromagnetic interference (EMI). Further, the conductive coating provides a ground plane for the traces facilitating impedance matching of signals on the traces. In addition, the conductive coating has a high thermal conductivity thus enhancing heat dissipation from the electronic component.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: February 3, 2015
    Inventors: Ruben Fuentes, August Joseph Miller, Jr.
  • Patent number: 8916423
    Abstract: A method of manufacturing a semiconductor device includes: forming a first electrode on a first semiconductor substrate; coating the semiconductor substrate with an insulating material having a first viscosity at a first temperature, having a second viscosity lower than the first viscosity at a second temperature higher than the first temperature, and having a third viscosity higher than the second viscosity at a third temperature higher than the second temperature; and forming a first insulating film by curing the insulating material. In this method, the forming the first insulating film includes: bringing the insulating material to the second viscosity by heating the insulating material under a first condition; and bringing the insulating material to the third viscosity by heating the insulating material under a second condition. The first condition and the second condition are different in their temperature rising rate.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: December 23, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Tamotsu Owada, Hikaru Ohira, Hirosato Ochimizu
  • Patent number: 8907437
    Abstract: A current sensor packaged in an integrated circuit package to include a magnetic field sensing circuit, a current conductor and an insulator that meets the safety isolation requirements for reinforced insulation under the UL 60950-1 Standard is presented. The insulator is provided as an insulation structure having at least two layers of thin sheet material. The insulation structure is dimensioned so that plastic material forming a molded plastic body of the package provides a reinforced insulation. According to one embodiment, the insulation structure has two layers of insulating tape. Each insulating tape layer includes a polyimide film and adhesive. The insulation structure and the molded plastic body can be constructed to achieve at least a 500 VRMS working voltage rating.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: December 9, 2014
    Assignee: Allegro Microsystems, LLC
    Inventors: Shaun D. Milano, Weihua Chen