Characterized By Material, E.g., Carbon (epo) Patents (Class 257/E23.117)
  • Patent number: 11889625
    Abstract: A module includes: a wiring board as a ceramic board having a first main surface; a first component and a second component that are mounted on the first main surface; at least one conductive member disposed on the first main surface between the first component and the second component; a sealing resin that seals the first component, the second component, and the conductive member; and a shield film that covers an upper surface and a side surface of the sealing resin and a side surface of the wiring board. The shield film is electrically connected to a ground conductor. The conductive member is formed by firing simultaneously with the wiring board, and electrically connected to the ground conductor and electrically connected to the shield film.
    Type: Grant
    Filed: December 15, 2021
    Date of Patent: January 30, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Akio Katsube
  • Patent number: 11398585
    Abstract: The present invention provides a hermetic package, including a ceramic base and a glass cover hermetically integrated with each other via a sealing material layer, wherein the ceramic base includes 0.1 mass % to 10 mass % of a black pigment, and wherein a difference between: a light absorption rate of the ceramic base at a wavelength of 808 nm when converted to 0.5 mm; and a light absorption rate of the sealing material layer at a wavelength of 808 nm when converted to 0.005 mm is 30% or less.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: July 26, 2022
    Assignee: NIPPON ELECTRIC GLASS CO., LTD.
    Inventor: Toru Shiragami
  • Patent number: 10644210
    Abstract: A method of manufacturing a light emitting element mounting base member includes: providing a first insulating member in a plate shaped having at least one recess portion or at least one through-hole; disposing in the recess portion or in the through-hole a light blocking resin and a plurality of core members each equipped with a second insulating member having light reflectivity on each surface of a plurality of electrical conductor cores; and exposing at least one of the surface of the electrical conductor cores from the second insulating members by removing each part of at least one of the second insulating members.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: May 5, 2020
    Assignee: NICHIA CORPORATION
    Inventor: Yukitoshi Marutani
  • Patent number: 10493488
    Abstract: An object has a durable superhydrophic, self-cleaning, and icephobic coating includes a substrate and a layer disposed on the substrate, the layer resulting from coating with a formulation having an effective amount of hierarchical structuring micro/nanoparticles, liquid silane having one or more groups configured to graft to a hierarchical structuring micro/nanoparticle and at least another group that results in hydrophobicity. The hierarchical structuring micro/nanoparticles are dispersed in the liquid silane. Another effective amount of synthetic adhesive, selected from thermosetting binders, moisture curing adhesives or polymers that form a strong interaction with a surface, is in solution with a solvent. Upon curing, the layer has a contact angle greater than 90° and a sliding angle of less than 10° and, less than 5% of an area of the layer is removed in a Tape test.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: December 3, 2019
    Assignee: The University of Masachusetts
    Inventors: Jason Constantinou, Hanna Dodiuk-Kenig, Carol M. F. Barry, Samuel Kenig, Joey L. Mead, Artee Panwar, Tehila Nahum, Sagar Mitra
  • Patent number: 9559029
    Abstract: A semiconductor device has a protective layer formed over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: January 31, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Il Kwon Shim, Yaojian Lin, Seng Guan Chow
  • Patent number: 8963309
    Abstract: A semiconductor device includes a first substrate. A first semiconductor die is mounted to the first substrate. A bond wire electrically connects the first semiconductor die to the first substrate. A first encapsulant is deposited over the first semiconductor die, bond wire, and first substrate. The first encapsulant includes a penetrable, thermally conductive material. In one embodiment, the first encapsulant includes a viscous gel. A second substrate is mounted over a first surface of the first substrate. A second semiconductor die is mounted to the second substrate. The second semiconductor die is electrically connected to the first substrate. The first substrate is electrically connected to the second substrate. A second encapsulant is deposited over the first semiconductor die and second semiconductor die. An interconnect structure is formed on a second surface of the first substrate, opposite the first surface of the first substrate.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: February 24, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Byung Tai Do, Seng Guan Chow, Heap Hoe Kuan, Linda Pei Ee Chua, Rui Huang
  • Patent number: 8896135
    Abstract: Disclosed is an encapsulation film. An inorganic oxide film is formed on an organic sealing layer by an atomic layer deposition (ALD) to form the encapsulation film, wherein the organic sealing layer is a polymer containing hydrophilic groups. The organic sealing layer and the inorganic oxide layer have covalent bondings therebetween. The encapsulation film can solve the moisture absorption problem of conventional organic sealing layers, thereby being suitable for use as a package of optoelectronic devices.
    Type: Grant
    Filed: January 4, 2011
    Date of Patent: November 25, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Ching-Chiun Wang, Kang-Feng Lee, Feng-Yu Tsai, Ming Horn Zheng, Chih-Yung Huang, Shih-Chin Lin, Jen-Rong Huang
  • Patent number: 8704361
    Abstract: A sealing glass, a sealing material, and a sealing material paste, which suppress metal deposition by reducing glass components (metal oxides) without decreasing the reactivity with and the adhesion to a semiconductor substrate. The sealing glass, contains a low temperature melting glass containing, by mass ratio: from 0.1 to 5% of at least one metal oxide selected from the group consisting of Fe, Mn, Cr, Co, Ni, Nb, Hf, W, Re, a rare earth element, and optionally Mo; and from 5 to 100 ppm by mass ratio of K2O, wherein the low temperature melting glass has a softening point of at most 430° C. The sealing material device, contains the sealing glass and an inorganic filler in an amount of from 0 to 40% by volume ratio. The sealing material paste contains a mixture of the sealing material and a vehicle.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: April 22, 2014
    Assignee: Asahi Glass Company, Limited
    Inventor: Hiroki Takahashi
  • Publication number: 20140061873
    Abstract: A method for processing a wafer in accordance with various embodiments may include: forming a passivation over the wafer; forming a protection layer over at least a surface of the passivation facing away from the wafer, wherein the protection layer includes a material that is selectively etchable to a material of the passivation; forming a mask layer over at least a surface of the protection layer facing away from the wafer, wherein the mask layer includes a material that is selectively etchable to the material of the protection layer; etching the wafer using the mask layer as a mask; selectively etching the material of the mask layer to remove the mask layer from the protection layer, after etching the wafer; and selectively etching the material of the protection layer to remove the protection layer from the passivation, after selectively etching the material of the mask layer.
    Type: Application
    Filed: August 31, 2012
    Publication date: March 6, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Joachim Hirschler, Gudrun Stranzl
  • Patent number: 8659125
    Abstract: A chipset package structure includes a carrier, a plurality of pinouts, at least one semiconductor package preforms, at least one electromagnetic shielding layer and a protective layer. The pinouts are disposed on the carrier. The semiconductor package preforms is disposed on the second surface of the carrier and electrically connected to the pinouts. The electromagnetic shielding layer is disposed on the semiconductor package preforms and the electromagnetic shielding layer. At least one of the electromagnetic shielding layers comprises a carbon nanotube film structure. The protective layer covers the electromagnetic shielding layer.
    Type: Grant
    Filed: October 9, 2008
    Date of Patent: February 25, 2014
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Wen-Hua Chen, Zheng-He Feng, Ping-Yang Chuang
  • Patent number: 8648479
    Abstract: According to the present invention, an epoxy resin composition for semiconductor encapsulant including (A) an epoxy resin, (B) a curing agent, (C) an inorganic filler, and (D) a compound in which a copolymer of a 1-alkene having 5 to 80 carbon atoms and maleic anhydride is esterified with an alcohol having 5 to 25 carbon atoms in the presence of a compound represented by General Formula (1), wherein R1 in General Formula (1) is selected from the group consisting of an alkyl group having 1 to 5 carbon atoms, a halogenated alkyl group having 1 to 5 carbon atoms, and an aromatic group having 6 to 10 carbon atoms is provided.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: February 11, 2014
    Assignee: Sumitomo Bakelite Co., Ltd.
    Inventor: Jun-ichi Tabei
  • Patent number: 8604599
    Abstract: A semiconductor housing is provided that includes a metal support and a semiconductor body, a bottom side thereof being connected to the metal support. The semiconductor body has metal surfaces that are connected to pins by bond wires and a plastic compound, which completely surrounds the bond wires and partially surrounds the semiconductor body. The plastic compound has an opening on the top side of the semiconductor body, and a barrier is formed on the top side of the semiconductor body. The barrier has a top area and a base area spaced from the edges of the semiconductor body and an internal clearance of the barrier determines a size of the opening. Whereby, a portion of the plastic compound has a height greater than the barrier, and a fixing layer is formed between the base area of the barrier and the top side of the semiconductor body.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: December 10, 2013
    Assignee: Micronas GmbH
    Inventors: Tobias Kolleth, Pascal Stumpf, Christian Joos
  • Publication number: 20130200502
    Abstract: A method of manufacturing a semiconductor device includes providing a transfer foil. A plurality of semiconductor chips is placed on and adhered to the transfer foil. The plurality of semiconductor chips adhered to the transfer foil is placed over a multi-device carrier. Heat is applied to laminate the transfer foil over the multi-device carrier, thereby accommodating the plurality of semiconductor chips between the laminated transfer foil and the multi-device carrier.
    Type: Application
    Filed: February 8, 2012
    Publication date: August 8, 2013
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Ivan Nikitin, Stefan Landau, Joachim Mahler, Alexander Heinrich, Ralf Wombacher
  • Patent number: 8502401
    Abstract: A polymeric composition comprising a first polymer chosen from a poly(arylene ether) polymer including polymer repeat units of the following structure: —(O—Ar1—O—Ar2—O—)m—(—O—Ar3—O—Ar4—O)n- where Ar1, Ar2, Ar3, and Ar4 are identical or different aryl radicals, m is 0 to 1, n is 1 m; a polysulfone, a polyimide, a poly(etherketone), a polyurea, a polyurethane, and combinations thereof and a second polymer comprising a per(phenylethynyl) arene polymer derivative. Cured films containing the polymer can exhibit at least one of the following properties: Tg from 160° C. to 180° C., a dielectric constant below 2.7 with frequency independence, and a maximum moisture absorption of less than 0.17 wt %. Accordingly, the polymer is especially useful, for example, in interlayer dielectrics and in die-attach adhesives.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: August 6, 2013
    Assignee: Delsper LP
    Inventors: William Franklin Burgoyne, Jr., Mark David Conner, Andrew Francis Nordquist, William Steven Collins
  • Patent number: 8481656
    Abstract: A silicone resin composition that exhibits low gas permeability and is suitable for encapsulating optical semiconductors. The composition includes: (A) an organopolysiloxane having a specific structure containing two or more alkenyl groups, (B) an organohydrogenpolysiloxane composed of two organohydrogenpolysiloxanes having specific structures, in which the mass ratio between the two organohydrogenpolysiloxanes is within a range from 10:90 to 90:10, in an amount that provides 0.4 to 4.0 mols of silicon atom-bonded hydrogen atoms within the component (B) per 1 mol of alkenyl groups within the component (A), and (C) an addition reaction catalyst.
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: July 9, 2013
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Tsutomu Kashiwagi, Yoshihira Hamamoto
  • Publication number: 20130134606
    Abstract: A semiconductor package may include a substrate including a substrate pad on a top surface thereof; at least one semiconductor chip including a connection terminal electrically connected to the substrate on an active surface thereof, and mounted on the substrate; a heat release pattern formed between the substrate and the at least one semiconductor chip and configured to generate heat; and underfill resin underfilled between the substrate and the at least one semiconductor chip and comprising fillers. A semiconductor package may include a substrate including a substrate pad on a top surface thereof and a first heat release pattern configured to generate heat, and a semiconductor chip including a bonding pad formed on an active surface facing the substrate and a second heat release pattern configured to generate heat.
    Type: Application
    Filed: August 16, 2012
    Publication date: May 30, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yun-hyeok IM, Won-keun KIM, Tae-Je CHO, Kyol PARK
  • Publication number: 20130105997
    Abstract: A silicone resin composition contains a first organopolysiloxane having, in one molecule, both at least two ethylenically unsaturated hydrocarbon groups and at least two silanol groups; a second organopolysiloxane having, in one molecule, at least two hydrosilyl groups without having an ethylenically unsaturated hydrocarbon group; a hydrosilylation catalyst; and a hydrosilylation retarder.
    Type: Application
    Filed: October 11, 2012
    Publication date: May 2, 2013
    Inventors: Hirokazu MATSUDA, Ryuichi KIMURA, Hiroyuki KATAYAMA
  • Patent number: 8421242
    Abstract: A semiconductor package is provided. The semiconductor package includes an organic substrate, a stiffness layer, and a chip subassembly. The stiffness layer is formed on the organic substrate. The chip subassembly is disposed on the stiffness layer. The chip subassembly includes at least a first chip, a second chip, and a third chip. The second chip is disposed between the first chip and the third chip in a stacked orientation. The first chip, the second chip, and the third chip have the function of proximity communication.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: April 16, 2013
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsiao-Chuan Chang, Tsung-Yueh Tsai, Yi-Shao Lai, Chang-Lin Yeh, Ming-Hsiang Cheng
  • Patent number: 8405233
    Abstract: A flexible barrier film has a thickness of from greater than zero to less than 5,000 nanometers and a water vapor transmission rate of no more than 1×10?2 g/m2/day at 22° C. and 47% relative humidity. The flexible barrier film is formed from a composition, which comprises a multi-functional acrylate. The composition further comprises the reaction product of an alkoxy-functional organometallic compound and an alkoxy-functional organosilicon compound. A method of forming the flexible barrier film includes the steps of disposing the composition on a substrate and curing the composition to form the flexible barrier film. The flexible barrier film may be utilized in organic electronic devices.
    Type: Grant
    Filed: January 13, 2010
    Date of Patent: March 26, 2013
    Assignee: Dow Corning Corporation
    Inventors: John Blizzard, James Steven Tonge, William Kenneth Weidner
  • Patent number: 8399366
    Abstract: A method is provided for forming a semiconductor device. The method includes providing a substrate on a substrate holder in a process chamber, where the substrate contains a raised feature having a top surface and a sidewall surface, and flowing a process gas into the process chamber, where the process gas contains a hydrocarbon gas, an oxygen-containing gas, and optionally argon or helium. The method further includes maintaining a process gas pressure of at least 1 Torr in the process chamber, forming a plasma from the process gas using a microwave plasma source, and exposing the substrate to the plasma to deposit a conformal amorphous carbon film over the surfaces of the raised feature.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: March 19, 2013
    Assignee: Tokyo Electron Limited
    Inventor: Hiroyuki Takaba
  • Patent number: 8377753
    Abstract: A semiconductor device including: a die pad, a die on the die pad, and resin encapsulating the die and forming an isolation thickness over the die pad, the resin including a mounting aperture and a major surface configured for mounting to an external device, the major surface having a non warpage compensation portion adjacent the die and a warpage compensation portion in a relatively thermally inactive zone with an approximate discontinuity and/or abrupt change in gradient between the non warpage compensation portion and the warpage compensation portion.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: February 19, 2013
    Assignee: Infineon Technologies AG
    Inventors: Chai Wei Heng, Wae Chet Yong, Stanley Job Doraisamy, Khai Huat Jeffrey Low, Gerhard Deml
  • Patent number: 8373287
    Abstract: A polymeric composition comprising a first polymer chosen from a poly(arylene ether) polymer including polymer repeat units of the following structure: —(O—Ar1—O—Ar2—O—)m—(—O—Ar3—O—Ar4—O)n- where Ar1, Ar2, Ar3, and Ar4 are identical or different aryl radicals, m is 0 to 1, n is 1 m; a polysulfone, a polyimide, a poly(etherketone), a polyurea, a polyurethane, and combinations thereof and a second polymer comprising a per(phenylethynyl) arene polymer derivative. Cured films containing the polymer can exhibit at least one of the following properties: Tg from 160° C. to 180° C., a dielectric constant below 2.7 with frequency independence, and a maximum moisture absorption of less than 0.17 wt %. Accordingly, the polymer is especially useful, for example, in interlayer dielectrics and in die-attach adhesives.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: February 12, 2013
    Assignee: Greene, Tweed IP, Inc.
    Inventors: William Franklin Burgoyne, Jr., Mark David Conner, Andrew Francis Nordquist, William Steven Collins
  • Publication number: 20130032955
    Abstract: A system and method for a low-k dielectric layer are provided. A preferred embodiment comprises forming a matrix and forming a porogen within the matrix. The porogen comprises an organic ring structure with fewer than fifteen carbons and a large percentage of single bonds. Additionally, the porogen may have a viscosity greater than 1.3 and a Reynolds numbers less than 0.5.
    Type: Application
    Filed: August 5, 2011
    Publication date: February 7, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Joung-Wei Liou, Hui-Chun Yang, Yu-Yun Peng, Keng-Chu Lin
  • Publication number: 20130009327
    Abstract: Disclosed is a resin composition for semiconductor encapsulation, containing an epoxy resin (A), a curing agent (B), and an inorganic filler material (C), the epoxy resin (A) including an epoxy resin (A-1) represented by formula (1), and the epoxy resin (A-1) containing a component represented by the formula (1) in which n?1, and a component (a1) represented by the formula (1) in which n=0 (wherein in the formula (1), R1 represents a hydrocarbon group having 1 to 6 carbon atoms; R2 represents a hydrocarbon group having 1 to 6 carbon atoms, or an aromatic hydrocarbon group having 6 to 14 carbon atoms, while R1s and R2s may be respectively identical with or different from each other; a represents an integer from 0 to 4; b represents an integer from 0 to 4; and n represents an integer of 0 or larger).
    Type: Application
    Filed: March 14, 2011
    Publication date: January 10, 2013
    Inventor: Yusuke Tanaka
  • Patent number: 8310064
    Abstract: Semiconductor devices are provided that employ voltage switchable materials for over-voltage protection. In various implementations, the voltage switchable materials are substituted for conventional die attach adhesives, underfill layers, and encapsulants. While the voltage switchable material normally functions as a dielectric material, during an over-voltage event the voltage switchable material becomes electrically conductive and can conduct electricity to ground. Accordingly, the voltage switchable material is in contact with a path to ground such as a grounded trace on a substrate, or a grounded solder ball in a flip-chip package.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: November 13, 2012
    Assignee: Shocking Technologies, Inc.
    Inventor: Lex Kosowsky
  • Patent number: 8288851
    Abstract: A system for hermetically sealing devices includes a substrate, which includes a plurality of individual chips. Each of the chips includes a plurality of devices and each of the chips are arranged in a spatial manner as a first array. The system also includes a transparent member of a predetermined thickness, which includes a plurality of recessed regions arranged in a spatial manner as a second array and each of the recessed regions are bordered by a standoff region. The substrate and the transparent member are aligned in a manner to couple each of the plurality of recessed regions to a respective one of said plurality of chips. Each of the chips within one of the respective recessed regions is hermetically sealed by contacting the standoff region of the transparent member to the plurality of first street regions and second street regions using at least a bonding process to isolate each of the chips within one of the recessed regions.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: October 16, 2012
    Assignee: Miradia Inc.
    Inventors: Xiao Yang, Dongmin Chen
  • Publication number: 20120256325
    Abstract: A silicone resin composition that exhibits low gas permeability and is suitable for encapsulating optical semiconductors. The composition includes: (A) an organopolysiloxane having a specific structure containing two or more alkenyl groups, (B) an organohydrogenpolysiloxane composed of two organohydrogenpolysiloxanes having specific structures, in which the mass ratio between the two organohydrogenpolysiloxanes is within a range from 10:90 to 90:10, in an amount that provides 0.4 to 4.0 mols of silicon atom-bonded hydrogen atoms within the component (B) per 1 mol of alkenyl groups within the component (A), and (C) an addition reaction catalyst.
    Type: Application
    Filed: April 6, 2012
    Publication date: October 11, 2012
    Applicant: Shin-Etsu Chemical Co., Ltd.
    Inventors: Tsutomu KASHIWAGI, Yoshihira Hamamoto
  • Publication number: 20120199991
    Abstract: A semiconductor device includes: a semiconductor chip including a nitride semiconductor layered structure including a carrier transit layer and a carrier supply layer; a first resin layer on the semiconductor chip, the first resin layer including a coupling agent; a second resin layer on the first resin layer, the second resin layer including a surfactant; and a sealing resin layer to seal the semiconductor chip with the first resin layer and the second resin layer.
    Type: Application
    Filed: December 20, 2011
    Publication date: August 9, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Keishiro OKAMOTO, Tadahiro Imada, Nobuhiro Imaizumi, Keiji Watanabe
  • Publication number: 20120175751
    Abstract: Disclosed are group IV metal-containing precursors and their use in the deposition of group IV metal-containing films{nitride, oxide and metal) at high process temperature. The use of cyclopentadienyl and imido ligands linked to the metal center secures thermal stability, allowing a large deposition temperature window, and low impurity contamination. The group IV metal (titanium, zirconium, hafnium)-containing fvm depositions may be carried out by thermal and/or plasma-enhanced CVD, ALD, and pulse CVD.
    Type: Application
    Filed: July 14, 2010
    Publication date: July 12, 2012
    Inventors: Julien Gatineau, Changhee Ko
  • Publication number: 20120168962
    Abstract: A thin wafer protection device includes a wafer having a plurality of semiconductor chips. The wafer has a first side and an opposite second side. A plurality of dies is over the first side of the wafer, and at least one of the plurality of dies is bonded to at least one of the plurality of semiconductor chips. A wafer carrier is over the second side of the wafer. An encapsulating layer is over the first side of the wafer and the plurality of dies, and the encapsulating layer has a planar top surface. An adhesive tape is over the planar top surface of the encapsulating layer.
    Type: Application
    Filed: March 13, 2012
    Publication date: July 5, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ku-Feng YANG, Weng-Jin WU, Wen-Chih CHIOU, Tsung-Ding WANG
  • Publication number: 20120153512
    Abstract: The present invention relates to an epoxy resin composition for semiconductor encapsulation, including the following components (A) to (E):(A) an epoxy resin; (B) a phenol resin other than component (C); (C) a silane-modified phenol resin represented by Formula (1) as defined in the specification; (D) a curing accelerator; and (E) an inorganic filler; wherein the component (C) is contained in an amount of 0.8 to 30.0% by weight based on a total weight of organic components in the epoxy resin composition.
    Type: Application
    Filed: December 21, 2011
    Publication date: June 21, 2012
    Applicant: NITTO DENKO CORPORATION
    Inventors: Naoya SUGIMOTO, Tomoaki ICHIKAWA, Mitsuaki FUSUMADA, Tomohito IWASHIGE
  • Publication number: 20120139133
    Abstract: A sealing glass, a sealing material, and a sealing material paste, which suppress metal deposition by reducing glass components (metal oxides) without decreasing the reactivity with and the adhesion to a semiconductor substrate. The sealing glass, contains a low temperature melting glass containing, by mass ratio: from 0.1 to 5% of at least one metal oxide selected from the group consisting of Fe, Mn, Cr, Co, Ni, Nb, Hf, W, Re, a rare earth element, and optionally Mo; and from 5 to 100 ppm by mass ratio of K2O, wherein the low temperature melting glass has a softening point of at most 430° C. The sealing material device, contains the sealing glass and an inorganic filler in an amount of from 0 to 40% by volume ratio. The sealing material paste contains a mixture of the sealing material and a vehicle.
    Type: Application
    Filed: January 31, 2012
    Publication date: June 7, 2012
    Applicant: Asahi Glass Company, Limited
    Inventor: Hiroki TAKAHASHI
  • Patent number: 8187795
    Abstract: Described herein are processing techniques for fabrication of stretchable and/or flexible electronic devices using laser ablation patterning methods. The laser ablation patterning methods utilized herein allow for efficient manufacture of large area (e.g., up to 1 mm2 or greater or 1 m2 or greater) stretchable and/or flexible electronic devices, for example manufacturing methods permitting a reduced number of steps. The techniques described herein further provide for improved heterogeneous integration of components within an electronic device, for example components having improved alignment and/or relative positioning within an electronic device. Also described herein are flexible and/or stretchable electronic devices, such as interconnects, sensors and actuators.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: May 29, 2012
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Kanti Jain, Kevin Lin
  • Publication number: 20120126435
    Abstract: Provided are a curable composition for semiconductor encapsulation which produces a cured product that is excellent in heat resistance, electrical insulation properties at high temperatures, flexibility and heat cycle resistance, and a semiconductor device encapsulated by curing this curable composition. Specifically, there is provided a curable composition for semiconductor encapsulation containing, as component (A), a particular SiH group-containing siloxane compound; as component (B), a particular vinyl group-containing siloxane compound; as component (C), a compound having at least three SiH groups or at least three vinyl groups; and as component (D), a hydrosilylation catalyst.
    Type: Application
    Filed: May 26, 2011
    Publication date: May 24, 2012
    Applicant: ADEKA CORPORATION
    Inventors: Ken-ichiro Hiwatari, Isamu Yumoto
  • Patent number: 8178983
    Abstract: It is an object of the present invention to provide a water repellant composition for a substrate to be exposed which inhibits the back side of a substrate to be exposed from being contaminated by an immersion liquid, can improve adhesion between a film to be processed and an organic film directly overlying that film to inhibit film peeling, and has excellent workability, a method for forming a resist pattern, an electronic device produced by the formation method, a treatment method for imparting water repellency to a substrate to be exposed, a water repellent set for a substrate to be exposed, and a treatment method for imparting water repellency to a substrate to be exposed using the same. A water repellent composition for a substrate to be exposed including at least an organosilicon compound represented by the following general formula (1) and a solvent is used.
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: May 15, 2012
    Assignees: Renesas Electronics Corporation, Asahi Glass Company, Limited
    Inventors: Takeo Ishibashi, Miwako Ishibashi, legal representative, Mamoru Terai, Takuya Hagiwara, Osamu Yokokoji, Yoko Takebe
  • Publication number: 20120038067
    Abstract: The disclosure provides methods and materials suitable for use as encapsulation barriers in electronic devices. In one embodiment, for example, there is provided an electroluminescent device or other electronic device encapsulated by alternating layers of a silicon-containing bonding material and a ceramic material. The encapsulation methods provide, for example, electronic devices with increased stability and shelf-life. The invention is useful, for example, in the field of microelectronic devices.
    Type: Application
    Filed: March 4, 2009
    Publication date: February 16, 2012
    Inventors: Yigal D. Blum, William Siu-Keung Chu, David Brent MacQueen, Yijian Shi
  • Publication number: 20120025405
    Abstract: Disclosed is a liquid encapsulating resin composition containing an epoxy resin (A), an amine type curing agent (B), and a basic compound (C), wherein, in case that the liquid encapsulating resin composition is filled between a semiconductor element and a substrate connected to each other by solder bumps, the residue of a fluxing agent used for forming the solder bump connection is removed.
    Type: Application
    Filed: January 28, 2010
    Publication date: February 2, 2012
    Inventor: Hiroshi Ito
  • Patent number: 8067841
    Abstract: A semiconductor device including: a die pad, a die on the die pad, and resin encapsulating the die and forming an isolation thickness over the die pad, the resin including a mounting aperture and a major surface configured for mounting to an external device, the major surface having a non warpage compensation portion adjacent the die and a warpage compensation portion in a relatively thermally inactive zone with an approximate discontinuity and/or abrupt change in gradient between the non warpage compensation portion and the warpage compensation portion.
    Type: Grant
    Filed: February 25, 2008
    Date of Patent: November 29, 2011
    Assignee: Infineon Technologies AG
    Inventors: Chai Wei Heng, Wae Chet Yong, Stanley Job Doraisamy, Khai Huat Jeffrey Low, Gerhard Deml
  • Publication number: 20110260343
    Abstract: A polymeric composition comprising a first polymer chosen from a poly(arylene ether) polymer including polymer repeat units of the following structure: —(O—Ar1—O—Ar2—O—)m—(—O—Ar3—O—Ar4—O)n- where Ar1, Ar2, Ar3, and Ar4 are identical or different aryl radicals, m is 0 to 1, n is 1 m; a polysulfone, a polyimide, a poly(etherketone), a polyurea, a polyurethane, and combinations thereof and a second polymer comprising a per(phenylethynyl) arene polymer derivative. Cured films containing the polymer can exhibit at least one of the following properties: Tg from 160° C. to 180° C., a dielectric constant below 2.7 with frequency independence, and a maximum moisture absorption of less than 0.17 wt %. Accordingly, the polymer is especially useful, for example, in interlayer dielectrics and in die-attach adhesives.
    Type: Application
    Filed: August 10, 2009
    Publication date: October 27, 2011
    Applicant: AIR PRODUCTS AND CHEMICALS, INC.
    Inventors: William Franklin Burgoyne, JR., Mark David Conner, Andrew Francis Nordquist, William Steven Collins
  • Patent number: 8043899
    Abstract: A photosensitive resin composition comprising a photosensitive silicone compound of specified molecular weight having any of specified photosensitive substituents and a photopolymerization initiator in any of specified proportions is used. Thus, there can be obtained a resin composition containing a photosensitive silicone compound that provides a material suitable for a rewiring layer or a buffer coat material of LSI chip, less in a film loss between before and after curing and improved in the stickiness of pre-exposure stage. Further, there can be obtained a resin insulating film utilizing the resin composition.
    Type: Grant
    Filed: March 25, 2008
    Date of Patent: October 25, 2011
    Assignee: Asahi Kasei E-Materials Corporation
    Inventor: Tomohiro Yorisue
  • Patent number: 7989269
    Abstract: A semiconductor device is made by mounting a first semiconductor die to a first substrate, forming a first encapsulant over the first semiconductor die, and forming a second encapsulant over the first encapsulant. The second encapsulant is penetrable, thermally conductive material. A second semiconductor die is mounted to the second substrate. A bond wire electrically connects the second semiconductor die to the second substrate. A passive circuit element is mounted to the second substrate. Leading with the second encapsulant, the first substrate is pressed onto the second substrate so that the second encapsulant completely covers the second semiconductor die, bond wire, and passive circuit element. The second encapsulant is then cured. A third encapsulant is formed over the first and second substrates. A shield can be disposed over the second semiconductor die with openings for the second encapsulant to flow through when pressed onto the second substrate.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: August 2, 2011
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Byung Tai Do, Seng Guan Chow, Heap Hoe Kuan, Linda Pei Ee Chua, Rui Huang
  • Publication number: 20110156255
    Abstract: A variety of characteristics of an integrated circuit chip arrangement with a chip and package-type substrate are facilitated. In various example embodiments, a carbon nanotube-filled material (110) is used in an arrangement between an integrated circuit chip (220, 340) and a package-type substrate (210, 350). The carbon-nanotube filled material is used in a variety of applications, such as package encapsulation (as a mold compound (330)), die attachment (374) and flip-chip underfill (240). The carbon nanotubes facilitate a variety of characteristics such as strength, thermal conductivity, electrical conductivity, durability and flow.
    Type: Application
    Filed: November 4, 2005
    Publication date: June 30, 2011
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventors: Chris Wyland, Hendrikus Johannes Thoonen
  • Patent number: 7939916
    Abstract: An electronics package includes a wafer die substrate containing electronic circuits and having a top surface and a bottom surface. A top protective layer is substantially thinner than the substrate and covers the top surface. A bottom protective layer is substantially thinner than the substrate and covers the bottom surface. Circuit contacts are distributed about the bottom protective layer for electrically coupling the substrate electronic circuits to external electronic circuits.
    Type: Grant
    Filed: January 25, 2007
    Date of Patent: May 10, 2011
    Assignee: Analog Devices, Inc.
    Inventors: Alan O'Donnell, Oliver Kierse, Thomas M. Goida
  • Patent number: 7923844
    Abstract: Semiconductor devices are provided that employ voltage switchable materials for over-voltage protection. In various implementations, the voltage switchable materials are substituted for conventional die attach adhesives, underfill layers, and encapsulants. While the voltage switchable material normally functions as a dielectric cmaterial, during an over-voltage event the voltage switchable material becomes electrically conductive and can conduct electricity to ground. Accordingly, the voltage switchable material is in contact with a path to ground such as a grounded trace on a substrate, or a grounded solder ball in a flip-chip package.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: April 12, 2011
    Assignee: Shocking Technologies, Inc.
    Inventor: Lex Kosowsky
  • Patent number: 7906859
    Abstract: A semiconductor device includes a molding resin layer and a semiconductor element encapsulated with the molding resin layer. The molding resin layer has an opening. A surface of the semiconductor element is partially exposed outside the molding resin layer through the opening. A groove is located in the surface of the semiconductor element around the opening of the molding resin layer. The groove is filled with the molding resin layer to produce anchor effect that enhances adhesive force of the molding resin layer to the surface of the semiconductor element around the opening.
    Type: Grant
    Filed: August 12, 2008
    Date of Patent: March 15, 2011
    Assignee: DENSO CORPORATION
    Inventors: Tetsuo Yoshioka, Kenji Fukumura, Takahiko Yoshida
  • Publication number: 20110042784
    Abstract: Embodiments of the invention are generally related to packaging of integrated circuit devices, and more specifically to the placement of thermal paste for cooling an integrated circuit device during operation. A barrier element may be placed along at least one side of an integrated circuit chip. The barrier element may contain thermal paste pumped out during expansion and contraction of the package components to areas near the chip. The barrier element may also form a reservoir to replenish thermal paste that is lost during thermal pumping of the paste.
    Type: Application
    Filed: August 12, 2010
    Publication date: February 24, 2011
    Applicant: International Business Machines Corporation
    Inventors: David L. Edwards, Jean-Luc Landreville, Kathryn R. Lange, Carl Savard, Kamla K. Sikka, Hilton T. Toy
  • Publication number: 20100225010
    Abstract: The present invention relates to a composition for a thermosetting silicone resin, the composition including: (A) an organohydrogenpolysiloxane; (B) an alkenyl group-containing epoxy compound; (C) an alkenyl group-containing cyclic siloxane; and (D) a hydrosilylation catalyst, a thermosetting silicone resin composition obtained by reacting the composition and a production method thereof, a photosemiconductor element-encapsulating material including the thermosetting silicone resin composition, and a photosemiconductor device including a photosemiconductor element encapsulated with the resin composition or the photosemiconductor element-encapsulating material.
    Type: Application
    Filed: March 4, 2010
    Publication date: September 9, 2010
    Applicant: NITTO DENKO CORPORATION
    Inventor: Hiroyuki KATAYAMA
  • Publication number: 20100213606
    Abstract: A method for improving signal levels between capacitively-coupled chips in proximity communication (PxC) includes depositing a high permittivity dielectric material layer over a signal pad of a first chip, and placing a second chip in close proximity to the first chip such that faces of the signal pads align to enable for capacitive signal coupling. The high permittivity dielectric material layer that fills at least a portion of a gap between the first chip and the second chip, and improves capacitive coupling between signal pads of the first chip and the second chip by providing for an increased permittivity in the gap between the first chip and the second chip. The increased permittivity ensures that electric fields are substantially confined to a space between the signal pad of the first chip and the signal pad of the second chip.
    Type: Application
    Filed: February 24, 2009
    Publication date: August 26, 2010
    Applicant: SUN MICROSYSTEMS, INC.
    Inventors: Ashok Krishnamoorthy, John E. Cunningham
  • Publication number: 20100201004
    Abstract: A carbon/epoxy resin composition and a method of producing a carbon-epoxy dielectric using the same. The carbon/epoxy resin composition includes about 45 volume percent (volume %) to about 50 volume % of an epoxy composition, the epoxy composition including a bisphenol-based epoxy compound and an alicyclic epoxy compound, based on a total volume of the carbon/epoxy resin composition, about 2.0 volume % to about 3.1 volume % of carbon black, based on a total volume of the carbon/epoxy resin composition, about 80 parts by volume to about 104 parts by volume of an acid anhydride-based curing agent, based on 100 parts by volume of the epoxy composition, and about 1 part by volume to about 3 parts by volume of a tertiary alkylamine-based curing catalyst, based on 100 parts by volume of the epoxy composition.
    Type: Application
    Filed: July 27, 2009
    Publication date: August 12, 2010
    Applicant: SAMSUNG ELECTRONICS CO., LTD
    Inventors: Yoo-Seong YANG, Eun-Sung LEE, Sang-Soo JEE, Soon-Jae KWON
  • Patent number: 7768141
    Abstract: A dicing die attachment film includes a die attachment layer attached to one surface of a semiconductor wafer; a dicing film layer attached to a dicing die that is used for cutting the semi-conductor wafer into die units; and an intermediate layer laminated between the die attachment layer and the dicing film layer. The intermediate layer has a modulus of 100 to 3000 MPa, which is greater than a modulus of the die attachment layer and the dicing film layer.
    Type: Grant
    Filed: February 14, 2007
    Date of Patent: August 3, 2010
    Assignee: LG Innotek Co., Ltd.
    Inventors: Joon-Mo Seo, Byoung-Un Kang, Kyung-Tae Wi, Jae-Hoon Kim, Tae-Hyun Sung, Soon-Young Hyun, Byoung-Kwang Lee, Chan-Young Choi