Gaseous At Normal Operating Temperature Of Device (epo) Patents (Class 257/E23.138)
  • Patent number: 8927418
    Abstract: Systems and methods are provided for reducing a contact resistivity associated with a semiconductor device structure. A substrate including a semiconductor region is provided. One or more dielectric layers are formed on the semiconductor region, the one or more dielectric layers including an element. A gaseous material is applied on the one or more dielectric layers to change a concentration of the element in the one or more dielectric layers. A contact layer is formed on the one or more dielectric layers to generate a semiconductor device structure. The semiconductor device structure includes the contact layer, the one or more dielectric layers, and the semiconductor region. A contact resistivity associated with the semiconductor device structure is reduced by changing the concentration of the element in the one or more dielectric layers.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: January 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Cheng-Tung Lin, Teng-Chun Tsai, Li-Ting Wang, Chi-Yuan Chen, Hong-Mao Lee, Hui-Cheng Chang, Wei-Jung Lin, Bing-Hung Chen, Chia-Han Lai
  • Patent number: 8823154
    Abstract: An article and method of using spacer layer regions is provided, containing a gas compound, to reduce gas permeation through barrier films overlying a substrate comprising creating a spacer layer between one or more of the barrier films, wherein the spacer layer comprises at least one inert gaseous compound. In another embodiment, an article and method is provided comprising creating alternating thin films of hybridized sol-gel spin-on glass and PDMS based and olefin based elastomers.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: September 2, 2014
    Assignee: The Regents of The University of California
    Inventors: Craig J. Hawker, Jimmy Granstrom, Luis M. Campos, Jeffrey A. Gerbec, Motoko Furukawa
  • Publication number: 20120104589
    Abstract: A method for sealing through-holes in a material via material diffusion, without the deposition of a sealant material, is disclosed. The method is well suited to the fabrication and packaging of microsystems technology-based devices and systems. In some embodiments, the method comprises forming sacrificial material release through-holes through a structural layer, removing the sacrificial material via an etch that etches the sacrificial material through the release through-holes, and sealing of the release through-holes via material diffusion.
    Type: Application
    Filed: October 28, 2011
    Publication date: May 3, 2012
    Applicant: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Rishi Kant, Roger Thomas Howe
  • Publication number: 20120074555
    Abstract: A semiconductor package comprises: a substrate comprising a semiconductor device; a cap comprising a seal ring disposed over a surface of the cap; and a gap between the substrate and the surface of the cap. The seal ring comprises a tread comprising at least two columns.
    Type: Application
    Filed: September 29, 2010
    Publication date: March 29, 2012
    Applicant: Avago Technologies Wireless IP (Singapore) Pte. Ltd.
    Inventors: Rick Snyder, Joel Philliber
  • Publication number: 20100270667
    Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip, a first substrate, a second substrate and a metal cap. The chips are electrically connected to the first substrate, the second substrate is disposed between the chips, and the chips and the second substrate are disposed within the metal cap.
    Type: Application
    Filed: April 24, 2009
    Publication date: October 28, 2010
    Inventors: Chong Yee Tong, Hui Teng Wang
  • Patent number: 7714433
    Abstract: In one embodiment, the present invention includes a semiconductor package having a plurality of fan blades embedded within a first surface of the package, where a first group of the fan blades extend from a first side of the package and a second group of the fan blades extend from a second side of semiconductor package. The fan blades may be powered by piezoelectric devices to cause motion of the fan blades. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 9, 2007
    Date of Patent: May 11, 2010
    Assignee: Intel Corporation
    Inventors: Edoardo Campini, Javier Leija, William Handley
  • Publication number: 20100038801
    Abstract: A system and method prevent corrosive elements (or at least the oxidizing agent) from making contact with metal connections at the interface between two layers of a stacked IC device. When layers are positioned in proximity to each other, a cavity is formed at the boundary of the planar surfaces of the layers. This cavity is bounded by a peripheral seal between the layers. In one embodiment, a vacuum is created within the cavity thereby reducing the corrosive atmosphere within the cavity. In another embodiment, the cavity is filled with an inert gas, such as argon. Once the cavity has oxidizing elements reduced, the peripheral seal can be encapsulated to prevent seepage of contaminants into the cavity.
    Type: Application
    Filed: August 15, 2008
    Publication date: February 18, 2010
    Applicant: QUALCOMM Incorporated
    Inventors: Shiqun Gu, Matthew Nowak
  • Publication number: 20100025832
    Abstract: A MEMS device is packaged in a process which hydrogen (H) deuterium (D) for reduced stiction. H is exchanged with D by exposing the MEMS device with a deuterium source, such as deuterium gas or heavy water vapor, optionally with the assistance of a direct or downstream plasma.
    Type: Application
    Filed: July 31, 2008
    Publication date: February 4, 2010
    Inventors: Earl V. Atnip, Simon Joshua Jacobs
  • Publication number: 20090309203
    Abstract: A microelectromechanical system (MEMS) hermetically sealed package device that is less labor intensive to construct and thus less expensive to manufacture. An example package device includes a package having a bottom section and a lid. A MEMS die includes upper and lower plates made in accordance with upper sense plate design. The MEMS die is mounted to the bottom section. The upper and lower plates form a cavity that receives a MEMS device. The upper and lower plates are bonded by one or more bond pads and a seal ring that surrounds the cavity. The seal ring includes grooves that allow exposure of the cavity to the space within the package. A getter material applied to a top surface of the MEMS die on the upper plate. The getter material is activated during or after the lid is mounted to the bottom section.
    Type: Application
    Filed: June 16, 2008
    Publication date: December 17, 2009
    Inventors: Bryan Seppala, Jon DCamp, Max Glenn
  • Publication number: 20090051286
    Abstract: It is an object of the present invention to provide a high reliable EL display device and a manufacturing method thereof by shielding intruding moisture or oxygen which is a factor of deteriorating the property of an EL element without enlarging the EL display device. In the invention, application is used as a method for forming a high thermostability planarizing film 16, typically, an interlayer insulating film (a film which serves as a base film of a light emitting element later) of a TFT in which a skeletal structure is configured by the combination of silicon (Si) and oxygen (O). After the formation, an edge portion or an opening portion is formed to have a tapered shape. Afterwards, distortion is given by adding an inert element with a comparatively large atomic radius to modify or highly densify a surface (including a side surface) for preventing the intrusion of moisture or oxygen.
    Type: Application
    Filed: October 15, 2008
    Publication date: February 26, 2009
    Inventors: Shunpei YAMAZAKI, Masaharu NAGAI, Osamu NAKAMURA
  • Publication number: 20080272475
    Abstract: A die package (72) for a semiconductor die (20). A plurality of the die packages (72) are formed on a single carrier (10) by applying a body (55) of molding compound across a carrier (10) with an air cavity (70) defined in the molding compound about each of a plurality of device regions (12) of the carrier (10). After a semiconductor die (20) is attached inside the air cavity (70) of each device region (12) and electrically connected with at least one contact pad (14, 16, 18), a cover (68) is applied to close all of the air cavities (70). Following singulation, each semiconductor die (20) is located inside the sealed air cavity (70) of one die package (72). The molding compound of each die package (72) may be locked against movement relative to the device region (12) of the carrier (10) by locking features (30, 38, 48, 50).
    Type: Application
    Filed: October 27, 2006
    Publication date: November 6, 2008
    Applicant: NXP B.V.
    Inventors: Paul Dijkstra, Roelf Anco Jacob Groenhuis
  • Publication number: 20080191336
    Abstract: The invention discloses a subminiature electronic device with a hermetic cavity and method of manufacturing the same. It particularly relates to a chip type or chip scale packaged electronic device produced in substrate level. Firstly, a sacrificial layer is coated onto each of the identical microstructures disposed on a large substrate. A protective layer containing glass powders is then applied to encapsulate the sacrificial layer. Afterwards, the sacrificial layer is removed so as to form a cavity between the microstructure and the protective layer. The whole protective layer is then melted at elevated temperature to seal the cavity in an environment of specific gas. Finally, the large substrate is diced into a plurality of individual devices with a hermetic cavity over the microstructure. The applicable fields include micro-electronic circuits, micro-vibration systems, micro electrical-mechanical systems (MEMS), and gas discharge apparatuses.
    Type: Application
    Filed: May 24, 2007
    Publication date: August 14, 2008
    Inventor: Chon-Ming Tsai
  • Publication number: 20080185701
    Abstract: Hermetically sealed packages having organic electronic devices are presented. A number of sealing mechanisms are provided to hermetically seal the package to protect the organic electronic device from environmental elements. A metal alloy sealant layer is employed proximate to the organic electronic device. Alternatively, a metal alloy sealant layer in combination with primer layer may also be implemented. Further, superstrates and edge wraps may be provided to completely surround the organic electronic device.
    Type: Application
    Filed: April 3, 2008
    Publication date: August 7, 2008
    Inventors: Donald Franklin Foust, William Francis Nealon
  • Publication number: 20080131817
    Abstract: Provided herein are gettering members that include a monitor substrate and a conditioning layer thereon. Also provided herein are methods of forming gettering layers and methods of performing immersion lithography processes using the same.
    Type: Application
    Filed: November 13, 2007
    Publication date: June 5, 2008
    Inventors: Jin-Young Yoon, Hyun-Woo Kim, Chan Hwang, Yun-Kyeong Jang
  • Publication number: 20070273013
    Abstract: Embodiments of the present disclosure provide systems and methods for producing micro electro-mechanical device packages. Briefly described, in architecture, one embodiment of the system, among others, includes a micro electro-mechanical device formed on a substrate layer; and a thermally decomposable sacrificial structure protecting at least a portion of the micro electro-mechanical device, where the sacrificial structure is formed on the substrate layer and surrounds a gas cavity enclosing an active surface of the micro electro-mechanical device. Other systems and methods are also provided.
    Type: Application
    Filed: March 15, 2005
    Publication date: November 29, 2007
    Inventors: Paul Kohl, Farrokh Ayazi