Conductive Vias Through Substrate With Or Without Pins, E.g., Buried Coaxial Conductors (epo) Patents (Class 257/E23.174)
  • Patent number: 9030024
    Abstract: Disclosed is a semiconductor device with through-silicon vias (TSVs) that comprises a primary TSV group, a plurality of signal lines connected to the primary TSV group, a redundant TSV group and connection circuitry responsive to a control signal having a predetermined value to electrically connect the signal lines to the redundant TSV group.
    Type: Grant
    Filed: April 26, 2011
    Date of Patent: May 12, 2015
    Assignee: Conversant Intellectual Property Management Inc.
    Inventor: Jin-Ki Kim
  • Patent number: 9018767
    Abstract: A dielectric stack and method of depositing the stack to a substrate using a single step deposition process. The dielectric stack includes a dense layer and a porous layer of the same elemental compound with different compositional atomic percentage, density, and porosity. The stack enhances mechanical modulus strength and enhances oxidation and copper diffusion barrier properties. The dielectric stack has inorganic or hybrid inorganic-organic random three-dimensional covalent bonding throughout the network, which contain different regions of different chemical compositions such as a cap component adjacent to a low-k component of the same type of material but with higher porosity.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: April 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Griselda Bonilla, Alfred Grill, Thomas J. Haigh, Jr., Satyanarayana V. Nitta, Son Nguyen
  • Patent number: 9000575
    Abstract: A first substrate with a penetration electrode formed thereon is stacked on a second substrate with a protruding electrode formed thereon. The penetration electrode has a recessed portion. The substrates are stacked with the protruding electrode entered in the recessed portion. A distal width of the protruding electrode is smaller than an opening width of the recessed portion.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: April 7, 2015
    Assignee: Seiko Epson Corporation
    Inventor: Hideo Imai
  • Patent number: 8994182
    Abstract: The present disclosure relates to a dielectric solder barrier for a semiconductor die. In one embodiment, a semiconductor die includes a substrate, a semiconductor body on a first surface of the substrate, one or more first metallization layers on the semiconductor body opposite the substrate, a via that extends from a second surface of the substrate through the substrate and the semiconductor body to the one or more first metallization layers, and a second metallization layer on the second surface of the substrate and within the via. A portion of the second metallization layer within the via provides an electrical connection between the second metallization layer and the one or more first metallization layers. The semiconductor die further includes a dielectric solder barrier on the second metallization layer. Preferably, the dielectric solder barrier is on a surface of the portion of the second metallization layer within the via.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: March 31, 2015
    Assignee: Cree, Inc.
    Inventors: Helmut Hagleitner, Fabian Radulescu
  • Patent number: 8994184
    Abstract: A semiconductor device has a substrate with a plurality of conductive vias and conductive layer formed over the substrate. A semiconductor die is mounted over a carrier. The substrate is mounted to the semiconductor die opposite the carrier. An encapsulant is deposited between the substrate and carrier around the semiconductor die. A plurality of conductive TMVs is formed through the substrate and encapsulant. The conductive TMVs protrude from the encapsulant to aid with alignment of the interconnect structure. The conductive TMVs are electrically connected to the conductive layer and conductive vias. The carrier is removed and an interconnect structure is formed over a surface of the encapsulant and semiconductor die opposite the substrate. The interconnect structure is electrically connected to the conductive TMVs. A plurality of semiconductor devices can be stacked and electrically connected through the substrate, conductive TMVs, and interconnect structure.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: March 31, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventor: Reza A. Pagaila
  • Patent number: 8987868
    Abstract: Method and apparatus for programmable heterogeneous integration of stacked semiconductor die are described. In some examples, a semiconductor device includes a first integrated circuit (IC) die including through-die vias (TDVs); a second IC die vertically stacked with the first IC die, the second IC die including inter-die contacts electrically coupled to the TDVs; the first IC die including heterogeneous power supplies and a mask-programmable interconnect, the mask-programmable interconnect mask-programmed to electrically couple a plurality of the heterogeneous power supplies to the TDVs; and the second IC die including active circuitry, coupled to the inter-die contacts, configured to operate using the plurality of heterogeneous power supplies provided by the TDVs.
    Type: Grant
    Filed: February 24, 2009
    Date of Patent: March 24, 2015
    Assignee: Xilinx, Inc.
    Inventor: Arifur Rahman
  • Patent number: 8970043
    Abstract: A wafer structure includes a first wafer stack and a first bonding layer disposed on the first wafer stack. The wafer structure further includes a second wafer stack that includes a first surface and a second surface opposing the first surface. A second bonding layer is disposed on the second surface and is in contact with the first bonding layer. The second wafer stack comprises through-silicon-vias (TSVs) that extend from the first surface to the second bonding layer. A seed layer is disposed on the first surface and is in contact with the TSVs.
    Type: Grant
    Filed: February 1, 2011
    Date of Patent: March 3, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Quanbo Zou, Uppili Sridhar, Amit S. Kelkar, Xuejun Ying
  • Patent number: 8970010
    Abstract: Embodiments of a semiconductor wafer having wafer-level die attach metallization on a back-side of the semiconductor wafer, resulting semiconductor dies, and methods of manufacturing the same are disclosed. In one embodiment, a semiconductor wafer includes a semiconductor structure and a front-side metallization that includes front-side metallization elements for a number of semiconductor die areas. The semiconductor wafer also includes vias that extend from a back-side of the semiconductor structure to the front-side metallization elements. A back-side metallization is on the back-side of the semiconductor structure and within the vias. For each via, one or more barrier layers are on a portion of the back-side metallization that is within the via and around a periphery of the via. The semiconductor wafer further includes wafer-level die attach metallization on the back-side metallization other than the portions of the back-side metallization that are within the vias and around the peripheries of the vias.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 3, 2015
    Assignee: Cree, Inc.
    Inventors: Fabian Radulescu, Helmut Hagleitner, Terry Alcorn, William T. Pulz
  • Patent number: 8957504
    Abstract: An integrated structure with a silicon-through via includes a substrate, a through-silicon via penetrating the substrate, a conductive protective structure surrounding the through-silicon via and a first and a second conductive dummy patterns with different shapes disposed between the through-silicon via and the conductive protective structure.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 17, 2015
    Assignee: IP Enval Consultant Inc.
    Inventors: Huang Chao-Yuan, Ho Yueh-Feng, Yang Ming-Sheng, Chen Hwi-Huang
  • Patent number: 8952499
    Abstract: An integrated circuit is provided with a substrate, an electrode, two diffusion areas, and a resistance heater. The substrate includes a first surface and second surface that are substantially parallel to each other. The electrode is laminated onto the first surface. The two diffusion areas are disposed within the substrate in the vicinity of the electrode to form one transistor with the electrode. The resistance heater is located on an area of the second surface across the substrate from the electrode. The resistance heater produces heat by allowing electric current to flow.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: February 10, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Takashi Morimoto, Takashi Hashimoto
  • Patent number: 8927410
    Abstract: A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. A liquid dielectric is applied to line at least an elevationally outermost portion of sidewalls of the via relative a side of the substrate from which the via was initially formed. The liquid dielectric is solidified within the via. Conductive material is formed within the via over the solidified dielectric and a through substrate interconnect is formed with the conductive material.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: January 6, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Dave Pratt, Andy Perkins
  • Patent number: 8928128
    Abstract: There are disclosed herein various implementations of a shield interposer situated between a top active die and a bottom active die for shielding the active dies from electromagnetic noise. One implementation includes an interposer dielectric layer, a through-silicon via (TSV) within the interposer dielectric layer, and an electromagnetic shield. The TSV connects the electromagnetic shield to a first fixed potential. The electromagnetic shield may include a grid of conductive layers laterally extending across the shield interposer. The shield interposer may also include another electromagnetic shield connected to another fixed potential.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: January 6, 2015
    Assignee: Broadcom Corporation
    Inventors: Sampath K. V. Karikalan, Kevin Kunzhong Hu, Sam Ziqun Zhao, Rezaur Rahman Khan, Pieter Vorenkamp, Xiangdong Chen
  • Patent number: 8927427
    Abstract: A method including introducing a dopant into a region of a substrate, etching a deep trench in the substrate through the region, gettering impurities introduced during etching of the deep trench using a pentavalent ion formed from a reaction between an element of the substrate and the dopant, wherein the charge of the pentavalent ion attracts the impurities, and filling the deep trench with a conductive material.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Troy L. Graves-Abe, Brian J. Greene, Chandrasekharan Kothandaraman
  • Patent number: 8921995
    Abstract: An integrated circuit (IC) package is disclosed comprising a substrate including a plurality of substrate contacts; a semiconductor die including a plurality of die contacts; and a plurality of conductors for providing direct connections between substrate contacts and die contacts, respectively. By having the conductors directly route the connections between the die contacts and substrate contacts, many improvements may be realized including, but not limited to, improved package routing capabilities, reduced die and/or package size, improved package reliability, improved current handling capacity, improved speed, improved thermal performance, and lower costs.
    Type: Grant
    Filed: July 15, 2011
    Date of Patent: December 30, 2014
    Assignee: Maxim Intergrated Products, Inc.
    Inventors: Tarak A. Railkar, Steven D. Cate
  • Patent number: 8896116
    Abstract: A microelectronic package includes a substrate (110), a die (120) embedded within the substrate, the die having a front side (121) and a back side (122) and a through-silicon-via (123) therein, build-up layers (130) built up over the front side of the die, and a power plane (140) in physical contact with the back side of the die. In another embodiment, the microelectronic package comprises a substrate (210), a first die (220) and a second die (260) embedded in the substrate and having a front side (221, 261) and a back side (222, 262) and a through-silicon-via (223, 263) therein, build-up layers (230) over the front sides of the first and second dies, and an electrically conductive structure (240) in physical contact with the back sides of the first and second dies.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: November 25, 2014
    Assignee: Intel Corporation
    Inventors: Ravi K. Nalla, Mathew J. Manusharow, Drew W. Delaney
  • Patent number: 8890329
    Abstract: A semiconductor device entirely having a small height, which performs a fan-out operation for input/output signals and forms a short electrical path is provided. The semiconductor device includes a first semiconductor die having a first surface, a second surface opposed to the first surface, a third surface connecting the first and second surfaces to each other, a first bond pad disposed on the first surface, and a first through electrode passing between the first surface and second surface and electrically connected to the first bond pad. A first redistribution part is disposed under the second surface and includes a first redistribution layer electrically connected to the first through electrode. A second redistribution part is disposed over the first surface and includes a second redistribution layer electrically connected to the first bond pad.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: November 18, 2014
    Inventors: Do Hyung Kim, Dae Byoung Kang, Seung Chul Han
  • Patent number: 8889483
    Abstract: A method of manufacturing a semiconductor device in one exemplary embodiment includes preparing a first substrate and a second substrate, the first substrate including a bump electrode group formed of bump electrodes arrayed with a certain pitch, the number of bump electrodes along a first direction being larger than the number of bump electrodes along a second direction perpendicular to the first direction; joining the first substrate and the second substrate to each other through the bump electrodes so that a gap is formed between the first substrate and the second substrate; and filling the gap with a mold resin by causing the mold resin to flow in the gap from an edge of the first substrate along the second direction of the bump electrode group.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: November 18, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Masahito Yamato
  • Patent number: 8890607
    Abstract: A stacked chip system is provided to comprise a first chip, a second chip, a first group of through silicon vias (TSVs) connecting the first chip and second chip and comprising at least one first VSS TSV, at least one first VDD TSV, a plurality of first signal TSVs and at least one first redundant TSV and a second group of through silicon vias (TSVs) connecting the first chip and second chip and comprising at least one second VSS TSV, at least one second VDD TSV, a plurality of second signal TSVs and at least one second redundant TSV, wherein all the first group of TSVs are coupled by a first selection circuitry configured to select the at least one first redundant TSV and bypass at least one of the rest of the first group of TSVs, and wherein the at least one first redundant TSV and the at least second redundant TSV are coupled by a second selection circuitry configured to allow one of them to replace the other.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 18, 2014
    Assignee: IPEnval Consultant Inc.
    Inventors: Chao-Yuan Huang, Yueh-Feng Ho, Ming-Sheng Yang, Hwi-Huang Chen
  • Patent number: 8884437
    Abstract: A device with contact elements. One embodiment provides an electrical device including a structure defining a main face. The structure includes an array of cavities and an array of overhang regions, each overhang region defining an opening to one of the cavities. The electrical device further includes an array of contact elements, each contact element only partially filling one of the cavities and protruding from the structure over the main face.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: November 11, 2014
    Assignee: Infineon Technologies AG
    Inventors: Klaus-Guenter Oppermann, Martin Franosch
  • Patent number: 8884440
    Abstract: An integrated circuit device includes a substrate through which a first through-hole extends, and an interlayer insulating film on the substrate, the interlayer insulating film having a second through-hole communicating with the first through-hole. A Through-Silicon Via (TSV) structure is provided in the first through-hole and the second through-hole. The TSV structure extends to pass through the substrate and the interlayer insulating film. The TSV structure comprises a first through-electrode portion having a top surface located in the first through-hole, and a second through-electrode portion having a bottom surface contacting with the top surface of the first through-electrode portion and extending from the bottom surface to at least the second through-hole. Related fabrication methods are also described.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: November 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Su-kyoung Kim, Gil-heyun Choi, Byung-lyul Park, Kwang-jin Moon, Kun-sang Park, Dong-chan Lim, Do-sun Lee
  • Patent number: 8878229
    Abstract: Disclosed is a light emitting device package. The light emitting device package includes a substrate including a recess, a light emitting chip on the substrate and a first conductive layer electrically connected to the light emitting chip. And the first conductive layer includes at least one metal layer electrically connected to the light emitting chip on an outer circumference of the substrate.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: November 4, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventors: Guen-Ho Kim, Yu Ho Won
  • Patent number: 8878367
    Abstract: A substrate structure with through vias is provided. The substrate structure with through vias includes a semiconductor substrate having a back surface and a via penetrating the back surface, a metal layer, a first insulating layer and a second insulating layer. The first insulating layer is formed on the back surface of the semiconductor substrate and has an opening connected to the through via. The second insulating layer is formed on the first insulating layer and has a portion extending into the opening and the via to form a trench insulating layer. The bottom of the trench insulating layer is etched back to form a footing portion at the corner of the via. The footing portion has a height less than a total height of the first and second insulating layers.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: November 4, 2014
    Assignee: Xintec Inc.
    Inventors: Chia-Sheng Lin, Chien-Hui Chen, Bing-Siang Chen, Tzu-Hsiang Hung
  • Patent number: 8872354
    Abstract: A method of forming through silicon vias (TSVs) uses a low-k dielectric material as a via insulating layer to thereby improve step coverage and minimize resistive capacitive (RC) delay. To this end, the method includes forming a primary via hole in a semiconductor substrate, depositing low-k dielectric material in the primary via hole, forming a secondary via hole by etching the low-k dielectric in the primary via hole, in such a manner that a via insulating layer and an inter metal dielectric layer of the low-k dielectric layer are simultaneously formed. The via insulating layer is formed of the low-k dielectric material on sidewalls and a bottom surface of the substrate which delimit the primary via hole and the inter metal dielectric layer is formed on an upper surface of the substrate. Then a metal layer is formed on the substrate including in the secondary via hole, and the metal layer is selectively removed from an upper surface of the semiconductor substrate.
    Type: Grant
    Filed: March 26, 2013
    Date of Patent: October 28, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han Kyu-hee, Sang-hoon Ahn, Jang-hee Lee, Jong-min Beak, Kyoung-hee Kim, Byung-lyul Park, Byung-hee Kim
  • Patent number: 8866303
    Abstract: Disclosed is a semiconductor device that comprises a plurality of through-silicon vias (TSVs), a signal line and a selective connector for causing the signal line to be either electrically connected to one of the TSVs or electrically isolated from all of the TSVs, based on a control signal.
    Type: Grant
    Filed: April 26, 2011
    Date of Patent: October 21, 2014
    Assignee: Conversant Intellectual Property Management Inc.
    Inventor: Jin-Ki Kim
  • Patent number: 8866301
    Abstract: A package system includes a first integrated circuit disposed over an interposer. The interposer includes at least one molding compound layer including a plurality of electrical connection structures through the at least one molding compound layer. A first interconnect structure is disposed over a first surface of the at least one molding compound layer and electrically coupled with the plurality of electrical connection structures. The first integrated circuit is electrically coupled with the first interconnect structure.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: October 21, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Lin, Jing-Cheng Lin, Chen-Hua Yu
  • Patent number: 8860230
    Abstract: In one embodiment, a semiconductor is provided comprising a substrate and a plurality of wiring layers and dielectric layers formed on the substrate, the wiring layers implementing a circuit. The dielectric layers separate adjacent ones of the plurality of wiring layers. A first passivation layer is formed on the plurality of wiring layers. A first contact pad is formed in the passivation layer and electrically coupled to the circuit. A wire is formed on the passivation layer and connected to the contact pad. A through silicon via (TSV) is formed through the substrate, the plurality of wiring and dielectric layers, and the passivation layer. The TSV is electrically connected to the wire formed on the passivation layer. The TSV is electrically isolated from the wiring layers except for the connection provided by the metal wire formed on the passivation layer.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: October 14, 2014
    Assignee: NXP B.V.
    Inventors: Florian Schmitt, Michael Ziesmann
  • Patent number: 8860188
    Abstract: A semiconductor device is disclosed allowing detection of a connection state of a Through Silicon Via (TSV) at a wafer level. The semiconductor device includes a first line formed over a Through Silicon Via (TSV), a second line formed over the first line, and a first power line and a second power line formed over the same layer as the second line. Therefore, the semiconductor device can screen not only a chip-to-chip connection state after packaging completion, but also a connection state between the TSV and the chip at a wafer level, so that unnecessary costs and time encountered in packaging of a defective chip are reduced.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: October 14, 2014
    Assignee: SK Hynix Inc.
    Inventor: Take Kyun Woo
  • Patent number: 8847360
    Abstract: An electrostatic discharge (ESD) protection device is fabricated in a vertical space between active layers of stacked semiconductor dies thereby utilizing space that would otherwise be used only for communication purposes. The vertical surface area of the through silicon vias (TSVs) is used for absorbing large voltages resulting from ESD events. In one embodiment, an ESD diode is created in a vertical TSV between active layers of the semiconductor dies of a stacked device. This ESD diode can be shared by circuitry on both semiconductor dies of the stack thereby saving space and reducing die area required by ESD protection circuitry.
    Type: Grant
    Filed: November 17, 2011
    Date of Patent: September 30, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Kenneth Kaskoun, Shiqun Gu, Matthew Nowak
  • Patent number: 8846526
    Abstract: A substrate (3) in which a through-hole (2) is filled with a filler (4) is prepared, and a structure (6), at least a part of the surface of which has an insulating property, is formed on the surface of the substrate (3). A plated layer (7) is formed on the substrate (3) having the structure (6) formed thereon, and the filler (4) and the structure (6) are removed. Thus, a through-hole substrate (8) is formed, in which the plated layer (7) having an opening (9) communicating with the through-hole (2) is provided on at least one surface of a substrate (1).
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: September 30, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takayuki Teshima
  • Patent number: 8841773
    Abstract: A multi-layer interconnect structure for stacked die configurations is provided. Through-substrate vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-substrate vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-substrate vias. A first conductive element is formed electrically coupled to respective ones of the through-substrate vias and extending over the isolation film. One or more additional layers of isolation films and conductive elements may be formed, with connection elements such as solder balls being electrically coupled to the uppermost conductive elements.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: September 23, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Pin Chang, Chien-Ming Chiu, Tsang-Jiuh Wu, Shau-Lin Shue, Chen-Hua Yu
  • Patent number: 8841755
    Abstract: The present invention relates to a through silicon via (TSV). The TSV is disposed in a substrate including a via opening penetrating through a first surface and a second surface of the substrate. The TSV includes an insulation layer, a barrier layer, a buffer layer and a conductive electrode. The insulation layer is disposed on a surface of the via opening. The barrier layer is disposed on a surface of the insulation layer. The buffer layer is disposed on a surface of the barrier layer. The conductive electrode is disposed on a surface of the buffer layer and a remainder of the via opening is completely filled with the conductive electrode. A portion of the buffer layer further covers a surface of the conductive electrode at a side of the second surface and said portion is level with the second surface.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: September 23, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Kuo-Hsiung Huang, Chun-Mao Chiou, Hsin-Yu Chen, Yu-Han Tsai, Ching-Li Yang, Home-Been Cheng
  • Patent number: 8836135
    Abstract: A semiconductor device including: a semiconductor substrate; a plurality of interconnect layers disposed at different heights from the semiconductor substrate, each interconnect layer including an interconnection formed therein; and a via formed in a columnar shape extending in the stack direction of the interconnect layers, the via electrically connecting the interconnections of the different interconnect layers, the interconnections including an intermediate interconnection in contact with the via in the intermediate portion thereof, and the intermediate interconnection including a first type intermediate interconnection passing through the via in a direction perpendicular to the stack direction and in contact with the via on the top surface, bottom surface, and both side surfaces thereof.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: September 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hirokazu Kikuchi
  • Patent number: 8829654
    Abstract: The present application discloses various implementations of a semiconductor package including an organic substrate and one or more interposers having through-semiconductor vias (TSVs). Such a semiconductor package may include a contiguous organic substrate having a lower substrate segment including first and second pluralities of lower interconnect pads, the second plurality of lower interconnect pads being disposed in an opening of the lower substrate segment. The contiguous organic substrate may also include an upper substrate segment having an upper width and including first and second pluralities of upper interconnect pads. In addition, the semiconductor package may include at least one interposer having TSVs for electrically connecting the first and second pluralities of lower interconnect pads to the first and second pluralities of upper interconnect pads. The interposer has an interposer width less than the upper width of the upper substrate segment.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: September 9, 2014
    Assignee: Broadcom Corporation
    Inventors: Sam Ziqun Zhao, Rezaur Rahman Khan
  • Patent number: 8829687
    Abstract: A semiconductor package is provided, which includes: a semiconductor substrate having opposite first and second surfaces; an adhesive layer formed on the first surface of the semiconductor substrate; at least a semiconductor chip disposed on the adhesive layer; an encapsulant formed on the adhesive layer for encapsulating the semiconductor chip; and a plurality of conductive posts penetrating the first and second surfaces of the semiconductor substrate and the adhesive layer and electrically connected to the semiconductor chip, thereby effectively reducing the fabrication cost, shortening the fabrication time and improving the product reliability.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: September 9, 2014
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Mu-Hsuan Chan, Wan-Ting Chen, Yi-Chian Liao, Chun-Tang Lin, Yi-Chi Lai
  • Patent number: 8829656
    Abstract: The present application discloses various implementations of a semiconductor package including an organic substrate and one or more interposers having through-semiconductor vias (TSVs). Such a semiconductor package may include a contiguous organic substrate having a lower substrate segment including first and second pluralities of lower interconnect pads, the second plurality of lower interconnect pads being disposed in an opening of the lower substrate segment. The contiguous organic substrate may also include an upper substrate segment having an upper width and including first and second pluralities of upper interconnect pads. In addition, the semiconductor package may include at least one interposer having TSVs for electrically connecting the first and second pluralities of lower interconnect pads to the first and second pluralities of upper interconnect pads. The interposer has an interposer width less than the upper width of the upper substrate segment.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: September 9, 2014
    Assignee: Broadcom Corporation
    Inventors: Sam Ziqun Zhao, Rezaur Rahman Khan
  • Patent number: 8829655
    Abstract: The present application discloses various implementations of a semiconductor package including an organic substrate and one or more interposers having through-semiconductor vias (TSVs). Such a semiconductor package may include a contiguous organic substrate having a lower substrate segment including first and second pluralities of lower interconnect pads, the second plurality of lower interconnect pads being disposed in an opening of the lower substrate segment. The contiguous organic substrate may also include an upper substrate segment having an upper width and including first and second pluralities of upper interconnect pads. In addition, the semiconductor package may include at least one interposer having TSVs for electrically connecting the first and second pluralities of lower interconnect pads to the first and second pluralities of upper interconnect pads. The interposer has an interposer width less than the upper width of the upper substrate segment.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: September 9, 2014
    Assignee: Broadcom Corporation
    Inventors: Sam Ziqun Zhao, Rezaur Rahman Khan
  • Patent number: 8823144
    Abstract: An interface substrate is disclosed which includes an interposer having through-semiconductor vias. An upper and a lower organic substrate are further built around the interposer. The disclosed interface substrate enables the continued use of low cost and widely deployed organic substrates for semiconductor packages while providing several advantages. The separation of the organic substrate into upper and lower substrates enables the cost effective matching of fabrication equipment. By providing an opening in one of the organic substrates, one or more semiconductor dies may be attached to exposed interconnect pads coupled to through-semiconductor vias of the interposer, enabling the use of flip chips with high-density microbump arrays and the accommodation of dies with varied bump pitches. By providing the opening specifically in the upper organic substrate, a package-on-package structure with optimized height may also be provided.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: September 2, 2014
    Assignee: Broadcom Corporation
    Inventors: Rezaur Rahman Khan, Sam Ziqun Zhao
  • Patent number: 8823090
    Abstract: A field-effect transistor has a gate, a source, and a drain. The gate has a via extending through a semiconductor chip substrate from one surface to an opposite surface of the semiconductor chip substrate. The source has a first toroid of ion dopants implanted in the semiconductor chip substrate surrounding one end of the via on the one surface of the semiconductor chip substrate. The drain has a second toroid of ion dopants implanted in the semiconductor chip substrate surrounding an opposite end of the via on the opposite surface of the semiconductor chip substrate.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: September 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Gerald K Bartley, Darryl J Becker, Philip R Germann, Andrew B Maki, John E Sheets, II
  • Patent number: 8816505
    Abstract: A component can include a substrate having a front surface and a rear surface remote therefrom, an opening extending from the rear surface towards the front surface, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The opening can define an inner surface between the front and rear surfaces. The conductive via can include a first metal layer overlying the inner surface and a second metal region overlying the first metal layer and electrically coupled to the first metal layer. The second metal region can have a CTE greater than a CTE of the first metal layer. The conductive via can have an effective CTE across a diameter of the conductive via that is less than 80% of the CTE of the second metal region.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: August 26, 2014
    Assignee: Tessera, Inc.
    Inventors: Ilyas Mohammed, Belgacem Haba, Cyprian Uzoh
  • Patent number: 8816490
    Abstract: An integrated circuit die stack including a first integrated circuit die mounted upon a substrate, the first die including pass-through vias (‘PTVs’) composed of conductive pathways through the first die with no connection to any circuitry on the first die; and a second integrated circuit die, identical to the first die, rotated with respect to the first die and mounted upon the first die, with the PTVs in the first die connecting signal lines from the substrate through the first die to through silicon vias (‘TSVs’) in the second die composed of conductive pathways through the second die connected to electronic circuitry on the second die; with the TSVs and PTVs disposed upon each identical die so that the positions of the TSVs and PTVs on each identical die are rotationally symmetrical with respect to the TSVs and PTVs on the other identical die.
    Type: Grant
    Filed: March 20, 2013
    Date of Patent: August 26, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jimmy G. Foster, Sr., Kyu-Hyoun Kim
  • Patent number: 8810038
    Abstract: A semiconductor device includes: a board; a power wire formed on the board; a signal wire formed on the board; a ground wire formed on the board; an insulating layer covering the signal wire, the power wire and the ground wire; and a metal film formed on the insulating layer, wherein a thickness of the insulating layer covering the power wire is different from a thickness of the insulating layer covering the signal wire, and the metal film is connected to a ground potential.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: August 19, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Takafumi Shimada, Atsushi Kikuchi
  • Patent number: 8810006
    Abstract: A system and method for providing an interposer is provided. An embodiment comprises forming a first region and a second region on an interposer wafer with a scribe region between the first region and the second region. The first region and the second region are then connected to each other through circuitry located over the scribe region. In another embodiment, the first region and the second region may be separated from each other and then encapsulated together prior to the first region being connected to the second region.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: August 19, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Shin-Puu Jeng, Shang-Yun Hou, Der-Chyang Yeh
  • Patent number: 8803332
    Abstract: An integrated circuit structure includes a first die including TSVs; a second die over and bonded to the first die, with the first die having a surface facing the second die; and a molding compound including a portion over the first die and the second die. The molding compound contacts the surface of the second die. Further, the molding compound includes a portion extending below the surface of the second die.
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: August 12, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-I Lee, Tsung-Ding Wang
  • Patent number: 8803269
    Abstract: A wafer scale implementation of an opto-electronic transceiver assembly process utilizes a silicon wafer as an optical reference plane and platform upon which all necessary optical and electronic components are simultaneously assembled for a plurality of separate transceiver modules. In particular, a silicon wafer is utilized as a “platform” (interposer) upon which all of the components for a multiple number of transceiver modules are mounted or integrated, with the top surface of the silicon interposer used as a reference plane for defining the optical signal path between separate optical components. Indeed, by using a single silicon wafer as the platform for a large number of separate transceiver modules, one is able to use a wafer scale assembly process, as well as optical alignment and testing of these modules.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: August 12, 2014
    Assignee: Cisco Technology, Inc.
    Inventors: Kalpendu Shastri, Vipulkumar Patel, Mark Webster, Prakash Gothoskar, Ravinder Kachru, Soham Pathak, Rao V. Yelamarty, Thomas Daugherty, Bipin Dama, Kaushik Patel, Kishor Desai
  • Patent number: 8791575
    Abstract: A microelectronic unit, an interconnection substrate, and a method of fabricating a microelectronic unit are disclosed. A microelectronic unit can include a semiconductor element having a plurality of active semiconductor devices therein, the semiconductor element having a first opening extending from a rear surface partially through the semiconductor element towards a front surface and at least one second opening, and a dielectric region overlying a surface of the semiconductor element in the first opening. The microelectronic unit can include at least one conductive interconnect electrically connected to a respective conductive via and extending away therefrom within the aperture. In a particular embodiment, at least one conductive interconnect can extend within the first opening and at least one second opening, the conductive interconnect being electrically connected with a conductive pad having a top surface exposed at the front surface of the semiconductor element.
    Type: Grant
    Filed: July 23, 2010
    Date of Patent: July 29, 2014
    Assignee: Tessera, Inc.
    Inventors: Vage Oganesian, Ilyas Mohammed, Craig Mitchell, Belgacem Haba, Piyush Savalia
  • Patent number: 8791578
    Abstract: This invention discloses a through-silicon via (TSV) structure for providing an electrical path between a first-side surface and a second-side surface of a silicon chip, and a method for fabricating the structure. In one embodiment, the TSV structure comprises a via penetrated through the chip from the first-side surface to the second-side surface, providing a first end on the first-side surface and a second end on the second-side surface. A local isolation layer is deposited on the via's sidewall and on a portion of the first-side surface surrounding the first end. The TSV structure further comprises a plurality of substantially closely-packed microstructures arranged to form a substantially non-random pattern and fabricated on at least the portion of the first-side surface covered by the local isolation layer for promoting adhesion of the local isolation layer to the chip. A majority of the microstructures has a depth of at least 1 ?m.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: July 29, 2014
    Assignee: Hong Kong Applied Science and Technology Research Institute Company Limited
    Inventors: Pui Chung Simon Law, Bin Xie, Dan Yang
  • Patent number: 8791015
    Abstract: A semiconductor wafer contains a plurality of semiconductor die separated by a non-active area of the semiconductor wafer. A plurality of contact pads is formed on an active surface of the semiconductor die. A first insulating layer is formed over the semiconductor wafer. A portion of the first insulating layer is removed to expose the contact pads on the semiconductor die. An opening is formed partially through the semiconductor wafer in the active surface of the semiconductor die or in the non-active area of the semiconductor wafer. A second insulating layer is formed in the opening in the semiconductor wafer. A shielding layer is formed over the active surface. The shielding layer extends into the opening of the semiconductor wafer to form a conductive via. A portion of a back surface of the semiconductor wafer is removed to singulate the semiconductor die.
    Type: Grant
    Filed: April 30, 2011
    Date of Patent: July 29, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventor: Reza A. Pagaila
  • Patent number: 8786099
    Abstract: A wiring substrate includes: a substrate body made of an inorganic material; a first electrode portion, having a rectangular plane shape, which penetrates through the substrate body in a thickness direction of the substrate body; a second electrode portion, having a rectangular plane shape, which penetrates through the substrate body in the thickness direction and faces the first electrode portion at a prescribed interval; and a signal electrode, which is provided between the first electrode portion and the second electrode portion and penetrates through the substrate body in the thickness direction, wherein one of the first electrode portion and the second electrode portion is a ground electrode and the other is a power electrode.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: July 22, 2014
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Tomoharu Fujii
  • Patent number: 8786102
    Abstract: A semiconductor device includes a first wiring board, a second semiconductor chip, and a second seal. The first wiring board includes a first substrate, a first semiconductor chip, and a first seal. The first semiconductor chip is disposed on the first substrate. The first seal is disposed on the first substrate. The first seal surrounds the first semiconductor chip. The first seal has the same thickness as the first semiconductor chip. The second semiconductor chip is stacked over the first semiconductor chip. The first semiconductor chip is between the second semiconductor chip and the first substrate. The second semiconductor chip is greater in size in plan view than the first semiconductor chip. The second seal seals at least a first gap between the first semiconductor chip and the second semiconductor chip.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: July 22, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventors: Masanori Yoshida, Fumitomo Watanabe
  • Patent number: 8786103
    Abstract: A first semiconductor component and a second semiconductor component are attached together via an adhesion layer so that the first semiconductor component and the second semiconductor component are electrically connected with each other via a through electrode. The through electrode is formed to fill a through hole formed in the second semiconductor component and a through hole formed in a portion the adhesion layer. The through hole formed in the portion the adhesion layer is positioned between the through hole formed in the second semiconductor component and a second connection surface of a first semiconductor component through electrode.
    Type: Grant
    Filed: April 7, 2010
    Date of Patent: July 22, 2014
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Kenta Uchiyama, Akihiko Tateiwa