Abstract: Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a backside, an interconnect extending through the first die to the backside, an integrated circuit electrically coupled to the interconnect, and a first electrostatic discharge (ESD) device electrically isolated from the interconnect. A second microelectronic die has a front side coupled to the backside of the first die, a metal contact at the front side electrically coupled to the interconnect, and a second ESD device electrically coupled to the metal contact. In another embodiment, the first die further includes a substrate carrying the integrated circuit and the first ESD device, and the interconnect is positioned in the substrate to disable an electrical connection between the first ESD device and the interconnect.

Abstract: A semiconductor device comprising a semiconductor die that is embedded in a package, wherein the die has a front side comprising a plurality of pads to be bonded to terminals of the package, and wherein a backside of the die is coupled to a backside surface of the package by a thermal bridge.

Abstract: A semiconductor package-on-package (PoP) device includes a first die incorporating a through-hole via (THV) disposed along a peripheral surface of the first die. The first die is disposed over a substrate or leadframe structure. A first semiconductor package is electrically connected to the THV of the first die, or electrically connected to the substrate or leadframe structure. An encapsulant is formed over a portion of the first die and the first semiconductor package.

Abstract: A three dimensional semiconductor device includes a first die; and a second die overlaying the first die, wherein said first die comprises signals are selectively coupleable to the second die using Through Silicon Vias.

Abstract: A stacked structure of chips including a first chip and a second chip is provided. The first chip includes a first and a second circuit blocks, a signal path, a first and a second hardwired switches. The second chip stacks with the first chip stack and includes a third circuit block, a third and a fourth hardwired switches. If the first circuit block is defective and the second and the third circuit blocks are functional, the first hardwired switch and the third hardwired switch are set correspondingly such that a power-supply bonding pad is connected to the third power terminal and disconnected to the first power terminal, and the second hardwired switch and the fourth hardwired switch are set correspondingly such that the third signal terminal is electrically connected to the signal path to make the third circuit block replace the first circuit block and provide the first function.

Abstract: A semiconductor chip includes: a semiconductor substrate; an interface member formed through the semiconductor substrate and electrically coupled to an external signal transfer terminal; and a backward diode formed between the semiconductor substrate and the interface member.

Abstract: A wiring structure of a semiconductor device, includes: an insulating layer formed on a base member; a first metal layer covered with the insulating layer; a second metal layer having a plurality of electrode parts which are arranged on the insulating layer to be spaced from each other and which have a thickness larger than the first metal layer, the insulating layer having a plurality of via holes which connect the first metal layer and the plurality of electrode parts; and a plurality of through wiring lines which are located within the plurality of via holes and which electrically connect the plurality of electrode parts to the first metal layer.

Abstract: A wafer includes a group of tiles of programmable logic formed thereon, wherein each tile comprises a micro control unit (MCU) communicating with adjacent MCUs, and wherein each MCU is controlled in a predetermined order of priority by adjacent MCUs; and dice lines on the wafer to separate the group into one or more end-devices.

Abstract: A semiconductor device has a first semiconductor die including TSVs mounted to a carrier with a thermally releasable layer. A first encapsulant having a first coefficient of thermal expansion CTE is deposited over the first semiconductor die. The first encapsulant includes an elevated portion in a periphery of the first encapsulant that reduces warpage. A surface of the TSVs is exposed. A second semiconductor die is mounted to the surface of the TSVs and forms a gap between the first and second semiconductor die. A second encapsulant having a second CTE is deposited over the first and second semiconductor die and within the gap. The first CTE is greater than the second CTE. In one embodiment, the first and second encapsulants are formed in a chase mold. An interconnect structure is formed over the first and second semiconductor die.

Abstract: A device includes: a first substrate including a plurality of first electrodes; a plurality of chips each including a plurality of through electrodes, the chips being stacked with each other such that the through electrodes of a lower one of the chips are connected respectively the through electrodes of an upper one of the chips to provide a chip stacked body; and a second substrate cooperating the first substrate to sandwich the chip stacked body between the first and second substrates, the second substrate including a plurality of second electrodes on a first surface that is opposite to a second surface facing the chip stacked body, each of the second electrodes being electrically connected to an associated one of the through electrodes of an uppermost one of the chips of the chip stacked body.

Abstract: A semiconductor chip includes a through-silicon via (TSV), a device region, and a cross-talk prevention ring encircling one of the device region and the TSV. The TSV is isolated from substantially all device regions comprising active devices by the cross-talk prevention ring.

Abstract: Provided are a photosensitive adhesive composition having an alkali soluble epoxy resin and a patternable adhesive film using the same. The photosensitive adhesive composition has good pattern formability and adhesiveness since the photosensitive adhesive composition includes the alkali soluble epoxy resin.

Abstract: A semiconductor device is made with a conductive via formed through a top-side of the substrate. The conductive via extends vertically through less than a thickness of the substrate. An integrated passive device (IPD) is formed over the substrate. A plurality of first conductive pillars is formed over the first IPD. A first semiconductor die is mounted over the substrate. An encapsulant is formed around the first conductive pillars and first semiconductor die. A second IPD is formed over the encapsulant. An interconnect structure is formed over the second IPD. The interconnect structure operates as a heat sink. A portion of a back-side of the substrate is removed to expose the first conductive via. A second semiconductor die is mounted to the back-side of the substrate. The second semiconductor die is electrically connected to the first IPD and first semiconductor die through the conductive via.

Abstract: In one embodiment, a method is presented for formation of a through-silicon via in a silicon substrate. A via is etched in the silicon substrate. A first layer of oxide film is deposited on side walls of the via and on a first surface of the silicon substrate. At least a portion of the first layer of oxide film formed on the first surface of the silicon substrate is etched, and a second layer of oxide film is deposited on side walls of the via and. A conductor is deposited in the via.

Abstract: A process for manufacturing semiconductor packages is provided, that includes drilling blind apertures in a reconstituted wafer, adhering a dry film resist on the wafer over the apertures, and patterning the film to expose a space around each of the apertures. The apertures and spaces are then filled with conductive paste by wiping a quantity of the paste across a surface of the film so that paste is forced into the spaces and apertures. The spaces around the apertures define contact pads whose thickness is constrained by the thickness of the film, preferably to about 10 ?m or less. To prevent paste from trapping air pockets in the apertures, the wiping process can be performed in a chamber from which much or all of the air has been evacuated. After curing the paste, the wafer is thinned from the back to expose the cured paste in the apertures.

Abstract: In a semiconductor device in which the semiconductor chip including the external terminal(s) is embedded in an insulating layer and interconnect conductor(s) is (are) formed on the insulating layer, base hole(s) is (are) formed at position(s) of the insulating layer corresponding to the external terminal(s) in a state where the semiconductor chip has shrunk after having been embedded in the insulating layer. The interconnect conductor(s) is (are) electrically connected to the external terminal(s) through the base hole(s).

Abstract: A microelectronic assembly includes a dielectric element having at least one aperture and electrically conductive elements thereon including terminals exposed at the second surface of the dielectric element; a first microelectronic element having a rear surface and a front surface facing the dielectric element, the first microelectronic element having a plurality of contacts exposed at the front surface thereof; a second microelectronic element having a rear surface and a front surface facing the rear surface of the first microelectronic element, the second microelectronic element having a plurality of contacts exposed at the front surface and projecting beyond an edge of the first microelectronic element; and an electrically conductive plane attached to the dielectric element and at least partially positioned between the first and second apertures, the electrically conductive plane being electrically connected with one or more of the contacts of at least one of the first or second microelectronic elements.

Abstract: A semiconductor device is made by forming a first active device on a first side of a semiconductor wafer. A first insulating layer is formed over the first side of the wafer. A first conductive layer is formed over the first insulating layer. A first interconnect structure is formed over the first insulating layer and first conductive layer. A temporary carrier is mounted to the first interconnect structure. A second active device is formed on a second side of the semiconductor wafer. A second insulating layer is formed over the second side of the wafer. A second conductive layer is formed over the second insulating layer. A second interconnect structure is formed over the second insulating layer and second conductive layer. The temporary carrier is removed, leaving a double-sided semiconductor device. The double-sided semiconductor device is enclosed in a package with the first and second interconnect structures electrically connected.

Abstract: An integrated circuit coupling device includes an integrated circuit package with N integrated circuit layers (L1-LN) arranged as a 3D stack; and a data transmission medium with n data transmission layers (l1-ln), wherein n?1 and N?2, and wherein the N integrated circuit layers are electrically connectable to the n data transmission layers.

Abstract: In a BEOL process, UV radiation is used in a curing process of ultra low-k (ULK) dielectrics. This radiation penetrates through the ULK material and reaches the cap film underneath it. The interaction between the UV light and the film leads to a change the properties of the cap film. Of particular concern is the change in the stress state of the cap from compressive to tensile stress. This leads to a weaker dielectric-cap interface and mechanical failure of the ULK film. A layer of nanoparticles is inserted between the cap and the ULK film. The nanoparticles absorb the UV light before it can damage the cap film, thus maintaining the mechanical integrity of the ULK dielectric.

Abstract: A semiconductor chip includes a semiconductor chip body, a through-silicon via and a silicon pattern. The semiconductor chip body has a first surface and a second surface facing away from the first surface. The through-silicon via is formed to pass through the semiconductor chip body and has a metal layer and an insulation layer which protrude from the second surface. The silicon pattern is formed on a sidewall of the protruding through-silicon via.

Abstract: A microelectronic unit 400 can include a semiconductor element 401 having a front surface, a microelectronic semiconductor device adjacent to the front surface, contacts 403 at the front surface and a rear surface remote from the front surface. The semiconductor element 401 can have through holes 410 extending from the rear surface through the semiconductor element 401 and through the contacts 403. A dielectric layer 411 can line the through holes 410. A conductive layer 412 may overlie the dielectric layer 411 within the through holes 410. The conductive layer 412 can conductively interconnect the contacts 403 with unit contacts.

Abstract: A method of fabricating a semiconductor device, a process of fabricating a through substrate via and a substrate with through vias are provided. The substrate with through vias includes a semiconductor substrate having a back surface and a via penetrating the back surface, a metal layer, a first insulating layer and a second insulating layer. The first insulating layer is formed on the back surface of the substrate and has an opening connected to the through via. The second insulating layer is formed on the first insulating layer and has a portion extending into the opening and the via to form a trench insulating layer. The bottom of the trench insulating layer is etched back to form a footing portion at the corner of the via. The footing portion has a height less than a total height of the first and second insulating layers.

Abstract: A semiconductor product is constructed of a wiring substrate in which pads for pin connection are formed, and a substrate with pins in which pins are disposed. The substrate with the pins is formed so that one end of the pin is exposed to one surface of a resin substrate formed by resin molding and the other end of the pin extends from the other surface of the resin substrate and one end of the pin is bonded to a pad of the wiring substrate through a conductive material.

Abstract: A structure of connecting at least two integrated circuits in a 3D arrangement by a metal-filled through silicon via which simultaneously connects a connection pad in a first integrated circuit and a connection pad in a second integrated circuit.

Abstract: A semiconductor device includes an integrated circuit (IC) die including a substrate, and at least one through substrate via (TSV) that extends through the substrate to a protruding integral tip that includes sidewalls and a distal end. The protruding integral tip has a tip height between 1 and 50 ?m. A metal layer is on the bottom surface of the IC die, and the sidewalls and the distal end of the protruding integral tips. A semiconductor device can include an IC die that includes TSVs and a package substrate such as a lead-frame, where the IC die includes a metal layer and an electrically conductive die attach adhesive layer, such as a solder filled polymer wherein the solder is arranged in an electrically interconnected network, between the metal layer and the die pad of the lead-frame.

Abstract: A method for forming a through substrate via (TSV) comprises forming an opening within a substrate. An adhesion layer of titanium is formed within the via opening, a nucleation layer of titanium nitride is formed over the adhesion layer, and a tungsten layer is deposited over the nucleation layer, the tungsten layer having a thickness less than or equal to a critical film thickness sufficient to provide for film integrity and adhesion stability. A stress relief layer of titanium nitride is formed over the tungsten layer and a subsequent tungsten layer is deposited over the stress relief layer. The subsequent tungsten layer has a thickness less than or equal to the critical film thickness. The method further includes planarizing to expose the interlevel dielectric layer and a top of the TSV and backgrinding a bottom surface of the substrate sufficient to expose a bottom portion of the TSV.

Abstract: The present disclosure provides a system and method for relieving stress and providing improved heat management in a 3D chip stack of a multichip package. A stress relief apparatus is provided to allow the chip stack to adjust in response to pressure, thereby relieving stress applied to the chip stack. Additionally, improved heat management is provided such that the chip stack adjusts in response to thermal energy generated within the chip stack to remove heat from between chips of the stack, thereby allowing the chips to operate as desired without compromising the performance of the chip stack. The chip stack also includes an array of flexible conductors disposed between two chips, thereby providing an electrical connection between the two chips.

Abstract: A device includes a semiconductor substrate including a front side and a backside. A through-substrate via (TSV) penetrates the semiconductor substrate. A dummy metal line is formed on the backside of the semiconductor substrate, and may be connected to the dummy TSV.

Abstract: An interposer is presented. The interposer includes an interposer base having first and second surfaces. A redistribution layer is disposed on a first surface of the interposer base. The interposer has at least one interposer pad coupled to the redistribution layer. It also includes at least one interposer contact on the second surface. The interposer contact is electrically coupled to the interposer pad via the redistribution layer. The interposer also includes at least one interposer via through the interposer base for coupling the interposer contact to the redistribution layer. The interposer via includes reflowed conductive material of the interposer contact.

Abstract: A disclosed semiconductor device includes a reinforcing board having first and second faces, an electronic part accommodating portion penetrating the reinforcing board, a through hole, an electronic part having a front face on which an electrode pad is formed and a back face, a through electrode installed inside the through hole, a first sealing resin filling a gap between the through electrode and an inner wall of the through hole, a second sealing resin filled into the electronic part accommodating portion while causing the bonding face of the electrode pad of the electronic part accommodating portion to be exposed to an outside, and a multi-layered wiring structure configured to include insulating layers laminated on the first face of the reinforcing board and an interconnection pattern, wherein the interconnection pattern is directly connected to the electrode pad of the electronic part and the through electrode.

Abstract: A circuit arrangement and method utilize hybrid bonding techniques that combine wafer-wafer bonding processes with chip-chip and/or chip-wafer bonding processes to form a multi-layer semiconductor stack, e.g., by bonding together one or more sub-assemblies formed by wafer-wafer bonding together with other sub-assemblies and/or chips using chip-chip and/or chip-wafer bonding processes. By doing so, the advantages of wafer-wafer bonding techniques, such as higher interconnect densities, may be leveraged with the advantages of chip-chip and chip-wafer bonding techniques, such as mixing and matching chips with different sizes, aspect ratios, and functions.

Abstract: A semiconductor device includes a chip stacked structure. The chip stacked structure may include, but is not limited to, first and second semiconductor chips. The first semiconductor chip has a first thickness. The second semiconductor chip has a second thickness that is thinner than the first thickness.

Abstract: A through silicon via (TSV) and a deep trench capacitor (DTCap) or a deep trench isolation (DTI) are simultaneously formed on the same substrate by a single mask and a single reactive ion etching (RIE). The TSV trench is wider and deeper that the DTCap or DTI trench. The TSV and DTCap or DTI are formed with different dielectric materials on the trench sidewalls. The TSV and DTCap or DTI are perfectly aligned.

Abstract: A semiconductor package having an internal cooling system is presented which includes a semiconductor chip and a through-electrode. The semiconductor chip has a circuit section. The through-electrode passes through an upper surface and a lower surface the semiconductor chip. The through-electrode is electrically connected with the circuit section of the semiconductor chip. The through-electrode also has a through-hole for allowing cooling fluid to flow therethrough.

Abstract: Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged microelectronic device can include a support member, a first die attached to the support member, and a second die attached to the first die in a stacked configuration. The device can also include an attachment feature between the first and second dies. The attachment feature can be composed of a dielectric adhesive material. The attachment feature includes (a) a single, unitary structure covering at least approximately all of the back side of the second die, and (b) a plurality of interconnect structures electrically coupled to internal active features of both the first die and the second die.

Abstract: An apparatus includes a coreless substrate with a through-silicon via (TSV) embedded die that is integral to the coreless substrate. The apparatus includes a subsequent die that is coupled to the TSV die and that is disposed above the coreless substrate.

Abstract: Example embodiments of the present invention relate to an interposer of a semiconductor device having an air gap structure, a semiconductor device using the interposer, a multi-chip package using the interposer and methods of forming the interposer. The interposer includes a semiconductor substrate including a void, a metal interconnect, provided within the void, thereby forming an air gap insulating the metal interconnect. The metal interconnect may be connected to a contact element, and may be maintained within the air gap using the contact element.

Abstract: A die that includes a substrate having a first and second major surface is disclosed. The die has at least one unfilled through via passing through the major surfaces of the substrate. The unfilled through via serves as a vent to release pressure generated during assembly.

Abstract: The semiconductor module includes a plurality of memory die on a first side of a substrate and a plurality of buffer die on a second side of the substrate. Each of the memory die is disposed opposite and electrically coupled to one of the buffer die.

Abstract: A die package structure, which comprises: a first die; a second die; a core material layer, provided between the first die and the second die; at least one via, penetrating through the first die, the second die and the core material layer; a metal material, stuffing into the via, such that the first die the second die, and the core material layer can be electrically contacted with each other; at least a signal contacting unit, contacting the metal material; and a dielectric layer, enclosing the first die, including at least one breach exposing the signal contacting unit.

Abstract: There is described a method of forming a through-silicon-via to form an interconnect between two stacked semiconductor components using pulsed laser energy. A hole is formed in each component, and each hole is filled with a plug formed of a first metal. One component is then stacked on another component such that the holes are in alignment, and a pulse of laser energy is applied to form a bond between the metal plugs.

Abstract: A stack package includes a substrate, a lower semiconductor chip stacked on the substrate and electrically connected to the substrate through a lower via, a plurality of upper semiconductor chips stacked on the lower semiconductor chip and electrically connected to the lower via through an upper via, wherein the upper semiconductor chips are larger in size than the lower semiconductor chip, and an edge guide electrically connecting edge vias of the upper semiconductor chips and the substrate.

Abstract: An address signal line having a stub structure connects between at least three memory elements and a data transferring element and transmits address signals for the memory elements. An address terminal of the data transferring element has an impedance lower than a characteristic impedance of the address signal line. A wiring length TL0 from the data transferring element to a first branch point S1 where a branch line is branched at a shortest distance from the data transferring element is configured to become equal to or greater than a wiring length TL1 from the first branch point S1 to a second branch point S2 where a second branch line is branched. A wiring length TL3 from the second branch point S2 to a third branch point S3 where a third branch line is branched is configured to become greater than the wiring lengths TL0 and TL1.

Abstract: A three-dimensional semiconductor device using redundant bonding-conductor structures to make inter-level electrical connections between multiple semiconductor chips. A first chip, or other semiconductor substrate, forms a first active area on its upper surface, and a second chip or other semiconductor substrate forms a second active area on its upper surface. According to the present invention, when the second chip has been mounted above the first chip, either face-up or face-down, the first active area is coupled to the second active area by at least one redundant bonding-conductor structure. In one embodiment, each redundant bonding-conductor structure includes at least one via portion that extends completely through the second chip to perform this function. In another, the redundant bonding-conductor structure extends downward to the top level interconnect. The present invention also includes a method for making such a device.

Abstract: A wafer-level package for semiconductor devices and a method for making the package. At least one dielectric layer is selectively printed on at least a portion of the semiconductor devices creating first recesses aligned with a plurality of electrical terminals on the semiconductor devices. A conductive material is printed in the first recesses to form contact members on the semiconductor devices. At least one dielectric layer is selectively printed to create a plurality of second recesses corresponding to a target circuit geometry. A conductive material is printed in at least a portion of the second recesses to create a circuit geometry. The circuit geometry includes a plurality of exposed terminals adapted to electrically couple to another circuit member. The wafer is diced to provide a plurality of discrete packaged semiconductor devices.

Abstract: The present disclosure relates to the field of integrated circuit package design and, more particularly, to packages using a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of fabricating microelectronic packages, wherein a first microelectronic device having through-silicon vias may be stacked with a second microelectronic device and used in a bumpless build-up layer package.

Abstract: A circuit arrangement and method in one aspect utilize thermal-only through vias, extending between the opposing faces of stacked semiconductor dies, to increase the thermal conductivity of a multi-layer semiconductor stack. The thermal vias are provided in addition to data-carrying through vias, which communicate data signals between circuit layers, and power-carrying through vias, which are coupled to a power distribution network for the circuit layers, such that the thermal conductivity is increased above that which may be provided by the data-carrying and power-carrying through vias in the stack. A circuit arrangement and method in another aspect organize the circuit layers in a multi-layer semiconductor stack based upon current density so as to reduce power distribution losses in the stack.

Abstract: A semiconductor wafer scale package system is provided including providing a semiconductor substrate having a through-hole via with a conductive coating, forming a filled via by filling the through-hole via with a conductive material, coupling a package substrate to the filled via, and singulating a chip scale package from the semiconductor substrate and the package substrate.

Abstract: A semiconductor device 1 has a semiconductor chip 10. The semiconductor chip 10 is constituted as having a semiconductor substrate 12 and an interlayer insulating film 14 on the semiconductor substrate 12. The semiconductor substrate 12 has a plurality of through electrodes 22 (first through electrodes) and a plurality of through electrodes 24 (second through electrodes) formed therein. On the top surface S1 (first surface) of the semiconductor chip 10, there are provided connection terminals 32 (first connection terminals) and connection terminals 34 (second connection terminals). The connection terminals 32, 34 are connected to the through electrodes 22, 24, respectively. The connection terminals 32 herein are disposed at positions overlapping the through electrodes 22 in a plan view. On the other hand, the connection terminals 34 are disposed at positions not overlapping the through electrodes 24 in a plan view.