Abstract: The present invention relates to a semiconductor device packaged at the wafer level such that an entire packaged device is formed prior to separation of individual devices. The semiconductor device package includes a semiconductor chip having one or more bonding pads associated with the chip and a protective layer bonded over the semiconductor chip. An insulation layer is positioned on at least side edges and a lower surface of the semiconductor chip. Interconnection/bump metallization is positioned adjacent one or more side edges of the semiconductor chip and is electrically connected to at least one bonding pad. A compact image sensor package can be formed that is vertically integrated with a digital signal processor and memory chip along with lenses and a protective cover.

Abstract: A method for manufacturing semiconductor devices is disclosed. A semiconductor wafer is provided having a first surface and a second surface opposite to the first surface. A first glass substrate is provided which has at least one of cavities and openings at the bonding surface. The first glass substrate is bonded to the first surface of the semiconductor wafer such that the metal pads are arranged within respective cavities or openings of the first glass substrate. The second surface of the semiconductor wafer is machined. At least one metallisation region is formed on the machined second surface of the semiconductor wafer.

Abstract: The invention includes methods of forming layers conformally over undulating surface topographies associated with semiconductor substrates. The undulating surface topographies can first be exposed to one or more of titanium oxide, neodymium oxide, yttrium oxide, zirconium oxide and vanadium oxide to treat the surfaces, and can be subsequently exposed to a material that forms a layer conformally along the treated surfaces. The material can, for example, comprise one or both of aluminum silane and aluminum silazane. The invention also includes semiconductor constructions having conformal layers formed over liners containing one or more of titanium oxide, yttrium oxide, zirconium oxide and vanadium oxide.

Abstract: A method for manufacturing a semiconductor package that includes forming a frame inside a conductive can, the frame being unwettable by liquid solder.

Abstract: A sample liquid supply container is disclosed. The sample liquid supply container includes a first region which is depressurized therein and is hermetically sealed, a second region which is able to receive a liquid therein, a first penetration portion, in which an interior of the first region is punctured by a hollow needle from outside, and a second penetration portion, in which an interior of the second region is punctured by the hollow needle inserted into the first penetration portion and reaches inside the first region.

Abstract: A package for an optical semiconductor element is provided. The package includes: a stem body having a sealing hole therein; and a lead pin having a glass sealing portion which is sealed with sealing glass in the sealing hole. Characteristic impedance of the glass sealing portion is adjusted to a given value. The characteristic impedance Zo is given by: Zo=(138/Er1/2)×log(D/d), where a hole diameter of the sealing hole is D, a wire diameter of the lead pint is d, and a dielectric constant of the sealing glass is Er, and the dielectric constant Er of the sealing glass is set by controlling an amount of bubble contained in the sealing glass.

Abstract: An electronic component includes a number of leads and at least one cooling element. The bottom surface of the cooling element is exposed and the material of the cooling element is different from the material of the leads. At least one semiconductor chip is provided on the cooling element. An encapsulation compound covers at least part of the leads, at least part of the semiconductor chip(s), and at least part of the cooling element(s).

Abstract: Disclosed is a protective film for an electronic component comprising a base material containing a heat resistant resin and an adhesive layer formed on the base material containing an ethylene-unsaturated carboxylic acid copolymer or a metal salt thereof, wherein the ethylene-unsaturated carboxylic acid copolymer or the metal salt thereof contains 3 to 30% by weight of the structural unit derived from an unsaturated carboxylic acid.

Abstract: A glass cap molding package includes a substrate with an external connection terminal formed on a peripheral region of a top surface; an image sensor mounted on the top surface of the substrate; a transparent member installed on an upper part of the image sensor; and a molding unit formed to seal the image sensor and the transparent member. The mold unit exposes the external connection terminal of the substrate to a lateral surface of the substrate. The glass cap molding package and a manufacturing method thereof and a camera module including the same reduce a manufacturing cost and improve productivity by manufacturing a small module in comparison with a conventional module and simplifying a process.

Abstract: An integrated circuit pad structure includes a ground strip (206) positioned below a pad (101). In one example a conductive element (102) is coupled to the pad (101), and at least two tiled layers, positioned below the first conductive element (102) and positioned above the ground strip (206) are included. A conductor (203), may run beneath the ground strip (206). In a second example, a pad (101) is seated on a ground shield cage having a bottom conductive ground element (302) including several ground strips where at least one ground strip (116) is along a signal routing path. The ground shield cage further includes a set of stacked conductive ground elements, stacked to form sidewalls (209, 210) of the cage. The top conductive ground element (301) of the stacked elements has an inner perimeter and an outer perimeter, such that the inner perimeter surrounds the pad (101) and the top conductive ground element (301) is in the plane of the conductive element (102) coupled to the pad (101).

Abstract: A package structure and an electronic device using the same are provided. The package structure includes a chip module and a cover. The chip module covered by the cover is used for receiving a first signal. The chip module includes a substrate, a heat sink and a first chip. The substrate has a first surface, a second surface and an opening. The first surface is opposite to the second surface. The opening penetrates the first surface and the second surface. The heat sink is disposed on the first surface of the substrate and covers the opening. The first chip is disposed on the heat sink and is positioned inside the opening. A bottom surface of the first chip flatly contacts the heat sink. The cover has a window element. The first signal passes through the window element to contact with the chip module.

Abstract: A semiconductor device has a first semiconductor die with a shielding layer formed over its back surface. The first semiconductor die is mounted to a carrier. A first insulating layer is formed over the shielding layer. A second semiconductor die is mounted over the first semiconductor die separated by the shielding layer and first insulating layer. A second insulating layer is deposited over the first and second semiconductor die. A first interconnect structure is formed over the second semiconductor die and second insulating layer. A second interconnect structure is formed over the first semiconductor die and second insulating layer. The shielding layer is electrically connected to a low-impedance ground point through a bond wire, RDL, or TSV. The second semiconductor die may also have a shielding layer formed on its back surface. The semiconductor die are bonded through the metal-to-metal shielding layers.

Abstract: Embodiments of the present invention provide a system and method for manufacturing integrated circuit (IC) chip packages. In one embodiment, the integrated circuit (IC) chip package can include an IC chip and a substrate coupled to the IC chip. The substrate can include a glass fiber re-enforced epoxy core, a plurality copper circuitry containing particle re-enforced epoxy layers symmetrically-oriented to each surface of the glass fiber re-enforced epoxy core, and an outermost amorphous glass layer on each surface of the plurality of layers. The IC chip can be coupled to copper circuitry bonded to one of the outermost amorphous glass layers.

Abstract: The invention includes methods of forming layers conformally over undulating surface topographies associated with semiconductor substrates. The undulating surface topographies can first be exposed to one or more of titanium oxide, neodymium oxide, yttrium oxide, zirconium oxide and vanadium oxide to treat the surfaces, and can be subsequently exposed to a material that forms a layer conformally along the treated surfaces. The material can, for example, comprise an aluminum-containing compound and one or both of silane and silazane. The invention also includes semiconductor constructions having conformal layers formed over liners containing one or more of titanium oxide, yttrium oxide, zirconium oxide and vanadium oxide.

Abstract: A sensor package includes an image sensing chip having a front surface, a plurality of bumps, a glass cover plate, and a connector. The plurality of bumps are formed on the front surface, and are electrically connected to the image sensing chip. The glass cover plate has a bottom surface facing the front surface, and the glass cover plate has a plurality of transparent conductive wires formed on the bottom surface. A terminal of each of the transparent conductive wires is electrically connected to a respective bump, and another terminal of each of the transparent conductive wires extends out of an orthogonal projection area of the image sensing chip on the bottom surface. The connector is electrically connected to the another terminal of each of the transparent conductive wires.

Abstract: A packaging substrate having a semiconductor chip embedded and a fabrication method thereof are provided. The method includes forming a semiconductor chip in a through cavity of a core board and exposing a photosensitive portion of the semiconductor chip from the through cavity; sequentially forming a first dielectric layer and a first circuit layer on the core board, the first circuit layer being electrically connected to the electrode pads of the semiconductor chip; forming a light-permeable window on the first dielectric layer to expose the photosensitive portion of the semiconductor chip and adhering a light-permeable layer onto the light-permeable window, thereby permitting light to penetrate through the light-permeable layer to reach the photosensitive portion. Therefore, when fabricated with the method, the packaging substrate dispenses with conductive wires and dams and thus can be downsized.

Abstract: A disclosed semiconductor device comprises a substrate, an element on the substrate and a sealing structure for sealing the element. The sealing structure has a structure such that a partition wall made of a metallic material formed on the substrate by a plating method so as to surround the element and a cap portion disposed on the partition wall are bonded via a bonding layer made of an inorganic material.

Abstract: A cap wafer with cavities is etched through areas not covered by a patterned photoresist to form a plurality of openings. The cap wafer is bonded to a transparent wafer at the surface having the cavities and is segmented around the cavities to form a plurality of cap structures. The cap structures are hermetically sealed to a device wafer to form hermetic windows over devices and pads located on the device wafer.

Abstract: A package for an optical semiconductor element is provided. The package includes: a stem body having a sealing hole therein; and a lead pin having a glass sealing portion which is sealed with sealing glass in the sealing hole. Characteristic impedance of the glass sealing portion is adjusted to a given value. The characteristic impedance Zo is given by: Zo=(138/Er1/2)×log(D/d), where a hole diameter of the sealing hole is D, a wire diameter of the lead pint is d, and a dielectric constant of the sealing glass is Er, and the dielectric constant Er of the sealing glass is set by controlling an amount of bubble contained in the sealing glass.

Abstract: A method for manufacturing a semiconductor package that includes forming a frame inside a conductive can, the frame being unwettable by liquid solder.

Abstract: A structure and a method for forming the same. The structure includes (i) a carrier substrate which includes substrate pads, (ii) a chip physically attached to the carrier substrate, and (iii) a first frame physically attached to the carrier substrate. A CTE (coefficient of thermal expansion) of the first frame is substantially lower than a CTE of the carrier substrate.

Abstract: A semiconductor sensor device is electrically coupled to an object. An attachment member attaches the semiconductor sensor device to the object. The attachment member comprises a first conductive contact region and a second conductive contact region. An insulating portion is electrically isolates the semiconductor sensor device from the first conductive contact region and second conductive contact region.

Abstract: A cerdip type of solid-state image sensing device includes a base on which photoelectric transfer devices are arranged in line along a main scanning direction, a sealed glass disposed on the base for fixing a lead frame, a wind frame disposed on the sealed glass, a transparent cover glass disposed on the wind frame, and a gripped surface for gripping the cerdip type of solid-state image sensing device.

Abstract: The invention discloses a subminiature electronic device with a hermetic cavity and method of manufacturing the same. It particularly relates to a chip type or chip scale packaged electronic device produced in substrate level. Firstly, a sacrificial layer is coated onto each of the identical microstructures disposed on a large substrate. A protective layer containing glass powders is then applied to encapsulate the sacrificial layer. Afterwards, the sacrificial layer is removed so as to form a cavity between the microstructure and the protective layer. The whole protective layer is then melted at elevated temperature to seal the cavity in an environment of specific gas. Finally, the large substrate is diced into a plurality of individual devices with a hermetic cavity over the microstructure. The applicable fields include micro-electronic circuits, micro-vibration systems, micro electrical-mechanical systems (MEMS), and gas discharge apparatuses.

Abstract: a method of manufacturing a semiconductor device including (1) providing a metal plate having an upper surface and a back surface, the metal plate including a plurality of lids disposed in matrix, which are defined by a first groove formed from the upper surface, (2) providing a ceramic sheet having an upper surface and a back surface, the ceramic sheet including a plurality of headers disposed in matrix, which are defined by a second groove formed from the back surface, (3) fixing the metal plate on the ceramic sheet by facing the back surface of the onto metal plate to the upper surface of the ceramic sheet, wherein the first groove is aligned with the second groove, and (4) dividing the metal plate and the ceramic sheet along the first and the second grooves.

Abstract: A semiconductor device may be fabricated according to a method that reduces stain difference of a passivation layer in the semiconductor device. The method may include forming top wiring patterns in a substrate, depositing a primary undoped silicate glass (USG) layer on the top wiring patterns to fill a gap between the top wiring patterns, and coating a SOG layer on the substrate on which the primary USG layer has been deposited. Next, the SOG layer on the surface of the substrate may be removed until the primary USG layer is exposed, and a secondary USG layer may be deposited on the substrate on which the primary USG layer has been exposed.

Abstract: An electronic device, such as a mini card, has an inlay substrate for the electronic device. The inlay includes a substrate layer, a communication interface having a first metallization supported by the substrate layer, a hole or a hole location area, for attachment to an external device, and a second metallization surrounding at least partially the hole or its location area. The second metallization strengthens the card at the hole area. The method includes realizing the first and second metallizations on the same machine and/or at the same time.

Abstract: A glass-sealed type semiconductor device has Dumet electrodes, a glass sealing member, and a semiconductor element tightly sealed in a cavity constituted by the Dumet electrodes and the glass sealing member. The semiconductor element is constituted by a Schottky barrier diode. External leads serving as external terminals of the semiconductor device are connected to the Dumet electrodes, respectively. The Dumet electrodes have core portions comprised of a nickel-iron alloy, copper layer formed on the outer peripheries of the core portions, and copper oxide layers formed on the outer surfaces of the copper layers, respectively. The ratios of the copper layers are 20 wt % or more each.

Abstract: A MEMS module package includes a housing with an accommodation chamber and an opening in communication with the accommodation chamber. The housing has a substrate and an electrically insulative cap capped on the substrate and defining with the substrate the accommodation chamber therebetween. A micro electro-mechanical chip is installed on the substrate and located inside the accommodation chamber. The micro electro-mechanical chip has an action zone corresponding to the opening of the housing. A first conducting layer and a second conducting layer are respectively disposed on an inner surface and an outer surface of the electrically insulative cap.

Abstract: The specification teaches a system for manufacturing microelectronic, microoptoelectronic or micromechanical devices (microdevices) in which a contaminant absorption layer improves the life and operation of the microdevice. In an embodiment, a system for manufacturing the devices includes efficiently integrating a getter material in multiple microdevices.

Abstract: The invention relates to a semiconductor device (1) comprising a semiconductor chip stack (2) and a plastic housing (3), and to methods for producing the semiconductor device (1). The semiconductor device (1) is constructed on a device carrier (4), on which a first semiconductor chip (5) is fixed by its rear side (6). At least one second semiconductor chip (8) is adhesively bonded by its rear side (9) on the top side (7) of the first semiconductor chip (5) by means of an adhesive layer (10). A second plastic composition (17) is arranged between a first plastic housing composition (11) of the plastic housing (3) and the edge sides (12, 13) of the adhesive layer and the edge sides (14, 15) of the second semiconductor chip (8) and also the top side (16) of the second semiconductor chip (8) in such a way that the first plastic housing composition (11) has no physical contact with the second semiconductor chip (8) and with the adhesive layer (10).

Abstract: A semiconductor device includes a semiconductor substrate; a circuit; a guard ring; a power source line; and a contact. The semiconductor substrate has a first conductive type. The circuit is formed on the semiconductor substrate. The guard ring is formed on the semiconductor substrate such that the guard ring surrounds the circuit. The power source line supplies an electric power both the circuit and the guard ring. The contact is formed on the guard ring and connects the guard ring and the power source line. The guard ring is composed of a semiconductor having a second conductive type opposite to the first conductive type. The contact is placed in an opposite side of a noise source over the circuit.

Abstract: A semiconductor device includes an insulator substrate mounted on a base plate, the insulator substrate having an upper electrode, semiconductor chips mounted on the insulator substrate, external terminals for establishing external electrical connections of the semiconductor device, wires for establishing electrical connections among the external terminals, the upper electrode and the semiconductor chips, a case accommodating the insulator substrate, the semiconductor chips, the external terminals and the wires which are sealed by a sealing material filled in the case, a lid for protecting an upper part of the sealing material, and an insulative low electrification covering fitted on each wire, the low electrification covering having a lesser tendency to produce an electric charge buildup than the sealing material.

Abstract: A surface acoustic wave device has a SAW device element 10 and a package 20 housing the SAW device element. The package includes a resin substrate 20 having metal patterns 21 and 22 formed on both surfaces thereof, and a resin cap 32. The SAW device element is mounted on one of the metal patterns of the resin substrate. The resin cap is adhered to the resin substrate to cover the SAW device element. The surfaces of the resin substrate are flush with corresponding end surfaces of the resin cap.

Abstract: A multilayer ceramic repair process which provides a new electrical repair path to connect top surface vias. The repair path is established between a defective net and a redundant repair net contained within the multilayer ceramic substrate. The defective net and the repair net each terminate at surface vias of the substrate. A laser is used to form post fired circuitry on and in the substrate. This is followed by the electrical isolation of the defective net from the electrical repair structure and passivation of the electrical repair line.

Abstract: The invention is directed to a hermetically packaged and implantable integrated circuit for electronics that is made by producing streets in silicon-on-insulator chips that are subsequently coated with a selected electrically insulating thin film prior to completing the dicing process to yield an individual chip. A thin-layered circuit may transmit light, allowing a photodetector to respond to transmitted light to stimulate a retina, for example. Discrete electronic components may be placed in the three-dimensional street area of the integrated circuit package, yielding a completely integrated hermetic package that is implantable in living tissue.

Abstract: A package structure for optical image sensing devices is disclosed. The package structure includes an image sensing integrated circuit chip having a light receiving side and a backside. The image sensing integrated circuit chip has a light sensing area on the light receiving side. A plurality of light sensing devices are arranged in the light sensing area for converting incident light into electrical signals. A plurality of bonding pads are arranged along one or two sides of the light sensing area. Black sealing glue is asymmetrically coated on the outskirts of the light sensing area. The black sealing glue has at least two coating widths. A glass lid is glued over the light sensing area with the sealing glue.