Abstract: A stacked-type chip package structure in which stacked chips and stacked flexible circuit boards are disposed on a substrate. A plurality of spacer layers is respectively sandwiched between two adjacent chips and stacked on top of each other. In addition, conductive bumps are disposed on the substrate and between the stacked flexible circuit boards, such that the stacked flexible circuit boards are electrically connected to the substrate. Besides, conductive wires are electrically connected between the flexible circuit boards and the chips, so as to form a package structure with multi-layer chips on the substrate. Thereby, electrical performance and reliability of the chips are improved.

Abstract: Embodiments comprise an adjusted polysilicon gate pitch to metal wire pitch relationship to improve area scalars while increasing ACLV tolerance with a fixed polysilicon gate pitch. In some embodiments, the wire pitch for at least one metallization layer is adjusted to match the pitch for the polysilicon gate. In one embodiment, the next to the lowest metallization layer running in the same orientation as the polysilicon gate, utilized to access the input or output of the interconnected cell structures is relaxed to match the minimum contacted gate pitch and the metal is aligned above each polysilicon gate. In another embodiment, the polysilicon gate pitch may be relaxed to attain a smaller lowest common multiple with the wire pitch for an integrated circuit to reduce the minimum step off.

Abstract: A polymer-based, self-aligned wafer-level heterogeneous integration system, SAWLIT, for integrating semiconductor integrated circuit (IC) chips to a substrate is presented. The system includes a method including preparing a substrate, flipping the substrate onto a polymer-based flat surface and securing the substrate to the flat surface, mounting semiconductor chips into the prepared substrate, integrating the chips to the substrate with another polymer-based material, and removing the resulting multi-chip module from the flat surface. The chips may then be connected with each other and regions off the multi-chip module with metal interconnect processing technology. A multi-chip module prepared by the polymer-based, self-aligned heterogeneous integration system including semiconductor chips mounted in a prepared substrate. The chips may be connected to the substrate by a polymer-based integrating material.

Abstract: An apparatus is described incorporating an interposer having a cavity for a portion of an antenna structure, having conductor through vias, a top Si part having interconnection wiring and having pads for electrically mounting an integrated circuit chip thereon, wherein the top Si part mates with the interposer electrically and mechanically. The interposer and top Si part may be scaled to provide an array of functional units. The invention overcomes the problem of combining a high efficient antenna with integrated circuit chips in a Si package with signal frequencies from 1 to 100 GHz and the problem of shielding components proximate to the antenna and reduces strain arising from mismatching of TCEs.

Abstract: One embodiment of the present invention provides an integrated chip module and a corresponding method of manufacture that facilitates proximity communication. This module includes a base chip and a bridge chip, both of which include an active face, upon which active circuitry and signal pads reside, and a back face opposite the active face. The active face of the bridge chip is bonded to the active face of the base chip, and the back face of the bridge chip is thinned via planarization or polishing.

Abstract: The invention relates to a method for producing a matrix of electronic components, comprising a step of producing an active layer on a substrate, and a step of individualizing the components by forming trenches in the active layer at least until the substrate emerges. The method comprises steps of depositing a layer of functional material on the active layer, depositing a photosensitive resin on the layer of material in such a way as to fill said trenches and to form a thin film on the upper face of the components, at least partially exposing the resin to radiation while underexposing the portion of resin in the trenches, developing the resin in such a way as to remove the properly exposed portion thereof, removing the functional material layer portion that shows through after the development step, and removing the remaining portion of resin.

Abstract: The present invention relates to a three-dimensional semiconductor module having at least one unit semiconductor device connected to the outer-facing side surfaces of a multi-side ground block. The unit semiconductor device has a structure in which a semiconductor package (or semiconductor chip) is mounted on a unit wiring substrate. Ground pads to be connected to the outer-facing side surfaces of the ground block are formed on the first surface of the unit wiring substrate, the semiconductor chip is mounted on the second surface opposite to the first surface, and contact terminals electrically connected to the semiconductor chip are formed on the second surface.

Abstract: A semiconductor integrated circuit device includes a main region on which a main circuit is formed and a spare cell region for logic modification of the circuit formed on the main region. The spare cell region includes a P-channel transistor region, an N-channel transistor region, a plurality of gate electrodes provided above the P-channel transistor region and the N-channel transistor region, a main wire layer that is a different layer from the gate electrodes, and a plurality of bypass wires that are formed at a different layer from the main wire layer. Each of the plurality of bypass wires has a structure that can be connected to the main wire layer at more than one point through contact holes formed in a dielectric layer intervening between the main wire layer and the bypass wires.

Abstract: A memory card includes a first cover, a second cover, a set of leads and a memory component. The first cover has a set of openings; the second cover is combined with the first cover to define a holding space. The leads are arranged in the holding space, and their one end are emerged from the openings as an exterior terminal. The memory component arranged in the holding space includes a chip substrate and at least one function component electrically connected with the chip substrate, wherein the chip substrate has a set of conductive pads electrically connected to the other end of the leads. According to the above-mentioned structure, the memory card with smaller chip substrate is designed to reduce manufacture cost.

Abstract: A semiconductor module has a coupling substrate which is used for the internal electrical coupling of an integrated circuit on adjacent semiconductor chips. The semiconductor chips have integrated circuits and are arranged on a mount structure. The semiconductor chips are externally connected to external contacts. The coupling substrate overlaps edge areas of the adjacent semiconductor chips.

Abstract: A semiconductor wafer has different impurity concentrations in respective regions and gate patterns have different lengths in the respective regions. The semiconductor wafer has different impurity concentrations in a central region, an intermediate region, and an outer region. The gate patterns have different lengths in the central region, the intermediate region, and the outer region. Accordingly, the semiconductor wafer may have a substantially uniform threshold voltage throughout the semiconductor wafer.

Abstract: A liquid crystal display (LCD) panel is fabricated in a simplified process. The LCD panel includes a thin film transistor (TFT) array substrate with a gate and data lines crossing each other to define a pixel area, a TFT at the crossings of the gate and data lines, a protective film, and a pixel electrode connected to the TFT and formed within a pixel opening that is arranged at the pixel area and formed through the protective film and a gate insulating film. A color filter array substrate is joined to the TFT array substrate. A pattern spacer is between the TFT and color filter array substrate and overlaps at least one of the gate line, the data line, and the thin film transistor. A rib is formed from the same layer as the pattern spacer and overlaps the pixel electrode. Liquid crystal material is provided within the LCD panel.

Abstract: A package for packaging one or more MEMS devices is disclosed. A package in accordance with an illustrative embodiment of the present invention can include a packaging structure having a base section, a top section, and an interior cavity adapted to contain a number of MEMS devices therein. In some embodiments, the packaging structure can include a first side, a second side, a third side, and a top end, which, in certain embodiments, may form a pinout plane surface that can be used to connect the packaging structure to other external components. In some embodiments, a number of MEMS-type inertial sensors contained within the interior cavity of the packaging structure can be used to detect and measure motion in multiple dimensions, if desired.

Abstract: A first semiconductor element is mounted on a base plate, and is in a sealed state by the periphery thereof being covered by an insulation member, and the upper surface thereof being covered by an upper insulation film. An upper wiring layer formed on the upper insulation film, and the lower wiring layer formed below the base plate via lower insulation films are connected by conductors. A second semiconductor element is mounted exposed, being connected to the lower wiring layer.

Abstract: A circuit module for use in a memory card. The circuit module comprises a base substrate including a plurality of contacts. Attached to the base substrate is a memory die, while attached to the memory die is an interposer having a plurality of terminals electrically connected to each other in a prescribed pattern. At least one of the terminals is electrically connected to at least one of the contacts. Attached to the interposer is a controller die, with the memory die and the controller die each being electrically connected to at least one of the terminals of the interposer.

Abstract: A semiconductor module according to the invention includes: an island formed of a conductive material; a plurality of leads disposed in vicinity of the island; a resin sealing body which is mounted on the island and disposed such that a back surface of a circuit board on which semiconductor elements is exposed upward; a sensor which is mounted on the back surface of the circuit board; and a thin metallic wire which electrically connects the circuit board with the leads. The island, the resin sealing body, the sensor, and parts of the leads are sealed by a second sealing resin.

Abstract: In a semiconductor apparatus of the present invention, a plurality of circuit components are provided. A first bus interconnects the circuit components. A second bus interconnects the circuit components. A switching unit outputs a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another. The second bus has a size larger than a size of the first bus.