Including Components Formed On Opposite Sides Of A Semiconductor Substrate (epo) Patents (Class 257/E27.027)
  • Patent number: 9024408
    Abstract: A method of manufacturing double-sided semiconductor die by performing a first plurality of processes to a first side of a wafer and performing a second plurality of processes to a second side of the wafer, thereby forming at least a first semiconductor device on the first side of the wafer and at least a second semiconductor device on the second side of the wafer. The wafer may be cut to form a plurality of die having at least one semiconductor device on each side.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: May 5, 2015
    Assignee: STMicroelectronics, Inc.
    Inventor: Ming Fang
  • Patent number: 8866193
    Abstract: According to one disclosed embodiment, a monolithic vertically integrated composite device comprises a double sided semiconductor substrate having first and second sides, a group IV semiconductor layer formed over the first side and comprising at least one group IV semiconductor device, and a group III-V semiconductor body formed over the second side and comprising at least one group III-V semiconductor device electrically coupled to the at least one group IV semiconductor device. The composite device may further comprise a substrate via and/or a through-wafer via providing electric coupling. In one embodiment, the group IV semiconductor layer may comprise an epitaxial silicon layer, and the at least one group IV semiconductor device may be a combined FET and Schottky diode (FETKY) fabricated on the epitaxial silicon layer. In one embodiment, the at least one group semiconductor device may be a III-nitride high electron mobility transistor (HEMT).
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: October 21, 2014
    Assignee: International Rectifier Corporation
    Inventor: Michael A. Briere
  • Patent number: 8716780
    Abstract: A memory device includes a planar substrate, a plurality of horizontal conductive planes above the planar substrate, and a plurality of horizontal insulating layers interleaved with the plurality of horizontal conductive planes. An array of vertical conductive columns, perpendicular to the pluralities of conductive planes and insulating layers, passes through apertures in the pluralities of conductive planes and insulating layers. The memory device includes a plurality of programmable memory elements, each of which couples one of the horizontal conductive planes to a respective vertical conductive column.
    Type: Grant
    Filed: August 26, 2010
    Date of Patent: May 6, 2014
    Assignee: Rambus Inc.
    Inventors: Mark D. Kellam, Gary B. Bronner
  • Patent number: 8557644
    Abstract: According to one disclosed embodiment, a monolithic vertically integrated composite device comprises a double sided semiconductor substrate having first and second sides, a group IV semiconductor layer formed over the first side and comprising at least one group IV semiconductor device, and a group III-V semiconductor body formed over the second side and comprising at least one group III-V semiconductor device electrically coupled to the at least one group IV semiconductor device. The composite device may further comprise a substrate via and/or a through-wafer via providing electric coupling. In one embodiment, the group IV semiconductor layer may comprise an epitaxial silicon layer, and the at least one group IV semiconductor device may be a combined FET and Schottky diode (FETKY) fabricated on the epitaxial silicon layer. In one embodiment, the at least one group III-V semiconductor device may be a III-nitride high electron mobility transistor (HEMT).
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: October 15, 2013
    Assignee: International Rectifier Corporation
    Inventor: Michael A. Briere
  • Patent number: 8536579
    Abstract: The invention relates to an electronic device including a sequence of a first thin film transistor (TFT) and a second TFT, the first TFT including a first set of electrodes separated by a first insulator, the second TFT comprising a second set of electrodes separated by a second insulator, wherein the first set of electrodes and the second set of electrodes are formed from a first shared conductive layer and a second shared conductive layer, the first insulator and the second insulator being formed by a shared dielectric layer. The invention further relates to a method of manufacturing an electronic device.
    Type: Grant
    Filed: July 16, 2008
    Date of Patent: September 17, 2013
    Assignee: Creator Technology B.V.
    Inventors: Christoph Wilhelm Sele, Monica Johanna Beenhakkers, Gerwin Hermanus Gelinck, Nicolaas Aldegonda Jan Maria Van Aerle, Hjalmar Edzer Ayco Huitema
  • Patent number: 8476708
    Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor substrate, memory cell array portion, single-crystal semiconductor layer, and circuit portion. The memory cell array portion is formed on the semiconductor substrate, and includes memory cells. The semiconductor layer is formed on the memory cell array portion, and connected to the semiconductor substrate by being formed in a hole extending through the memory cell array portion. The circuit portion is formed on the semiconductor layer. The Ge concentration in the lower portion of the semiconductor layer is higher than that in the upper portion of the semiconductor layer.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: July 2, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Fukuzumi, Hideaki Aochi, Masaru Kito, Kiyotaka Miyano, Shinji Mori, Ichiro Mizushima
  • Patent number: 8426926
    Abstract: A semiconductor device includes a device isolation pattern, a gate line, and an epitaxial pattern. The device isolation pattern is disposed in a semiconductor substrate to define an active area. The gate line intersects the active area. The epitaxial pattern fills a recess region in the active area at one side of the gate line and includes a different constituent semiconductor element than the semiconductor substrate. The recess region includes a first inner sidewall that is adjacent to the device isolation pattern and extends in the lengthwise direction of the gate, and a second inner sidewall that extends in the direction perpendicular to the lengthwise direction of the gate line. The active area forms the first inner sidewall of the recess, while the device isolation layer forms at least a portion of the second inner sidewall of the recess. The epitaxial pattern contacts the first inner sidewall and the second inner sidewall of the recess region.
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: April 23, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dongsuk Shin, Dong Hyuk Kim, Myungsun Kim, YongJoo Lee, Hoi Sung Chung
  • Patent number: 8299572
    Abstract: According to an exemplary embodiment, a semiconductor die includes a backside surface opposite an active surface. The active surface includes at least one active device. The semiconductor die includes at least one passive device situated on the backside surface. The semiconductor die further includes an interconnect region situated over the active surface. The semiconductor die further includes at least one through-wafer via, where the at least one through-wafer via electrically connects the at least one passive device to the interconnect region. The interconnect region can include a number of solder bump pads or a number of bond pads.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: October 30, 2012
    Assignee: Skyworks Solutions, Inc
    Inventor: Russ Reisner
  • Publication number: 20120181683
    Abstract: A three-dimensionally integrated semiconductor device includes a flexible circuit substrate which has a lower portion, an upper portion, and at least one side portion, a support body which supports the upper portion of the flexible circuit substrate, and at least two devices mounted on the flexible circuit substrate and wherein at least one of the devices is mounted on an upper surface of the lower portion of the flexible circuit substrate, at least one of the other devices is mounted on a lower surface of the upper portion of the flexible circuit substrate, and a gap is provided between the device mounted on the upper surface of the lower portion of the flexible circuit substrate and the device mounted on the lower surface of the upper portion of the flexible circuit substrate.
    Type: Application
    Filed: January 17, 2012
    Publication date: July 19, 2012
    Inventors: TAKAO YAMAZAKI, Shizuaki Masuda
  • Patent number: 8198698
    Abstract: To improve a performance of a semiconductor device having a capacitance element. An MIM type capacitance element, an electrode of which is formed with comb-shaped metal patterns composed of the wirings, is formed over a semiconductor substrate. A conductor pattern, which is a dummy gate pattern for preventing dishing in a CMP process, and an active region, which is a dummy active region, are disposed below the capacitance element, and these are coupled to shielding metal patterns composed of the wirings and then connected to a fixed potential. Then, the conductor pattern and the active region are disposed so as not to overlap the comb-shaped metal patterns in the wirings in a planar manner.
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: June 12, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Satoshi Maeda, Yasushi Sekine, Tetsuya Watanabe
  • Patent number: 8125073
    Abstract: A semiconductor device has a wafer for supporting the device and a conductive layer formed over a top surface of the wafer. A carrier wafer is permanently bonded over the conductive layer. Within the wafer and the carrier wafer, an interconnect structure is formed. The interconnect structure includes a first via formed in the wafer that exposes the conductive layer, a second via formed in the carrier wafer that exposes the conductive layer, a first metal layer deposited over the first via, the first metal layer in electrical contact with the conductive layer, and a second metal layer deposited over the second via, the second metal layer in electrical contact with the conductive layer. First and second insulation layers are deposited over the first and second metal layers respectively. The first or second insulation layer has an etched portion to expose a portion of the first or second metal layer.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: February 28, 2012
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Byung Joon Han, Nathapong Suthiwongsunthorn, Pandi Chelvam Marimuthu, Kock Liang Heng
  • Patent number: 8110832
    Abstract: An electro-optical substrate, including: a transparent substrate; a first light-shielding layer arranged on a first surface of the transparent substrate, in at least part of a region surrounding an opening in plan view; a first insulating layer arranged in a position facing the transparent substrate with the first light-shielding layer interposed therebetween, the first insulating layer having a refraction index n and a layer thickness t measured in nanometers, and covering at least part of the first light-shielding layer; a semiconductor layer, arranged in a position facing the transparent substrate, with the first light-shielding layer interposed therebetween, containing part of a thin film transistor, the thin film transistor including a channel region which is, in plan view, positioned within the first light-shielding layer, a corner edge of the first light-shielding layer and a corner edge of the channel region having a distance Lc therebetween in nanometers, the distance Lc satisfying relational express
    Type: Grant
    Filed: February 21, 2008
    Date of Patent: February 7, 2012
    Assignee: Seiko Epson Corporation
    Inventor: Yasushi Hiroshima
  • Publication number: 20120001297
    Abstract: A semiconductor die includes a semiconductive substrate layer with first and second sides, a metal layer adjacent the second side of the semiconductive substrate layer, one or more active devices in an active layer on the first side of the semiconductive substrate layer; and a passive device in the metal layer in electrical communication with the active layer. The passive device can electrically couple to the active layer with through silicon vias (TSVs).
    Type: Application
    Filed: September 13, 2011
    Publication date: January 5, 2012
    Applicant: QUALCOMM INCORPORATED
    Inventors: Jonghae Kim, Shiqun Gu, Brian Matthew Henderson, Thomas R. Toms, Matthew Nowak
  • Patent number: 8089073
    Abstract: This invention provides thin film devices that have been processed on their front- and backside. The devices include an active layer that is sufficiently thin to be mechanically flexible. Examples of the devices include back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.
    Type: Grant
    Filed: September 8, 2010
    Date of Patent: January 3, 2012
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Paul G. Evans, Max G. Lagally, Zhenqiang Ma, Hao-Chih Yuan, Guogong Wang, Mark A. Eriksson
  • Publication number: 20110284869
    Abstract: A high voltage durability III-nitride semiconductor device comprises a support substrate including a first silicon body, an insulator body over the first silicon body, and a second silicon body over the insulator body. The high voltage durability III-nitride semiconductor device further comprises a III-nitride semiconductor body characterized by a majority charge carrier conductivity type, formed over the second silicon body. The second silicon body has a conductivity type opposite the majority charge carrier conductivity type. In one embodiment, the high voltage durability III-nitride semiconductor device is a high electron mobility transistor (HEMT) comprising a support substrate including a <100> silicon layer, an insulator layer over the <100> silicon layer, and a P type conductivity <111> silicon layer over the insulator layer.
    Type: Application
    Filed: August 3, 2011
    Publication date: November 24, 2011
    Inventor: Michael A. Briere
  • Publication number: 20110233783
    Abstract: In an embodiment, a substrate arrangement is provided. The substrate arrangement may include a semiconductor substrate including a first contact portion and a second contact portion on a first surface of the semiconductor substrate, wherein the semiconductor substrate is arranged such that the first contact portion and the second contact portion face each other. The substrate arrangement may further include an electrical connector configured to connect the first contact portion and the second contact portion.
    Type: Application
    Filed: August 26, 2008
    Publication date: September 29, 2011
    Applicant: SIEMENS MEDICAL INSTRUMENTS PTE. LTD.
    Inventors: Hock Peng Lim, Meng Kiang Lim
  • Patent number: 8026545
    Abstract: An EEPROM according to the present invention includes: a semiconductor layer of a first conductive type; and a first insulating film formed on the semiconductor layer. A first impurity region, a second impurity region, a third impurity region, a fourth impurity region, and a fifth impurity region of a second conductive type are formed in top layer portions of the semiconductor layer. On the first insulating film, a select gate, a first floating gate, and a second floating gate are respectively disposed opposite a region between the first impurity region and the second impurity region, a region between the second impurity region and the third impurity region, and a region between the third impurity region and the fourth impurity region. In the first insulating film, a first tunnel window and a second tunnel window are respectively formed at portions in contact with the first floating gate and the second floating gate.
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: September 27, 2011
    Assignee: Rohm Co., Ltd.
    Inventor: Yushi Sekiguchi
  • Patent number: 8018008
    Abstract: A semiconductor device includes a first chip and a second chip. The first chip includes a first conductivity type channel power MOSFET. The second chip includes a second conductivity type channel power MOSFET. The first chip and the second chip are integrated in such a manner that a second-surface drain electrode of the first chip and a second-surface drain electrode of the second chip face to each other and are electrically coupled with each other through a conductive material.
    Type: Grant
    Filed: April 21, 2009
    Date of Patent: September 13, 2011
    Assignee: DENSO CORPORATION
    Inventor: Shoji Ozoe
  • Patent number: 8008667
    Abstract: A semiconductor device includes a first semiconductor layer and a first semiconductor element located in the first semiconductor layer. The semiconductor device also includes a second semiconductor layer of a transparent semiconductor material. The second semiconductor layer is disposed on the first semiconductor layer covering the first semiconductor element. The semiconductor device also includes a second semiconductor element located in the second semiconductor layer. The semiconductor device also includes a wire extending within the second semiconductor layer and electrically connecting the first and second semiconductor elements.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: August 30, 2011
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hidetoshi Koyama, Yoshitaka Kamo
  • Publication number: 20110180902
    Abstract: In a reverse conducting IGBT, diode cathode regions are formed dispersedly on the back side of a device chip. When the distribution density of the diode cathode region becomes low, VF of a fly-back diode, that is, a forward voltage drop becomes large. On the other hand, when the distribution density of the diode cathode region becomes high, it becomes hard for a PN junction at a collector part to turn ON and a snap back occurs. In contrast to this, there is a method of providing about one to several diode cathode absent regions having a macro area, however, the arrangement of the regions itself directly affects the device characteristics, and therefore, it is difficult to control the device characteristics and variations thereof.
    Type: Application
    Filed: January 26, 2011
    Publication date: July 28, 2011
    Inventor: HIROSHI INAGAWA
  • Patent number: 7919814
    Abstract: As well as achieving both downsizing and thickness reduction and sensitivity improvement of a semiconductor device that has: a MEMS sensor formed by bulk micromachining technique such as an acceleration sensor and an angular rate sensor; and an LSI circuit, a packaging structure of the semiconductor device having the MEMS sensor and the LSI circuit can be simplified. An integrated circuit having MISFETs and wirings is formed on a silicon layer of an SOI substrate, and the MEMS sensor containing a structure inside is formed by processing a substrate layer of the SOI substrate. In other words, by using both surfaces of the SOI substrate, the integrated circuit and the MEMS sensor are mounted on one SOI substrate. The integrated circuit and the MEMS sensor are electrically connected to each other by a through-electrode provided in the SOI substrate.
    Type: Grant
    Filed: November 13, 2008
    Date of Patent: April 5, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Yasushi Goto, Tsukasa Fujimori, Heewon Jeong, Kiyoko Yamanaka
  • Patent number: 7915645
    Abstract: According to one disclosed embodiment, a monolithic vertically integrated composite device comprises a double sided semiconductor substrate having first and second sides, a group IV semiconductor layer formed over the first side and comprising at least one group IV semiconductor device, and a group III-V semiconductor body formed over the second side and comprising at least one group III-V semiconductor device electrically coupled to the at least one group IV semiconductor device. The composite device may further comprise a substrate via and/or a through-wafer via providing electric coupling. In one embodiment, the group IV semiconductor layer may comprise an epitaxial silicon layer, and the at least one group IV semiconductor device may be a combined FET and Schottky diode (FETKY) fabricated on the epitaxial silicon layer. In one embodiment, the at least one group III-V semiconductor device may be a III-nitride high electron mobility transistor (HEMT).
    Type: Grant
    Filed: May 28, 2009
    Date of Patent: March 29, 2011
    Assignee: International Rectifier Corporation
    Inventor: Michael A. Briere
  • Patent number: 7883972
    Abstract: A semiconductor device may include a fin structure having source/drain regions and channel fins connected between source/drain patterns. A gate insulation layer may be provided on the channel fins. A gate electrode may include lower gate patterns and an upper gate pattern. The lower gate patterns may extend in a vertical direction and contact the gate insulation layer. The upper gate pattern may extend in a second horizontal direction substantially perpendicular to the first horizontal direction. The upper gate pattern may be connected to upper portions of the lower gate patterns.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: February 8, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Man Yoon, Choong-Ho Lee, Chul Lee, Dong-Gun Park
  • Patent number: 7880293
    Abstract: A semiconductor device has a wafer for supporting the device and a conductive layer formed over a top surface of the wafer. A carrier wafer is permanently bonded over the conductive layer. Within the wafer and the carrier wafer, an interconnect structure is formed. The interconnect structure includes a first via formed in the wafer exposing the conductive layer, a second via formed in the carrier wafer exposing the conductive layer, a first metal layer deposited over the first via, the first metal layer in electrical contact with the conductive layer, and a second metal layer deposited over the second via, the second metal layer in electrical contact with the conductive layer. First and second passivation layers are deposited over the first and second metal layers. The first or second passivation layer has an etched portion to expose a portion of the first metal layer or second metal layer.
    Type: Grant
    Filed: March 25, 2008
    Date of Patent: February 1, 2011
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Byung Joon Han, Nathapong Suthiwongsunthorn, Pandi Chelvam Marimuthu, Kock Liang Heng
  • Patent number: 7868391
    Abstract: A 3-D (Three Dimensional) inverter having a single gate electrode. The single gate electrode has a first gate dielectric between the gate electrode and a body of a first FET (Field Effect transistor) of a first doping type, the first FET having first source/drain regions in a semiconductor substrate, or in a well in the semiconductor substrate. The single gate electrode has a second gate dielectric between the gate electrode and a body of a second FET of opposite doping to the first FET. Second source/drain regions of the second FET are formed from epitaxial layers grown over the first source/drain regions.
    Type: Grant
    Filed: June 4, 2009
    Date of Patent: January 11, 2011
    Assignee: International Business Machines Corporation
    Inventors: Phil Christopher Felice Paone, David P. Paulsen, John E. Sheets, II, Kelly L. Williams
  • Patent number: 7812353
    Abstract: This invention provides methods for fabricating thin film electronic devices with both front- and backside processing capabilities. Using these methods, high temperature processing steps may be carried out during both frontside and backside processing. The methods are well-suited for fabricating back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.
    Type: Grant
    Filed: March 4, 2008
    Date of Patent: October 12, 2010
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Hao-Chih Yuan, Guogong Wang, Mark A. Eriksson, Paul G. Evans, Max G. Lagally, Zhenqiang Ma
  • Patent number: 7791169
    Abstract: Disclosed is a semiconductor structure that incorporates a capacitor for reducing the soft error rate of a device within the structure. The multi-layer semiconductor structure includes an insulator-filled deep trench isolation structure that is formed through an active silicon layer, a first insulator layer, and a first bulk layer and extends to a second insulator layer. The resulting isolated portion of the first bulk layer defines the first capacitor plate. A portion of the second insulator layer that is adjacent the first capacitor plate functions as the capacitor dielectric. Either the silicon substrate or a portion of a second bulk layer that is isolated by a third insulator layer and another deep trench isolation structure can function as the second capacitor plate. A first capacitor contact couples, either directly or via a wire array, the first capacitor plate to a circuit node of the device in order to increase the critical charge, Qcrit, of the circuit node.
    Type: Grant
    Filed: April 18, 2008
    Date of Patent: September 7, 2010
    Assignee: International Business Machines Corporation
    Inventors: John M. Aitken, Ethan H. Cannon, Philip J. Oldiges, Alvin W. Strong
  • Patent number: 7759711
    Abstract: Disclosed is a semiconductor device including: an N-type RESURF region formed in a P-type semiconductor substrate; a P-type base region formed in an upper portion of the semiconductor substrate so as to be adjacent to the RESURF region; an N-type emitter/source region formed in the base region so as to be apart from the RESURF region; a P-type base connection region formed in the base region so as to be adjacent to the emitter/source region; a gate insulating film and a gate electrode overlying the emitter/source region, the base region, and the RESURF region; and a P-type collector region formed in the RESURF region so as to be apart from the base region. Lattice defect is generated in the semiconductor substrate such that a resistance value of the semiconductor substrate is twice or more the resistance value of the semiconductor substrate that depends on the concentration of an impurity implanted in the semiconductor substrate.
    Type: Grant
    Filed: October 22, 2008
    Date of Patent: July 20, 2010
    Assignee: Panasonic Corporation
    Inventors: Kazuyuki Sawada, Yuji Harada, Masahiko Niwayama, Saichirou Kaneko, Yoshimi Shimizu
  • Patent number: 7755180
    Abstract: An integrated circuit package-in-package system is provided forming a first integrated circuit package having a first interface, stacking a second integrated circuit package having a second interface above the first integrated circuit package, fitting the first interface and the second interface, and attaching a third integrated circuit package on the second integrated circuit package.
    Type: Grant
    Filed: September 20, 2007
    Date of Patent: July 13, 2010
    Assignee: Stats Chippac Ltd.
    Inventors: Choong Bin Yim, Hyeog Chan Kwon, Jong-Woo Ha
  • Patent number: 7723851
    Abstract: A method of forming a high aspect ratio via opening through multiple dielectric layers, a high aspect ratio electrically conductive via, methods of forming three-dimension integrated circuits, and three-dimensional integrated circuits. The methods include forming a stack of at least four dielectric layers and etching the first and third dielectric layers with processes selective to the second and fourth dielectric layers, etching the second and third dielectric layers with processes selective to the first and second dielectric layers. Advantageously the process used to etch the third dielectric layer is not substantially selective to the first dielectric layer.
    Type: Grant
    Filed: September 11, 2007
    Date of Patent: May 25, 2010
    Assignee: International Business Machines Corporation
    Inventors: Douglas C. La Tulipe, Jr., Mark Todhunter Robson
  • Patent number: 7679119
    Abstract: A single-poly electrically erasable/programmable CMOS logic memory cell for mobile applications includes a CMOS inverter that share a single polysilicon floating gate, and an enhanced control capacitor including a control gate capacitor and an optional isolated P-well (IPW) capacitor formed below the control gate capacitor. The control gate capacitor includes a polysilicon control gate that is interdigitated with the floating gate and serves as a capacitor plate to induce Fowler-Nordheim (F-N) injection or Band-to-Band Tunneling (BBT) to both program and erase the floating gate. The IPW capacitor is provided in the otherwise unused space below the control gate capacitor by a IPW that is separated from the control/floating gates by a dielectric layer and is electrically connected to the control gate. Both F-N injection and BBT program/erase are performed at 5V or less.
    Type: Grant
    Filed: November 7, 2007
    Date of Patent: March 16, 2010
    Assignee: Tower Semiconductor Ltd.
    Inventors: Yakov Roizin, Victor Kairys, Erez Sarig, David Zfira
  • Publication number: 20090073667
    Abstract: A semiconductor chip package and a printed circuit board having an embedded semiconductor chip package are disclosed. The semiconductor chip package may include a semiconductor chip that has at least one chip pad formed on one side, and a capacitor formed on the other side of the semiconductor chip.
    Type: Application
    Filed: September 5, 2008
    Publication date: March 19, 2009
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Yul-Kyo Chung, Sung Yi, Soon-Gyu Yim, Seog-Moon Choi, Jin-Gu Kim, Young-Do Kweon
  • Publication number: 20080315356
    Abstract: According to an exemplary embodiment, a semiconductor die includes a backside surface opposite an active surface. The active surface includes at least one active device. The semiconductor die includes at least one passive device situated on the backside surface. The semiconductor die further includes an interconnect region situated over the active surface. The semiconductor die further includes at least one through-wafer via, where the at least one through-wafer via electrically connects the at least one passive device to the interconnect region. The interconnect region can include a number of solder bump pads or a number of bond pads.
    Type: Application
    Filed: June 6, 2008
    Publication date: December 25, 2008
    Applicant: SKYWORKS SOLUTIONS, INC.
    Inventor: Russ Reisner
  • Publication number: 20080203526
    Abstract: A plurality of wirings, column-shaped electrodes, sealing films, and soldering balls, are provided on a third upper-layer insulating film formed on a silicon substrate. A spirally configured thin-film inductive element is disposed beneath the bottom surface of a ground insulating film formed beneath the silicon substrate. The inner and outer end portions of the thin-film inductive element are respectively connected to the wirings via a vertical conductor disposed in the silicon substrate. In this case, it is not required to secure a certain area otherwise needed for the formation of the thin-film inductive element over the surface of the third upper-layer insulating film that accommodates the wirings. Hence, even when the thin-film inductive element has been provided, it is possible to evade a feasibility to incur restraint on the distribution of the wirings formed over the surface of the third upper-layer insulating film.
    Type: Application
    Filed: February 25, 2008
    Publication date: August 28, 2008
    Applicant: Casio Computer Co., Ltd.
    Inventor: Ichiro Mihara