With Semiconductor Substrate Only (epo) Patents (Class 257/E27.01)

  • Patent number: 8975132
    Abstract: A semiconductor device with an isolation layer buried in a trench includes an interface layer formed on the surface of the trench, a buffer layer formed in the interface layer at a bottom corner of the trench, a liner layer formed over the interface layer, and a gap-fill layer gap-filling the trench over the liner layer. The trench includes a micro-trench formed at the bottom corner thereof, and the buffer layer fills the micro-trench.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: March 10, 2015
    Assignee: SK Hynix Inc.
    Inventors: Hyung-Hwan Kim, Bong-Ho Choi, Jin-Yul Lee, Seung-Seok Pyo
  • Patent number: 8860146
    Abstract: According to one embodiment, a semiconductor device including a field-effect transistor, and a resistance element connected between a gate electrode of the field effect transistor and a connection point connected between a back gate electrode of the field effect transistor and one of source-drain regions of the field effect transistor, a voltage being applied between the other of the source-drain regions and the gate electrode.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: October 14, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuki Nakamura, Takehito Ikimura
  • Patent number: 8853833
    Abstract: Semiconductor devices are described, along with methods and systems that include them. One such device includes a diffusion region in a semiconductor material, a terminal coupled to the diffusion region, and a field plate coupled to the terminal and extending from the terminal over the diffusion region to shield the diffusion region. Additional embodiments are also described.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: October 7, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Vladimir Mikhalev, Michael Smith, Henry J. Fulford, Puneet Sharma, Zia A. Shafi
  • Patent number: 8815698
    Abstract: A well region formation method and a semiconductor base in the field of semiconductor technology are provided. A method comprises: forming isolation regions in a semiconductor substrate to isolate active regions; selecting at least one of the active regions, and forming a first well region in the selected active region; forming a mask to cover the selected active region, and etching the rest of the active regions, so as to form grooves; and growing a semiconductor material by epitaxy to fill the grooves. Another method comprises: forming isolation regions in a semiconductor substrate for isolating active regions; forming well regions in the active regions; etching the active regions to form grooves, such that the grooves have a depth less than or equal to a depth of the well regions; and growing a semiconductor material by epitaxy to fill the grooves.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: August 26, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Haizhou Yin, Huilong Zhu, Zhijiong Luo
  • Patent number: 8786047
    Abstract: A semiconductor device with an isolation layer buried in a trench includes an interface layer formed on the surface of the trench, a buffer layer formed in the interface layer at a bottom corner of the trench, a liner layer formed over the interface layer, and a gap-fill layer gap-filling the trench over the liner layer. The trench includes a micro-trench formed at the bottom corner thereof, and the buffer layer fills the micro-trench.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: July 22, 2014
    Assignee: SK Hynix Inc.
    Inventors: Hyung-Hwan Kim, Bong-Ho Choi, Jin-Yul Lee, Seung-Seok Pyo
  • Patent number: 8785980
    Abstract: A semiconductor memory device includes a memory cell array layer which includes a first wiring line, a memory cell stacked on the first wiring line, and a second wiring line formed on the memory cell so as to intersect the first wiring line, wherein a step is formed in the first wiring line so that the height of an upper surface of the first wiring line in the memory cell array region where the memory cell array is formed is higher than the height in a peripheral region around the memory cell array region.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: July 22, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoya Osaki, Naohito Morozumi
  • Patent number: 8735986
    Abstract: A substrate includes a first region having a first resistivity, for optimizing a field effect transistor, a second region having a second resistivity, for optimizing an npn subcollector of a bipolar transistor device and triple well, a third region having a third resistivity, with a high resistivity for a passive device, a fourth region, substantially without implantation, to provide low perimeter capacitance for devices.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: May 27, 2014
    Assignee: International Business Machines Corporation
    Inventors: Alan B. Botula, Renata Camillo-Castillo, James S. Dunn, Jeffrey P. Gambino, Douglas B. Hershberger, Alvin J. Joseph, Robert M. Rassel, Mark E. Stidham
  • Publication number: 20140103488
    Abstract: A device includes a top package bonded to a bottom package. The bottom package includes a molding material, a device die molded in the molding material, a Through Assembly Via (TAV) penetrating through the molding material, and a redistribution line over the device die. The top package includes a discrete passive device packaged therein. The discrete passive device is electrically coupled to the redistribution line.
    Type: Application
    Filed: October 11, 2012
    Publication date: April 17, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsu-Hsien Chen, Chih-Hua Chen, En-Hsiang Yeh, Monsen Liu, Chen-Shien Chen
  • Patent number: 8698203
    Abstract: A semiconductor device includes a semiconductor layer having a plurality of active regions that are separated by element isolation grooves, a capacitive film having a sidewall covering portion covering a sidewall of the element isolation grooves, and an electrode film laminated on the capacitive film, and a capacitor element is formed by the semiconductor layer, the capacitive film and the electrode film.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: April 15, 2014
    Assignee: Rohm Co., Ltd.
    Inventor: Bungo Tanaka
  • Patent number: 8698205
    Abstract: An integrated circuit layout having a mixed track standard cell configuration that having a mixed track standard cell configuration that includes first well regions of a predetermined height and second well regions of a predetermined height, the first and second well regions are arranged within a substrate, first conductors and second conductors arranged and extending across regions of corresponding first and second well regions, and a plurality of standard cells in multiple rows. The standard cells include a first substantially equal to standard cell having a first cell height substantially equal to I(X+Y)+X or Y, wherein X is one half the predetermined height of the first well region, Y is one half the predetermined height of the second well region, and I is a positive integer.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: April 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiann-Tyng Tzeng, Chih-Liang Chen, Yi-Feng Chen, Kam-Tou Sio, Shang-Chih Hsieh, Helen Shu-Hui Chang
  • Publication number: 20140071566
    Abstract: In one embodiment, an apparatus includes a package that encompasses at least a first integrated circuit die and a second integrated circuit die. The first integrated circuit die is attached to the package and includes one or more electrical overstress/electrostatic discharge (EOS/ESD) protection circuits. The second integrated circuit die is attached to the package and electrically coupled to the first integrated circuit die such that at least one component of the second integrated circuit die is protected from EOS/ESD by the first integrated circuit die.
    Type: Application
    Filed: September 11, 2012
    Publication date: March 13, 2014
    Applicant: ANALOG DEVICES, INC.
    Inventors: Srivatsan PARTHASARATHY, Charly EL-KHOURY, Francisco SANTOS, Nathan R. Carter
  • Publication number: 20140027819
    Abstract: A corner layout for a semiconductor device that maximizes the breakdown voltage is disclosed. The device includes first and second subsets of the striped cell arrays. The ends of each striped cell in the first array is spaced a uniform distance from the nearest termination device structure. In the second subset, the ends of striped cells proximate a corner of the active cell region are configured to maximize breakdown voltage by spacing the ends of each striped cell a non-uniform distance from the nearest termination device structure. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Application
    Filed: July 30, 2012
    Publication date: January 30, 2014
    Applicant: Alpha and Omega Semiconductor Incorporated
    Inventors: Lingpeng Guan, Anup Bhalla
  • Patent number: 8614482
    Abstract: A improved termination structure for semiconductor power devices is disclosed, comprising a trenched field plate formed not only along trench sidewall but also on trench bottom of the wide termination trench by doing poly-silicon CMP so that body ion implantation is blocked by the trenched field plate on the trench bottom to prevent a body region formation underneath the trench bottom of the wide termination trench, degrading avalanche voltage.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: December 24, 2013
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Publication number: 20130299848
    Abstract: In one embodiment, a semiconductor package includes a vertical semiconductor chip having a first major surface on one side of the vertical semiconductor chip and a second major surface on an opposite side of the vertical semiconductor chip. The first major surface includes a first contact region and the second major surface includes a second contact region. The vertical semiconductor chip is configured to regulate flow of current from the first contact region to the second contact region along a current flow direction. A back side conductor is disposed at the second contact region of the second major surface. The semiconductor package further includes a first encapsulant in which the vertical semiconductor chip and the back side conductor are disposed.
    Type: Application
    Filed: May 14, 2012
    Publication date: November 14, 2013
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Edward Fuergut, Joachim Mahler, Khalil Hosseini, Hans-Joerg Timme
  • Publication number: 20130292772
    Abstract: An approach for providing layout designs with via routing structures is disclosed. Embodiments include: providing a gate structure and a diffusion contact on a substrate; providing a gate contact on the gate structure; providing a metal routing structure that does not overlie a portion of the gate contact, the diffusion contact, or a combination thereof; and providing a via routing structure over the portion and under a part of the metal routing structure to couple the gate contact, the diffusion contact, or a combination thereof to the metal routing structure.
    Type: Application
    Filed: May 7, 2012
    Publication date: November 7, 2013
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Yuansheng Ma, Jongwook KYE, Harry LEVINSON, Hidekazu YOSHIDA, Mahbub RASHED
  • Publication number: 20130277797
    Abstract: A method for manufacturing an electronic device and an electronic device are disclosed. In an embodiment the method comprises forming an opening in an isolation layer, isotropically etching the opening thereby forming an extended opening with curved sidewalls, and forming a conductive material in the opening.
    Type: Application
    Filed: April 20, 2012
    Publication date: October 24, 2013
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Markus Menath, Thomas Fischer, Hermann Wendt
  • Patent number: 8552522
    Abstract: A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming patterned features over the semiconductor substrate, wherein gaps are formed between the patterned features; filling the gaps with a first filling material, wherein the first filling material has a first top surface higher than top surfaces of the patterned features; and performing a first planarization to lower the top surface of the first filling material, until the top surfaces of the patterned features are exposed. The method further includes depositing a second filling material, wherein the second filling material has a second top surface higher than the top surfaces of the patterned features; and performing a second planarization to lower the top surface of the second filling material, until the top surfaces of the patterned features are exposed.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: October 8, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Yuan Wu, Kong-Beng Thei, Chiung-Han Yeh, Harry Chuang, Mong-Song Liang
  • Publication number: 20130256833
    Abstract: A triple well isolate diode including a substrate having a first conductivity type and a buried layer formed in the substrate, where the buried layer has a second conductivity type. The triple well isolated diode including an epi-layer formed over the substrate and the buried layer, where the epi-layer has the first conductivity type. The triple well isolated diode including a first well formed in the epi-layer, where the first well has the second conductivity type, a second well formed in the epi-layer, where the second well has the first conductivity type and surrounds the first well, a third well formed in the epi-layer, where the third well has the second conductivity type and surrounds the second well. The triple well isolated diode including a deep well formed in the epi-layer, where the deep well has the first conductivity type and extends beneath the first well.
    Type: Application
    Filed: April 3, 2012
    Publication date: October 3, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chang CHENG, Fu-Yu CHU, Ruey-Hsin LIU
  • Publication number: 20130257489
    Abstract: Apparatuses and methods are described that include a plurality of drivers corresponding to a single via. A number of drivers can be selected to operate individually or together to drive a signal through a single via. Additional apparatus and methods are described.
    Type: Application
    Filed: March 27, 2012
    Publication date: October 3, 2013
    Inventor: Feng Lin
  • Publication number: 20130249048
    Abstract: A semiconductor device with an isolation layer buried in a trench includes an interface layer formed on the surface of the trench, a buffer layer formed in the interface layer at a bottom corner of the trench, a liner layer formed over the interface layer, and a gap-fill layer gap-filling the trench over the liner layer. The trench includes a micro-trench formed at the bottom corner thereof, and the buffer layer fills the micro-trench.
    Type: Application
    Filed: July 9, 2012
    Publication date: September 26, 2013
    Inventors: Hyung-Hwan KIM, Bong-Ho CHOI, Jin-Yul LEE, Seung-Seok PYO
  • Publication number: 20130241026
    Abstract: A device including a first layer of first transistors interconnected by at least one first interconnection layer, wherein the first interconnection layer includes copper or aluminum, a second layer including second transistors, the second layer overlaying the first interconnection layer, wherein the second layer is less than 2 micron thick, wherein the second layer has a coefficient of thermal expansion; and a connection path connecting at least one of the second transistors to the first interconnection layer, wherein the connection path includes at least one through-layer via, and wherein the through-layer via includes material whose co-efficient of thermal expansion is within 50 percent of the second layer coefficient of thermal expansion.
    Type: Application
    Filed: March 17, 2012
    Publication date: September 19, 2013
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Publication number: 20130228892
    Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate, isolation regions disposed in the semiconductor substrate, and device regions disposed between the isolation regions in the semiconductor substrate. The device further includes a first line disposed on the device regions and the isolation regions, a line width of the first line on the isolation regions being larger than a line width of the first line on the device regions.
    Type: Application
    Filed: August 21, 2012
    Publication date: September 5, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Shinya ARAI
  • Publication number: 20130207163
    Abstract: Semiconductor devices and manufacturing methods thereof are disclosed. In one embodiment, a semiconductor device includes a workpiece with a first region having a plurality of first features and a second region having a plurality of second features proximate the first region. The first region and the second region share a patterning overlap region disposed between the first region and the second region. The patterning overlap region includes a residue feature with an aspect ratio of about 4 or less.
    Type: Application
    Filed: February 9, 2012
    Publication date: August 15, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chang Chen, Shun-Shing Yang, Shih-Chi Fu, Wang-Pen Mo, Hung-Chang Hsieh
  • Patent number: 8507332
    Abstract: A method for manufacturing components on a mixed substrate. The method comprises the following steps: providing a substrate of the semiconductor-on-insulator (SeOI) type comprising a buried oxide layer between a supporting substrate and a thin layer, forming in this substrate a plurality of trenches opening out at a free surface of the thin layer and extending over a depth such that each trench passes through the thin layer and the buried oxide layer, these primary trenches delimiting at least one island of the SeOI substrate, forming a mask inside the primary trenches and as a layer covering the areas of the free surface of the thin layer located outside the islands, proceeding with heat treatment for dissolving the buried oxide layer present at the island, so as to reduce the thickness thereof.
    Type: Grant
    Filed: February 11, 2010
    Date of Patent: August 13, 2013
    Assignee: Soitec
    Inventors: Gregory Riou, Didier Landru
  • Publication number: 20130193512
    Abstract: A semiconductor device arrangement includes a semiconductor layer and at least one series circuit with a first semiconductor device and a plurality of n second semiconductor devices, with n>1. The first semiconductor device has a load path and active device regions integrated in the semiconductor layer. Each second semiconductor device has active device regions integrated in the semiconductor layer and a load path between a first and second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each second semiconductor device has its control terminal connected to the load terminal of one of the other second semiconductor devices. One of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. The arrangement further includes an edge termination structure.
    Type: Application
    Filed: January 31, 2012
    Publication date: August 1, 2013
    Applicant: INFINEON TECHNOLOGIES DRESDEN GMBH
    Inventor: Rolf Weis
  • Patent number: 8492801
    Abstract: A semiconductor structure with high breakdown voltage and high resistance and method for manufacturing the same. The semiconductor structure at least comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate; two first wells having the first conductive type and formed within the deep well; a second well having the first conductive type and formed between the two first wells within the deep well, and an implant dosage of the second well lighter than an implant dosage of each of the two first wells; and two first doping regions having the first conductive type and respectively formed within the two first wells.
    Type: Grant
    Filed: May 11, 2007
    Date of Patent: July 23, 2013
    Assignee: System General Corp.
    Inventors: Chiu-Chih Chiang, Chih-Feng Huang
  • Publication number: 20130161781
    Abstract: A semiconductor device and a method for manufacturing the same are disclosed, which can improve device characteristics by increasing a process margin between an active region and a storage node contact. The semiconductor device includes an active region, a device isolation film formed to have a lower height than the active region, and exposing an upper part of the active region, and a barrier pattern formed at a sidewall of the exposed active region of an upper part of the device isolation film.
    Type: Application
    Filed: May 17, 2012
    Publication date: June 27, 2013
    Applicant: SK Hynix Inc.
    Inventor: Seong Eun LEE
  • Publication number: 20130162331
    Abstract: A diode string voltage adapter includes diodes formed in a substrate of a first conductive type. Each diode includes a deep well region of a second conductive type formed in the substrate. A first well region of the first conductive type formed on the deep well region. A first heavily doped region of the first conductive type formed on the first well region. A second heavily doped region of the second conductive type formed on the first well region. The diodes are serially coupled to each other. A first heavily doped region of a beginning diode is coupled to a first voltage. A second heavily doped region of each diode is coupled to a first heavily doped region of a next diode. A second heavily doped region of an ending diode provides a second voltage. The deep well region is configured to be electrically floated.
    Type: Application
    Filed: December 23, 2011
    Publication date: June 27, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Peng HSIEH, Jaw-Juinn HORNG
  • Publication number: 20130146957
    Abstract: A memory device including an SOI substrate with a buried dielectric layer having a thickness of less than 30 nm, and a trench extending through an SOI layer and the buried dielectric layer into the base semiconductor layer of the SOI substrate. A capacitor is present in a lower portion of the trench. A dielectric spacer is present on the sidewalls of an upper portion of the trench. The dielectric spacer is present on the portions of the trench where the sidewalls are provided by the SOI layer and the buried dielectric layer. A conductive material fill is present in the upper portion of the trench. A semiconductor device is present on the SOI layer that is adjacent to the trench. The semiconductor device is in electrical communication with the capacitor through the conductive material fill.
    Type: Application
    Filed: December 9, 2011
    Publication date: June 13, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Joseph Ervin, Chengwen Pei, Ravi M. Todi, Geng Wang
  • Publication number: 20130147013
    Abstract: A semiconductor device comprises a conductor film and a capacitor comprising a lower electrode provided on the conductor film. The conductor film includes a first conductive film containing a first metal, a second conductive film containing a second metal on the first conductive film, and an oxide film of the second metal on the second conductive film. The oxide film of the second metal has a lower electric resistivity than an oxide film of the first metal.
    Type: Application
    Filed: November 8, 2012
    Publication date: June 13, 2013
    Applicant: Elpida Memory, Inc.
    Inventor: Elpida Memory, Inc.
  • Publication number: 20130140668
    Abstract: A substrate includes a first region having a first resistivity, for optimizing a field effect transistor, a second region having a second resistivity, for optimizing an npn subcollector of a bipolar transistor device and triple well, a third region having a third resistivity, with a high resistivity for a passive device, a fourth region, substantially without implantation, to provide low perimeter capacitance for devices.
    Type: Application
    Filed: December 6, 2011
    Publication date: June 6, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alan B. Botula, Renata Camillo-Castillo, James S. Dunn, Jeffrey P. Gambino, Douglas B. Hershberger, Alvin J. Joseph, Mark E. Stidham, Robert M. Rassel
  • Publication number: 20130105938
    Abstract: The present invention relates to device matching in an integrated circuit. In one embodiment, an integrated circuit of matched devices can include: N main-devices to be matched by 4×K sub-devices configured to form K device arrays, where each of the device arrays includes four sub-device groups arrayed symmetrically around a vertical axis and a horizontal axis, where each of the sub-device groups includes N sub-devices arrayed with equal distance along a direction of the vertical axis, where K and N are integers, and N is larger than two; metal lead wires arrayed in parallel and with equal distance, and configured to connect the main-devices; a common connecting wire configured to connect common nodes of the sub-devices together; and where four sub-devices arrayed in the four sub-device groups, and other sub-devices arrayed in other sub-device groups, are coupled to form 4×K sub-devices to match the main-devices.
    Type: Application
    Filed: October 2, 2012
    Publication date: May 2, 2013
    Applicant: SILERGY SEMICONDUCTOR TECHNOLOGY (HANGZHOU) LTD
    Inventor: Silergy Semiconductor Technology (Hangzhou)
  • Publication number: 20130093040
    Abstract: A semiconductor structure and method for forming a shallow trench isolation (STI) structure having one or more oxide layers and a nitride plug. Specifically, the structure and method involves forming one or more trenches in a substrate. The STI structure is formed having one or more oxide layers and a nitride plug, wherein the STI structure is formed on and adjacent to at least one of the one or more trenches. One or more gates are formed on the substrate and spaced at a distance from each other. A dielectric layer is formed on and adjacent to the substrate, the STI structure, and the one or more gates.
    Type: Application
    Filed: October 18, 2011
    Publication date: April 18, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Byeong Y. Kim, Shreesh Narasimha
  • Publication number: 20130082235
    Abstract: A monolithic three dimensional integrated circuit device includes a first layer having first active devices. The monolithic three dimensional integrated circuit device also includes a second layer having second active devices that each include a graphene portion. The second layer can be fabricated on the first layer to form a stack of active devices. A base substrate may support the stack of active devices.
    Type: Application
    Filed: October 4, 2012
    Publication date: April 4, 2013
    Applicant: Qualcomm Incorporated
    Inventor: Qualcomm Incorporated
  • Publication number: 20130062724
    Abstract: A power module includes a semiconductor chip, a first coupling conductor with one main surface coupled to one main surface of the semiconductor chip, a second coupling conductor with one main surface coupled to the other main surface of the semiconductor chip, a coupling terminal supplied with electrical power from the direct current power source, and resin material to seal the semiconductor chip, and in which the resin member has a protruding section that protrudes from the space where the first and second coupling conductors are formed opposite each other, and the coupling terminal is clamped on the protruding section, and at least one of the first or second coupling conductors is coupled to a coupling terminal by way of a metallic material that melts at a specified temperature.
    Type: Application
    Filed: March 30, 2011
    Publication date: March 14, 2013
    Inventors: Takeshi Tokuyama, Kinya Nakatsu, Toshiya Satoh, Hideaki Ishikawa
  • Publication number: 20130062699
    Abstract: A semiconductor device and a method for manufacturing the same are disclosed. In one embodiment, the semiconductor device may comprise a semiconductor layer, a fin formed by patterning the semiconductor layer, and a gate stack crossing over the fin. The fin may comprise a doped block region at the bottom portion thereof. According to the embodiment, it is possible to effectively suppress current leakage at the bottom portion of the fin by the block region.
    Type: Application
    Filed: November 25, 2011
    Publication date: March 14, 2013
    Inventors: Huilong Zhu, Zhijiong Luo, Haizhou Yin
  • Publication number: 20130056850
    Abstract: To provide a semiconductor device featuring reduced variation in capacitor characteristics. In the semiconductor device, a protective layer is provided at the periphery of the upper end portion of a recess (hole). This protective layer has a dielectric constant higher than that of an insulating layer placed in the same layer as the protective layer and configuring a multilayer wiring layer placed in a logic circuit region.
    Type: Application
    Filed: August 23, 2012
    Publication date: March 7, 2013
    Inventors: Ippei KUME, Kenichiro Hijioka, Naoya Inoue, Hiroyuki Kunishima, Manabu Iguchi, Hiroki Shirai
  • Publication number: 20130056798
    Abstract: As technology scales, the mask cost rises sharply. It was generally believed that three-dimensional mask-programmed read-only memory (3D-MPROM) would become economically un-viable. The present invention discloses a three-dimensional printed memory (3D-P). It is a type of 3D-MPROM and uses shared data-masks to print data. By forming the mask-patterns for a plurality of distinct mass-contents on a same data-mask, the share of the data-mask cost on each mass-content is significantly reduced. For mass publication, the minimum feature size of the 3D-P is preferably less than 45 nm.
    Type: Application
    Filed: August 8, 2012
    Publication date: March 7, 2013
    Applicant: CHENGDU HAICUN IP TECHNOLOGY LLC
    Inventor: Guobiao ZHANG
  • Publication number: 20130056799
    Abstract: A simulation method of a circuit in which a transistor is formed of a material (e.g., SiGe, etc.) having a lattice constant different from that of a semiconductor substrate, on source and drain regions, an adjacent active region is formed near the transistor, and a gate electrode is formed in the active region, where a region not overlapping with the gate electrode in the adjacent active region is formed of a material such as SiGe, includes a step of calculating an electrical characteristic (e.g., flowing current, threshold voltage, etc.) of the transistor based on a distance between an edge closer to the transistor, of both edges of the adjacent active region disposed near the transistor, and the gate electrode formed in the adjacent active region. Thus, circuit simulation can be performed with high accuracy with respect to an electrical characteristic of the transistor.
    Type: Application
    Filed: November 2, 2012
    Publication date: March 7, 2013
    Applicant: PANASONIC CORPORATION
    Inventor: PANASONIC CORPORATION
  • Patent number: 8389976
    Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may comprise forming a channel region on a substrate, wherein the channel region comprises at least one CNT, forming at least one source/drain region adjacent the channel region, and then forming a gate electrode on the channel region, wherein a width of the gate electrode comprises about 50 percent to about 90 percent of a width of the contact region.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: March 5, 2013
    Assignee: Intel Corporation
    Inventors: Arijit Raychowdhury, Ali Keshavarzi, Juanita Kurtin, Vivek De
  • Publication number: 20130049845
    Abstract: An apparatus, system, and method are provided for a differential integrated input circuit. The apparatus includes n-type semiconductor devices and p-type semiconductor devices. The p-type semiconductor devices are cross-coupled with the n-type semiconductor devices. Each of the p-type semiconductor devices biases a corresponding n-type semiconductor device.
    Type: Application
    Filed: August 26, 2011
    Publication date: February 28, 2013
    Applicant: NXP B.V.
    Inventors: Aloysius Johannes Maria Boomkamp, Stefan Butselaar, Ben Gelissen, Mehdi El Ghorba, Cornelis Klaas Waardenburg
  • Publication number: 20130043509
    Abstract: A non-volatile memory device according to an aspect of the present disclosure includes a substrate, a plurality of word lines stacked over the substrate and having a stepwise pattern, wherein the plurality of word lines each have a pad region, and a plurality of contact plugs coupled to the respective pad regions of the word lines, wherein a width of a pad region of a first one of the plurality of word lines is greater than a width of a pad region of a second word line lower than the first word line.
    Type: Application
    Filed: August 16, 2012
    Publication date: February 21, 2013
    Inventors: Sung Yoon CHO, Hae Jung LEE, Byung Soo PARK, Eun Mi KIM
  • Publication number: 20130043531
    Abstract: A semiconductor device is disclosed having vertically stacked (also referred to as vertically offset) transistors in a semiconductor fin. The semiconductor fin may include lower transistors separated by a first trench and having a source and drain in a first doped region of the fin. The semiconductor fin also includes upper transistors vertically offset from the first transistors and separated by a second trench and having a source and drain in a second doped region of the fin. Upper and lower stacked gates may be disposed on the sidewalls of the fin, such that the lower transistors are activated by biasing the lower gates and upper transistors are activated by biasing the upper gates. Methods of manufacturing and operating the device are also disclosed.
    Type: Application
    Filed: October 22, 2012
    Publication date: February 21, 2013
    Applicant: Micron Technology, Inc.
    Inventor: Micron Technology, Inc.
  • Patent number: 8369144
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate including a device region which is isolated by a device isolation film, a first conductive layer provided on the device region via a gate insulation film, an inter-gate insulation film provided on the first conductive layer and including an opening on the first conductive layer, a second conductive layer disposed over the device region and the device isolation film via the inter-gate insulation film, a third conductive layer provided on the first conductive layer, isolated from the second conductive layer by a peripheral trench, and connected to the first conductive layer via the opening of the inter-gate insulation film, and source/drain diffusion layers provided, spaced apart, in the device region in a manner to sandwich the first conductive layer.
    Type: Grant
    Filed: September 18, 2011
    Date of Patent: February 5, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kikuko Sugimae, Hiroyuki Kutsukake
  • Publication number: 20130026542
    Abstract: A semiconductor device includes a semiconductor layer having a plurality of active regions that are separated by element isolation grooves, a capacitive film having a sidewall covering portion covering a sidewall of the element isolation grooves, and an electrode film laminated on the capacitive film, and a capacitor element is formed by the semiconductor layer, the capacitive film and the electrode film.
    Type: Application
    Filed: July 26, 2012
    Publication date: January 31, 2013
    Applicant: ROHM CO., LTD.
    Inventor: Bungo TANAKA
  • Publication number: 20130009275
    Abstract: A semiconductor integrated circuit device includes a first standard cell and a second standard cell adjacent to the first standard cell in a first direction. An interconnect is provided to extend in the first direction to electrically connect input and output terminal portions, which extend in a second direction orthogonal to the first direction. The output terminal portion extends in a first sub-direction of the second direction from a region connected to the interconnect, but not in a second sub-direction opposite to the first sub-direction. The input terminal portion extends in a second sub-direction of the second direction from a region connected to the interconnect, but not in the first sub-direction.
    Type: Application
    Filed: September 15, 2012
    Publication date: January 10, 2013
    Applicant: Panasonic Corporation
    Inventors: Atsushi TAKAHATA, Hiroyuki Uehara
  • Publication number: 20130001649
    Abstract: A semiconductor device is disclosed, which comprises First and second inputs ports, first and second output nodes, and first and second transistors. The first transistor includes first and second diffusion regions defining a first channel region and a first gate electrode and connected to the first input port, the first diffusion region being connected to the first output node, the second diffusion region being disposed between the first diffusion region and the first input port and supplied with a first operating potential. The second transistor includes third and fourth diffusion regions defining a second channel region and a second gate electrode and connected to the second input port, the third diffusion region being supplied with the first operating potential, the fourth diffusion region being disposed between the third diffusion region and the second input port and connected to the second output node.
    Type: Application
    Filed: June 14, 2012
    Publication date: January 3, 2013
    Applicant: Elpida Memory, Inc.
    Inventors: Hiroshi SHIMIZU, Takamitsu ONDA
  • Publication number: 20130001742
    Abstract: In a semiconductor device, a first semiconductor chip includes a first circuit and a first inductor, and a second semiconductor chip includes a second circuit and chip-side connecting terminals. An interconnect substrate is placed over the first semiconductor chip and the second semiconductor chip. The interconnect substrate includes a second inductor and substrate-side connecting terminals. The second inductor is located above the first inductor. The chip-side connecting terminals and the two substrate-side connecting terminals are connected through first solder balls.
    Type: Application
    Filed: September 11, 2012
    Publication date: January 3, 2013
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Yasutaka NAKASHIBA
  • Publication number: 20120326266
    Abstract: A high-voltage semiconductor device is disclosed. The HV semiconductor device includes: a substrate; a well of first conductive type disposed in the substrate; a first doping region of second conductive type disposed in the p-well; a first isolation structure disposed in the well of first conductive type and surrounding the first doping region of second conductive type; and a first drift ring of second conductive type disposed between the first doping region of second conductive type and the first isolation structure.
    Type: Application
    Filed: June 26, 2011
    Publication date: December 27, 2012
    Inventors: Shih-Chieh Pu, Ching-Ming Lee, Wei-Lun Hsu, Chih-Chung Wang, Ke-Feng Lin
  • Publication number: 20120319230
    Abstract: Methods of forming isolation structures are disclosed. A method of forming isolation structures for an image sensor array of one aspect may include forming a dielectric layer over a semiconductor substrate. Narrow, tall dielectric isolation structures may be formed from the dielectric layer. The narrow, tall dielectric isolation structures may have a width that is no more than 0.3 micrometers and a height that is at least 1.5 micrometers. A semiconductor material may be epitaxially grown around the narrow, tall dielectric isolation structures. Other methods and apparatus are also disclosed.
    Type: Application
    Filed: June 20, 2011
    Publication date: December 20, 2012
    Inventors: Chia-Ying Liu, Keh-Chiang Ku, Wu-Zhang Yang