Including Semiconductor Component With At Least One Potential Barrier Or Surface Barrier Adapted For Rectifying, Oscillating, Amplifying, Or Switching, Or Including Integrated Passive Circuit Elements (epo) Patents (Class 257/E27.009)
  • Patent number: 10418079
    Abstract: A bit cell structure with an integrated multiplexer is disclosed. In one embodiment, a circuit includes a plurality of bit cells, e.g., first and second bit cells. The circuit further includes a multiplexer having an input coupled to a first data line associated with the first bit cell and a second input coupled to a second data line associated with a second bit cell. The circuit further includes a PMOS transistor having a gate terminal coupled to an output of the multiplexer, and further coupled between a local read bit line and a voltage source. The PMOS transistor is configured to pull the local read bit line to a logic high value responsive to a selected one of the plurality of bit cells conveying a logic low to its respectively coupled input of the multiplexer.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: September 17, 2019
    Assignee: Oracle International Corporation
    Inventor: Robert Weisenbach
  • Patent number: 9502405
    Abstract: A plurality of contact trenches are formed in a semiconductor structure. The plurality of contact trenches are formed with a contact opening width selected to result in improper contact trench formation in a random number of the plurality of contact trenches. Devices are formed from the semiconductor structure using the plurality of contact trenches, wherein devices formed with improperly formed contact trenches are defective and devices formed with properly formed contact trenches are not defective. One or more measurements are performed to determine which devices are defective and which devices are not defective. The results of the measuring step represent a unique authentication code for an integrated circuit in which the devices are formed. Advantageously, the unique authentication code represents a physically unclonable function.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: November 22, 2016
    Assignee: International Business Machines Corporation
    Inventors: Qing Cao, Kangguo Cheng, Zhengwen Li, Fei Liu
  • Patent number: 9041122
    Abstract: Provided are a semiconductor device and a method of manufacturing the semiconductor device. In order to improve reliability by solving a problem of conductivity that may occur when an air spacer structure that may reduce a capacitor coupling phenomenon between a plurality of conductive lines is formed, there are provided a semiconductor device including: a substrate having an active region; a contact plug connected to the active region; a landing pad spacer formed to contact a top surface of the contact plug; a contact conductive layer formed to contact the top surface of the contact plug and formed in a space defined by the landing pad spacer; a metal silicide layer formed on the contact conductive layer; and a landing pad connected to the contact conductive layer in a state in which the metal silicide layer is disposed between the landing pad and the contact conductive layer, and a method of manufacturing the semiconductor device.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: May 26, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-seok Yoo, Young-seok Kim, Han-jin Lim, Jeon-Il Lee
  • Patent number: 9041162
    Abstract: A wafer includes a plurality of chips, each of the chips being spaced from each other by kerf-line regions including a reduced width.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: May 26, 2015
    Assignee: Infineon Technologies AG
    Inventors: Giuseppe Miccoli, Bhaskaran Jayachandran, Friedrich Steffen, Alfred Vater
  • Patent number: 9035425
    Abstract: A semiconductor integrated circuit includes a substrate, a multi-gate transistor device formed on the substrate, and an n-well resistor formed in the substrate. The substrate includes a plurality of first isolation structures and at least a second isolation structure formed therein. A depth of the first isolation structures is smaller than a depth of the second isolation structure. The multi-gate transistor device includes a plurality of fin structures, and the fin structures are parallel with each other and spaced apart from each other by the first isolation structures. The n-well resistor includes at least one first isolation structure. The n-well resistor and the multi-gate transistor device are electrically isolated from each other by the second isolation structure.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: May 19, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Po-Chao Tsao
  • Patent number: 9018776
    Abstract: A hard mask composition includes a solvent and an aromatic ring-containing compound represented by the following Chemical Formula 1:
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: April 28, 2015
    Assignee: Cheil Industries, Inc.
    Inventors: Jee-Yun Song, Min-Soo Kim, Hwan-Sung Cheon, Seung-Bae Oh, Yoo-Jeong Choi
  • Patent number: 8969976
    Abstract: A double-sided diaphragm micro gas-preconcentrator has a micro-gas chamber which is formed by bonding an upper silicon substrate with a lower silicon substrate. One or more suspended membranes are provided on every silicon substrate. The silicon where the suspended membrane is provided is completely removed for forming a cavity. A thin-film heater is deposited on every suspended membrane. A sorptive film is coated on an inner wall of every suspended membrane. Thus, the upper and lower sides of the preconcentrator in the present invention are suspended membranes, which improve the area of the sorptive film on the diaphragm. As a result, the preconcentrating factor is improved while keeping the small heat capacity, fast heating rate, and low power consumption features of the planar diaphragm preconcentrator.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: March 3, 2015
    Assignee: University of Electronic Science and Technology of China
    Inventors: Xiaosong Du, Ze Wu, Yi Li, Yadong Jiang, Dong Qiu
  • Patent number: 8969941
    Abstract: According to an embodiment, a semiconductor device, includes a semiconductor substrate, first and second transistors. The first transistor includes a first insulating film provided on the semiconductor substrate, a first conductive film provided on the first insulating film, a second insulating film provided on the first conductive film, and a second conductive film provided on the second insulating film. The second transistor is provided to be separated from the first transistor, the second transistor including a third insulating film provided on the semiconductor substrate, a third conductive film provided on the third insulating film, a fourth insulating film provided on the third conductive film, and a fourth conductive film provided on the fourth insulating film. The third conductive film is thicker than the first conductive film, and the second transistor has a through-portion piercing the fourth insulating film to connect the third conductive film and the fourth conductive film.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: March 3, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Wataru Sakamoto
  • Patent number: 8928110
    Abstract: A dummy cell pattern includes a dummy diffusion pattern disposed within a predetermined region A; a trench isolation pattern encompassing the dummy diffusion pattern in the predetermined region A; a first dummy gate pattern disposed on the dummy diffusion pattern with two ends of the first dummy gate pattern extending above the trench isolation pattern, thereby forming overlapping areas C1 and C2; and a second dummy gate pattern directly on the trench isolation pattern forming an overlapping area C therebetween, wherein the combination of C1, C2 and C is about 5%-20% of the predetermined region A.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: January 6, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Wai-Yi Lien, Yu-Ho Chiang, Tsung-Yen Pan
  • Patent number: 8830725
    Abstract: A crystalline semiconductor Schottky barrier-like diode sandwiched between two conducting electrodes is in series with a memory element, a word line and a bit line, wherein the setup provides voltage margins greater than 1V and current densities greater than 5×106 A/cm2. This Schottky barrier-like diode can be fabricated under conditions compatible with low-temperature BEOL semiconductor processing, can supply high currents at low voltages, exhibits high on-off ratios, and enables large memory arrays.
    Type: Grant
    Filed: August 15, 2011
    Date of Patent: September 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Donald S Bethune, Kailash Gopalakrishnan, Andrew J Kellock, Rohit S Shenoy, Kumar R Virwani
  • Patent number: 8810003
    Abstract: Provided are semiconductor devices and methods of fabricating the same. The device may include lower interconnection lines, upper interconnection lines crossing the lower interconnection lines, selection elements disposed at intersections, respectively, of the lower and upper interconnection lines, and memory elements interposed between the selection elements and the upper interconnection lines, respectively. Each of the selection elements may be realized using a semiconductor pattern having a first sidewall, in which a first lower width is smaller than a first upper width, and a second sidewall, in which a second lower width is greater than a second upper width, the first and second sidewalls crossing each other.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: August 19, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byoungjae Bae, Jung-in Kim
  • Patent number: 8796813
    Abstract: A method for controlling an electrical property of a passive device during a fabrication of an integrated component includes providing a substrate, manufacturing the passive device on the substrate, measuring the electrical property of the passive device to obtain a measuring result, determining at least one layout pattern corresponding to at least one later manufacturing process by the measuring result for adjusting the electrical property of the passive device, and continuing the rest of the fabrication including the at least one later manufacturing process of the integrated component.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: August 5, 2014
    Assignee: MediaTek Inc.
    Inventors: Ming-Da Tsai, George Chien, Cheng-Chou Hung
  • Patent number: 8772880
    Abstract: A high-speed semiconductor integrated circuit device is achieved by adjusting an offset voltage. For example, dummy NMOS transistors MND1 (MND1a and MND1b) and MND2 (MND2a and MND2b) are connected to drain outputs of NMOS transistors MN1 and MN2 operated according to differential input signals Din_p and Din_n, respectively. The MND1 is arranged adjacent to the MN1, and a source of the MND1a and a drain of the MN1 share a diffusion layer. The MND2 is arranged adjacent to the MN2, and a source of the MND2a and a drain of the MN2 share a diffusion layer. The MND1 and the MND2 function as dummy transistors for suppressing variations in process of the MN1 and the MN2 and, and besides, they also function as means for adjusting the offset voltage by appropriately applying an offset-amount setting signal OFST to each gate to provide a capacitor to either the MN1 or the MN2.
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: July 8, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Koji Fukuda, Hiroki Yamashita
  • Patent number: 8742570
    Abstract: This disclosure provides systems, methods and apparatus for manufacturing display devices having electronic components mounted within a display device package. In one aspect, the electronic component connects to the exterior of the display device through pads that run below a seal that holds a substrate and a backplate of the display device together. In another aspect the electronic components also connect to an electromechanical device within the display device, as well as connecting to pads that are external to the display device.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: June 3, 2014
    Assignee: QUALCOMM MEMS Technologies, Inc.
    Inventors: Ravindra V. Shenoy, Marc Maurice Mignard, Manish Kothari, Clarence Chui
  • Patent number: 8729713
    Abstract: A vent hole precursor structure (26) in an intermediate product for a semi-conductor device has delicate structures (27, 28), and said intermediate product has a cavity (21) with a pressure therein differing from the pressure of the surroundings. The intermediate product comprises a first wafer (20) in which there is formed a depression (21). The first wafer is bonded to a second wafer (22) comprising a device layer (23) from which the structures (27, 28) are to be made by etching. A hole or groove (26) having a predefined depth extends downwards into the device layer, such that the cavity (21) during etching is opened up before the etching procedure breaks through the device layer (23) to form the structures (27, 28).
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: May 20, 2014
    Assignee: Silex Microsystems AB
    Inventors: Thorbjörn Ebefors, Edvard Kälvesten, Peter Agren, Niklas Svedin
  • Patent number: 8716852
    Abstract: A device includes a capping substrate bonded with a substrate structure. The substrate structure includes an integrated circuit structure. The integrated circuit structure includes a top metallic layer disposed on an outgasing prevention structure. At least one micro-electro mechanical system (MEMS) device is disposed over the top metallic layer and the outgasing prevention structure.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: May 6, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Pao Shu, Chia-Ming Hung, Wen-Chuan Tai, Hung-Sen Wang, Hsiang-Fu Chen, Alex Kalnitsky
  • Patent number: 8709933
    Abstract: A method for making an interconnection component is disclosed, including forming a plurality of metal posts extending away from a reference surface. Each post is formed having a pair of opposed end surface and an edge surface extending therebetween. A dielectric layer is formed contacting the edge surfaces and filling spaces between adjacent ones of the posts. The dielectric layer has first and second opposed surfaces adjacent the first and second end surfaces. The dielectric layer has a coefficient of thermal expansion of less than 8 ppm/° C. The interconnection component is completed such that it has no interconnects between the first and second end surfaces of the posts that extend in a lateral direction. First and second pluralities of wettable contacts are adjacent the first and second opposed surfaces. The wettable contacts are usable to bond the interconnection component to a microelectronic element or a circuit panel.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: April 29, 2014
    Assignee: Tessera, Inc.
    Inventors: Belgacem Haba, Ilyas Mohammed
  • Patent number: 8692291
    Abstract: Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A device structure is formed that includes a well of a first conductivity type in a device region and a doped region of a second conductivity in the well. The device region is comprised of a portion of a device layer of a semiconductor-on-insulator substrate. The doped region and a first portion of the well define a junction. A second portion of the well is positioned between the doped region and an exterior sidewall of the device region. Another portion of the device layer may be patterned to form fins for fin-type field-effect transistors.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: April 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: William F. Clark, Jr., Robert J. Gauthier, Jr., Junjun Li
  • Publication number: 20140091428
    Abstract: A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die mounted to a die side surface of the package substrate, and the opposing land side surface of the package substrate may be mounted to a printed circuit board (PCB). The capacitor may be mounted within a cavity formed in the die side surface of the package substrate or the land side surface of the package substrate. Mounting a capacitor within a cavity may reduce the form factor of the package. The die may be mounted within a cavity formed in the die side surface of the package substrate. Solder balls connecting the package to the PCB may be mounted within one or more cavities formed in one or both of the package substrate and the PCB.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Inventors: MD Altaf Hossain, Scott A. Gilbert
  • Patent number: 8680653
    Abstract: A wafer includes a plurality of chips, each of the chips being spaced from each other by kerf-line regions including a reduced width.
    Type: Grant
    Filed: November 12, 2007
    Date of Patent: March 25, 2014
    Assignee: Infineon Technologies AG
    Inventors: Giuseppe Miccoli, Bhaskaran Jayachandran, Friedrich Steffen, Alfred Vater
  • Patent number: 8637375
    Abstract: A method of manufacturing a tunnel field effect transistor is disclosed. The method comprises forming a two-step profile in a silicon substrate (100) using a patterned hard mask (104) covering the higher steps of said profile; forming a gate stack (114, 116) against the side wall of the higher step; forming spacers (122) on either side of the gate stack (118); and implanting a first type impurity (124) in the higher step and an opposite type impurity in the neighboring lower step (120), wherein at least the first type impurity is implanted using an angled implanting step after removing the patterned hard mask (104). In a preferred embodiment, the method further comprises forming a sacrificial spacer (108) against a side wall of a higher step and the side wall of the hard mask (104); further etching the lower step (106, 110) next to said spacer (108) and subsequently growing a further semiconductor portion (112) on said lower step and removing the spacer (108) prior to forming the gate stack.
    Type: Grant
    Filed: October 12, 2009
    Date of Patent: January 28, 2014
    Assignee: NXP B.V.
    Inventors: Gilberto Curatola, Marcus J. H. Van Dal
  • Patent number: 8624352
    Abstract: An IC capacitor bank includes a plurality of high-k metal-insulator-metal (MIM) capacitors connected to a pair of conductive traces. A fusible trace located on an end of one of the pair of conductive traces forms a capacitor column connected between supply lines, such that failure of a dielectric in the MIM capacitors causes the fusible trace to at least partially open thereby limiting a fault current in the capacitor column. Additionally, a method of manufacturing an IC capacitor bank includes providing a plurality of high-k metal-insulator-metal (MIM) capacitors connected to a pair of conductive traces and locating a fusible trace on an end of the pair of conductive traces to form a capacitor column that is connected between supply lines, such that failure of a dielectric in the MIM capacitors causes the fusible trace to at least partially open thereby limiting a fault current in the capacitor column.
    Type: Grant
    Filed: November 24, 2010
    Date of Patent: January 7, 2014
    Assignee: LSI Corporation
    Inventors: Bonnie E. Weir, Edward B. Harris, Ramnath Venkatraman
  • Patent number: 8587088
    Abstract: A die package having a vertical stack of dies and side-mounted circuitry and methods for making the same are disclosed, for use in an electronic device. The side-mounted circuitry is mounted to a vertical surface of the stack, as opposed to a top surface or adjacent of the stack to reduce the volume of the NVM package.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: November 19, 2013
    Assignee: Apple Inc.
    Inventor: Nicholas Seroff
  • Patent number: 8569881
    Abstract: A semiconductor device includes a baseplate and a first and a second insulated gate bipolar transistor (IGBT) substrate coupled to the baseplate. The semiconductor device includes a first and a second diode substrate coupled to the baseplate and a first, a second, and a third control substrate coupled to the baseplate. Bond wires couple the first and second IGBT substrates to the first control substrate. Bond wires couple the first and second IGBT substrates to the second control substrate via the first and second diode substrates, and bond wires couple the first and second IGBT substrates to the third control substrate via the second diode substrate.
    Type: Grant
    Filed: September 8, 2010
    Date of Patent: October 29, 2013
    Assignee: Infineon Technologies AG
    Inventors: Reinhold Spanke, Waleri Brekel, Ivonne Benzler
  • Publication number: 20130249022
    Abstract: A double-sided diaphragm micro gas-preconcentrator has a micro-gas chamber which is formed by bonding an upper silicon substrate with a lower silicon substrate. One or more suspended membranes are provided on every silicon substrate. The silicon where the suspended membrane is provided is completely removed for forming a cavity. A thin-film heater is deposited on every suspended membrane. A sorptive film is coated on an inner wall of every suspended membrane. Thus, the upper and lower sides of the preconcentrator in the present invention are suspended membranes, which improve the area of the sorptive film on the diaphragm. As a result, the preconcentrating factor is improved while keeping the small heat capacity, fast heating rate, and low power consumption features of the planar diaphragm preconcentrator.
    Type: Application
    Filed: August 9, 2012
    Publication date: September 26, 2013
    Inventors: Xiaosong Du, Ze Wu, Yi Li, Yadong Jiang, Dong Qiu
  • Publication number: 20130193527
    Abstract: The present disclosure includes micro-electro mechanical system (MEMS) structures and methods of forming the same. Substrates of the MEMS structures are bonded together by fusion bonding at high processing temperatures, which enables more complete removal of chemical species from the dielectric materials in the substrates prior to sealing cavities of the MEMS structures. Fusion bonding of MEMS structures reduces outgassing of chemical species and is compatible with the cavity formation process. The MEMS structures bonded by fusion bonding are mechanically stronger compared to eutectic bonding due to a higher bonding ratio. In addition, fusion bonding enables the formation of through substrate vias (TSVs) in the MEMS structures.
    Type: Application
    Filed: March 23, 2012
    Publication date: August 1, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Hua CHU, Kuei-Sung CHANG, Te-Hao LEE
  • Patent number: 8476735
    Abstract: Various structures of a programmable semiconductor interposer for electronic packaging are described. An array of semiconductor devices having various values is formed in the interposer. A user can program the interposer and form a “virtual” device having a desired value by selectively connecting various one of the array of devices to contact pads formed on the surface of the interposer. An inventive electronic package structure includes a standard interposer having an array of unconnected devices of various values and a device selection unit, which selectively connects various one of the array of devices in the standard interposer to an integrated circuit die encapsulated in the electronic package. Methods of forming the programmable semiconductor interposer and the electronic package are also illustrated.
    Type: Grant
    Filed: May 29, 2007
    Date of Patent: July 2, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Shun Hsu, Clinton Chao, Mark Shane Peng
  • Patent number: 8461662
    Abstract: A carbon/epoxy composition includes a bisphenol-based epoxy, an amine-based curing agent, an imidazole-based curing catalyst, and carbon black. A carbon-epoxy dielectric layer is fabricated using a reaction product of the carbon/epoxy composition.
    Type: Grant
    Filed: February 23, 2010
    Date of Patent: June 11, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-Sung Lee, Jin-Young Bae, Yoo-Seong Yang, Sang-Soo Jee
  • Patent number: 8426924
    Abstract: An area efficient distributed device for integrated voltage regulators comprising at least one filler cell coupled between a pair of PADS on I/O rail of a chip and at least one additional filler cell having small size replica of said device is coupled to said I/O rails for distributing replicas of said device on the periphery of said chip. The device is coupled as small size replica on the lower portion of said second filler cell for distributing said device on the periphery of said chip and providing maximal area utilization.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: April 23, 2013
    Assignee: STMicroelectronics Pvt. Ltd.
    Inventors: Joshipura Jwalant, Nitin Bansal, Amit Katyal, Massimiliano Picca
  • Patent number: 8421087
    Abstract: A semiconductor module having one or more silicon carbide diode elements mounted on a switching element is provided in which the temperature rise is reduced by properly disposing each of the diode elements on the switching element, to thereby provide a thermal dissipation path for the respective diode elements. The respective diode elements are arranged on a non-central portion of the switching element, to facilitate dissipation of the heat produced by each of the diode elements, whereby the temperature rise in the semiconductor module is reduced.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: April 16, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kiyoshi Arai, Gourab Majumdar
  • Publication number: 20130082348
    Abstract: Techniques for fabricating passive devices in an extremely-thin silicon-on-insulator (ETSOI) wafer are provided. In one aspect, a method for fabricating one or more passive devices in an ETSOI wafer is provided. The method includes the following steps. The ETSOI wafer having a substrate and an ETSOI layer separated from the substrate by a buried oxide (BOX) is provided. The ETSOI layer is coated with a protective layer. At least one trench is formed that extends through the protective layer, the ETSOI layer and the BOX, and wherein a portion of the substrate is exposed within the trench. Spacers are formed lining sidewalls of the trench. Epitaxial silicon templated from the substrate is grown in the trench. The protective layer is removed from the ETSOI layer. The passive devices are formed in the epitaxial silicon.
    Type: Application
    Filed: October 3, 2011
    Publication date: April 4, 2013
    Applicant: International Business Machines Corporation
    Inventors: Ming Cai, Dechao Guo, Chun-Chen Yeh
  • Patent number: 8400577
    Abstract: Herein disclosed a display apparatus including: a pixel array having a matrix of pixel circuits each including respective electrooptical elements for determining a display brightness level and respective drive circuits for driving the electrooptical elements; wherein adjacent two of the pixel circuits are paired with each other, and each of the drive circuits of the adjacent two pixel circuits includes at least one transistor having a low-concentration source/drain region or an offset region of an offset gate structure, the electrooptical elements and the drive circuits of the adjacent two pixel circuits being laid out such that a line interconnecting a drain region and a source region of the at least one transistor extends parallel to a direction of pixel columns of the pixel circuits of the pixel array.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: March 19, 2013
    Assignee: Sony Corporation
    Inventors: Mitsuru Asano, Seiichiro Jinta, Masatsugu Tomida, Hiroshi Fujimura
  • Patent number: 8390094
    Abstract: An inexpensive variable inductor has inductance value continuously changeable without reducing a Q value. When a control voltage is applied to a control terminal of a MOS transistor from a power supply, a continuity region is formed in a channel, and a region between main terminals becomes conductive. When the control voltage is changed, length of the continuity region in the channel is changed. This changes length of a path area of an induced current, flowing in an induced current film. Thus, the amount of induced current is increased or decreased. Therefore, when the control voltage of the MOS transistor is changed, the inductance value of the coil is continuously changed.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: March 5, 2013
    Assignee: Taiyo Yuden Co., Ltd.
    Inventors: Kunihiko Nakajima, Hideo Ishihara, Yuichi Sasajima
  • Patent number: 8362538
    Abstract: An object is to provide a memory device which does not need a complex manufacturing process and whose power consumption can be suppressed, and a semiconductor device including the memory device. A solution is to provide a capacitor which holds data and a switching element which controls storing and releasing charge in the capacitor in a memory element. In the memory element, a phase-inversion element such as an inverter or a clocked inverter includes the phase of an input signal is inverted and the signal is output. For the switching element, a transistor including an oxide semiconductor in a channel formation region is used. In the case where application of a power supply voltage to the phase-inversion element is stopped, the data is stored in the capacitor, so that the data is held in the capacitor even when the application of the power supply voltage to the phase-inversion element is stopped.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: January 29, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Jun Koyama, Shunpei Yamazaki
  • Publication number: 20130001740
    Abstract: A heat spreader is provided for use with a thermally enhanced flip-chip ball grid array package. In the package, a semiconductor die is positioned front-side down on a package substrate, coupled thereto via solder balls. Passive devices can also be coupled to the substrate alongside the die. The heat spreader is positioned over the substrate and die, in thermal contact with the die. A projection in the center of the heat spreader makes contact with the back surface of the die via a thermal interface material, to draw heat from the die for improved cooling. The projection enables close contact with a thinned die while accommodating thicker passive devices positioned around the die on the substrate.
    Type: Application
    Filed: June 30, 2011
    Publication date: January 3, 2013
    Applicant: STMICROELECTRONICS PTE LTD.
    Inventor: Yiyi Ma
  • Publication number: 20120326247
    Abstract: A method of forming a nanopore array includes patterning a front layer of a substrate to form front trenches, the substrate including a buried layer disposed between the front layer and a back layer; depositing a membrane layer over the patterned front layer and in the front trenches; patterning the back layer and the buried layer to form back trenches, the back trenches being aligned with the front trenches; forming a plurality of nanopores through the membrane layer; depositing a sacrificial material in the front trenches and the back trenches; depositing front and back insulating layers over the sacrificial material; and heating the sacrificial material to a decomposition temperature of the sacrificial material to remove the sacrificial material and form pairs of front and back channels, wherein the front channel of each channel pair is connected to the back channel of its respective channel pair by an individual nanopore.
    Type: Application
    Filed: September 7, 2012
    Publication date: December 27, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bing Dang, Hongbo Peng
  • Patent number: 8330216
    Abstract: A non-volatile semiconductor memory device includes a first columnar semiconductor layer and a plurality of first conductive layers formed such that a charge storage layer for storing charges is sandwiched between the first conductive layers and the first columnar semiconductor layer. Also, the non-volatile semiconductor memory device includes a second columnar semiconductor layer and a second conductive layer formed such that an insulating layer is sandwiched between the second conductive layer and the second columnar semiconductor layer, the second conductive layer being repeatedly provided in a line form by providing a certain interval in a first direction perpendicular to a laminating direction. A first sidewall conductive layer being in contact with the second conductive layer and extending in the first direction is formed on a sidewall along a longitudinal direction of the second conductive layer.
    Type: Grant
    Filed: December 29, 2008
    Date of Patent: December 11, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yosuke Komori, Masaru Kito, Megumi Ishiduki, Ryota Katsumata, Hiroyasu Tanaka, Masaru Kidoh, Yoshiaki Fukuzumi, Hideaki Aochi, Yasuyuki Matsuoka
  • Patent number: 8304271
    Abstract: A bulk GaN layer is on a first surface of a substrate, wherein the bulk GaN layer has a GaN transistor region and a bulk acoustic wave (BAW) device region. A source/drain layer is over a first surface of the bulk GaN layer in the GaN transistor region. A gate electrode is formed over the source/drain layer. A first BAW electrode is formed over the first surface of the bulk GaN layer in the BAW device region. An opening is formed in a second surface of the substrate, opposite the first surface of the substrate, which extends through the substrate and exposes a second surface of the bulk GaN layer, opposite the first surface of the bulk GaN layer. A second BAW electrode is formed within the opening over the second surface of the bulk GaN layer.
    Type: Grant
    Filed: May 20, 2009
    Date of Patent: November 6, 2012
    Inventors: Jenn Hwa Huang, Bruce M. Green
  • Patent number: 8299525
    Abstract: In a power IC device, a surface layer channel CMOS transistor and a trench power MOS transistor are formed on the same chip. In one embodiment, a source region of the trench power MOS transistor is arranged at the same level as a gate electrode of the surface layer channel CMOS transistor. Thus, the power IC device and a method for manufacturing the power IC device are provided for reducing manufacturing cost in the case of forming the trench power MOS transistor and the surface layer channel CMOS transistor on the same chip.
    Type: Grant
    Filed: March 20, 2007
    Date of Patent: October 30, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Alberto O. Adan, Mitsuhiro Kikuta
  • Patent number: 8299537
    Abstract: A semiconductor-on-insulator substrate and a related semiconductor structure, as well as a method for fabricating the semiconductor-on-insulator substrate and the related semiconductor structure, provide for a multiple order radio frequency harmonic suppressing region located and formed within a base semiconductor substrate at a location beneath an interface of a buried dielectric layer with the base semiconductor substrate within the semiconductor-on-insulator substrate. The multiple order radio frequency harmonic suppressing region may comprise an ion implanted atom, such as but not limited to a noble gas atom, to provide a suppressed multiple order radio frequency harmonic when powering a radio frequency device, such as but not limited to a radio frequency complementary metal oxide semiconductor device (or alternatively a passive device), located and formed within and upon a surface semiconductor layer within the semiconductor structure.
    Type: Grant
    Filed: February 11, 2009
    Date of Patent: October 30, 2012
    Assignee: International Business Machines Corporation
    Inventors: Joseph R. Greco, Kevin Munger, Richard A. Phelps, Jennifer C. Robbins, William Savaria, James A. Slinkman, Randy L. Wolf
  • Publication number: 20120267751
    Abstract: A method for making an interconnection component is disclosed, including forming a plurality of metal posts extending away from a reference surface. Each post is formed having a pair of opposed end surface and an edge surface extending therebetween. A dielectric layer is formed contacting the edge surfaces and filling spaces between adjacent ones of the posts. The dielectric layer has first and second opposed surfaces adjacent the first and second end surfaces. The dielectric layer has a coefficient of thermal expansion of less than 8 ppm/° C. The interconnection component is completed such that it has no interconnects between the first and second end surfaces of the posts that extend in a lateral direction. First and second pluralities of wettable contacts are adjacent the first and second opposed surfaces. The wettable contacts are usable to bond the interconnection component to a microelectronic element or a circuit panel.
    Type: Application
    Filed: April 21, 2011
    Publication date: October 25, 2012
    Applicant: TESSERA RESEARCH LLC
    Inventors: Belgacem Haba, Ilyas Mohammed
  • Publication number: 20120261767
    Abstract: Systems and methods for reducing gate leakage current and positive bias temperature instability drift are provided. In one embodiment, a system comprises a p-channel field effect transistor (PFET) device on a semiconductor substrate, and a high voltage transistor on the substrate. The system also comprises a plurality of silicides formed in the substrate, the plurality of silicides formed proximate to the PFET device and the high voltage transistor. Further, the system comprises a buffer oxide layer formed over the substrate, the PFET device, and the high voltage transistor and a moisture barrier formed over the buffer layer, the moisture barrier comprised of silicon oxynitride. Additionally, the system comprises an interlayer dielectric device formed over the moisture barrier and a plurality of electrical contacts extending through the interlayer dielectric, the moisture barrier, and the buffer oxide layer, wherein the plurality of electrical contacts are electrically connected to the plurality of silicides.
    Type: Application
    Filed: March 19, 2012
    Publication date: October 18, 2012
    Applicant: INTERSIL AMERICAS INC.
    Inventor: Michael D. Church
  • Publication number: 20120250910
    Abstract: A semiconductor die with an integrated electronic circuit, configured so as to be mounted in a housing with a capacitive transducer e.g. a microphone. A first circuit is configured to receive an input signal from the transducer at an input node and to provide an output signal at a pad of the semiconductor die. The integrated electronic circuit comprises an active switch device with a control input, coupled to a pad of the semiconductor die, to operatively engage or disengage a second circuit interconnected with the first circuit so as to operate the integrated electronic circuit in a mode selected by the control input. That is, a programmable or controllable transducer. The second circuit is interconnected with the first circuit so as to be separate from the input node. Thereby less noise is induced, a more precise control of the circuit is obtainable and more advanced control options are possible.
    Type: Application
    Filed: March 29, 2012
    Publication date: October 4, 2012
    Applicant: AUDIOASICS A/S
    Inventors: Mohammad SHAJAAN, Henrik THOMSEN, Jens Jorge Gaarde HENRIKSEN, Claus Erdmann FUERST
  • Publication number: 20120250429
    Abstract: A process is provided for fabricating a wafer including a plurality of chips separated by scribe lines. The method includes locking at least one chip on the wafer using a secret key, and writing the secret key into at least one memory present on the wafer.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 4, 2012
    Inventors: FRANCOIS TAILLIET, Marc Battista, Luc Wuidart
  • Patent number: 8269308
    Abstract: A semiconductor device is made by forming an oxide layer over a substrate and forming a first conductive layer over the oxide layer. The first conductive layer is connected to ground. A second conductive layer is formed over the first conductive layer as a plurality of segments. A third conductive layer is formed over the second conductive layer as a plurality of segments. If the conductive layers are electrically isolated, then a conductive via is formed through these layers. A first segment of the third conductive layer operates as a first passive circuit element. A second segment operates as a second passive circuit element. A third segment is connected to ground and operates as a shield disposed between the first and second segments. The shield has a height at least equal to a height of the passive circuit elements to block cross-talk between the passive circuit elements.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: September 18, 2012
    Assignee: STATS ChipPAC, Ltd.
    Inventors: YongTaek Lee, Gwang Kim, ByungHoon Ahn
  • Patent number: 8264007
    Abstract: A cell of a semiconductor device includes a substrate portion formed to include a plurality of diffusion regions, including at least one p-type diffusion region and at least one n-type diffusion region separated from each other by one or more non-active regions. The cell includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight. The cell also includes a number of interconnect levels formed above the gate electrode level.
    Type: Grant
    Filed: October 1, 2009
    Date of Patent: September 11, 2012
    Assignee: Tela Innovations, Inc.
    Inventors: Scott T. Becker, Michael C. Smayling
  • Patent number: 8264008
    Abstract: A cell layout of a semiconductor device includes a diffusion level layout including a plurality of diffusion region layout shapes, including p-type and n-type diffusion regions separated by a central inactive region. The cell layout also includes a gate electrode level layout for the entire cell defined to include linear-shaped layout features placed to extend in only a first parallel direction. Adjacent linear-shaped layout features that share a common line of extent in the first parallel direction are separated from each other by an end-to-end spacing that is substantially equal and minimized across the gate electrode level layout. Linear-shaped layout features within the gate electrode level layout extend over one or more of the p-type and/or n-type diffusion regions to form PMOS and NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight.
    Type: Grant
    Filed: October 1, 2009
    Date of Patent: September 11, 2012
    Assignee: Tela Innovations, Inc.
    Inventors: Scott T. Becker, Michael C. Smayling
  • Patent number: 8258552
    Abstract: A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal and minimized across the gate electrode level region. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight. A width of the conductive features within a five wavelength photolithographic interaction radius is less than a wavelength of light of 193 nanometers as used in a photolithography process for their fabrication.
    Type: Grant
    Filed: October 1, 2009
    Date of Patent: September 4, 2012
    Assignee: Tela Innovations, Inc.
    Inventors: Scott T. Becker, Michael C. Smayling
  • Patent number: 8258550
    Abstract: A cell layout of a semiconductor device includes a diffusion level layout including a plurality of diffusion region layout shapes. The cell layout also includes a gate electrode level layout defined to include linear-shaped layout features placed to extend in only a first parallel direction. Adjacent linear-shaped layout features that share a common line of extent in the first parallel direction are separated from each other by an end-to-end spacing that is substantially equal across the gate electrode level layout and that is minimized to an extent allowed by a semiconductor device manufacturing capability. The gate electrode level layout includes linear-shaped layout features defined along at least four different lines of extent in the first parallel direction. The cell layout also includes a number of interconnect level layouts each defined to pattern conductive features within corresponding interconnect levels above the gate electrode level of the cell.
    Type: Grant
    Filed: October 1, 2009
    Date of Patent: September 4, 2012
    Assignee: Tela Innovations, Inc.
    Inventors: Scott T. Becker, Michael C. Smayling
  • Patent number: 8258551
    Abstract: A cell of a semiconductor device includes a diffusion level including a plurality of diffusion regions separated by inactive regions. The cell also includes a gate electrode level including conductive features defined to extend in only a first parallel direction. Adjacent ones of the conductive features that share a common line of extent in the first parallel direction are fabricated from respective originating layout features that are separated from each other by an end-to-end spacing having a size that is substantially equal across the gate electrode level region and is minimized to an extent allowed by a semiconductor device manufacturing capability. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the cell. The cell also includes a number of interconnect levels formed above the gate electrode level.
    Type: Grant
    Filed: October 1, 2009
    Date of Patent: September 4, 2012
    Assignee: Tela Innovations, Inc.
    Inventors: Scott T. Becker, Michael C. Smayling