With At Least One Potential Barrier Or Surface Barrier (epo) Patents (Class 257/E27.128)
  • Patent number: 10670456
    Abstract: An integrated circuit includes a substrate and at least one photo-voltaic cell implemented on the substrate. The at least one photo-voltaic cell is configured to generate a supply voltage. Circuitry is implemented on the substrate. The circuitry is powered by the supply voltage. The at least one photo-voltaic cell can include a number of series-connected photo-voltaic cells.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: June 2, 2020
    Assignee: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED
    Inventors: Jeffrey M. Raynor, Laurence Stark, Filip Kaklin
  • Patent number: 10630392
    Abstract: According to one embodiment, a quantum communication system includes a transmitting apparatus and a receiving apparatus. The transmitting apparatus includes a plurality of light sources configured to generate a plurality of optical pulses having different wavelengths, an encoder including a single first modulator configured to modulate the optical pulses to encode information, and a transmitting part configured to transmit an optical pulse train including the modulated optical pulses to the receiving apparatus. The receiving apparatus includes a receiving part configured to receive the optical pulse train from the transmitting apparatus, and a decoder configured to obtain information based on the received optical pulse train.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: April 21, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, Toshiba Infrastructure Systems & Solutions Corporation
    Inventors: Masakazu Kikawada, Masatoshi Hirono
  • Patent number: 10605985
    Abstract: An optoelectronic device includes an integrated circuit including electronic devices formed on a front side of a semiconductor substrate. A barrier layer is formed on a back side of the semiconductor substrate. A photonics layer is formed on the barrier layer. The photonics layer includes a core for transmission of light and a cladding layer encapsulating the core and including a different index of refraction than the core. The core is configured to couple light generated from a component of the optoelectronic device.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: March 31, 2020
    Assignee: International Business Machines Corporation
    Inventors: Russell A. Budd, Effendi Leobandung, Ning Li, Jean-Olivier Plouchart, Devendra K. Sadana
  • Patent number: 10168044
    Abstract: A self-contained smoke alarm detector, emergency light and alternate light source mechanism in one unit.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: January 1, 2019
    Inventor: Marcia Lawson
  • Patent number: 9997414
    Abstract: Techniques are disclosed for forming Ge/SiGe-channel and III-V-channel transistors on the same die. The techniques include depositing a pseudo-substrate of Ge/SiGe or III-V material on a Si or insulator substrate. The pseudo-substrate can then be patterned into fins and a subset of the fins can be replaced by the other of Ge/SiGe or III-V material. The Ge/SiGe fins can be used for p-MOS transistors and the III-V material fins can be used for n-MOS transistors, and both sets of fins can be used for CMOS devices, for example. In some instances, only the channel region of the subset of fins are replaced during, for example, a replacement gate process. In some instances, some or all of the fins may be formed into or replaced by one or more nanowires or nanoribbons.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: June 12, 2018
    Assignee: INTEL CORPORATION
    Inventors: Glenn A. Glass, Anand S. Murthy, Karthik Jambunathan
  • Patent number: 9917418
    Abstract: Monolithic, wavelength-tunable QCL devices are provided which comprise a substrate, an array of QCLs formed on the substrate and an optical beam combiner formed on the substrate electrically isolated from the array of QCLs. In embodiments, the QCL devices are configured to provide laser emission in the range of from about 3 ?m to about 12 ?m, a wavelength tuning range of at least about 500 cm?1, and a wavelength tuning step size of about 1.0 nm or less.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: March 13, 2018
    Assignee: Northwestern University
    Inventor: Manijeh Razeghi
  • Patent number: 9864136
    Abstract: Disclosed are non-planar monolithic hybrid optoelectronic structures. These structures are referred to as non-planar because they contain one or more semiconductor fins. These structures are referred to as monolithic because they contain, within each semiconductor fin, an optical waveguide core positioned laterally between a light sensor and a photodetector. Specifically, each semiconductor fin has end portions and a center portion positioned laterally between the end portions. The center portion is an optical waveguide core and the end portions have trenches that contain the light source and photodetector, respectively. These structures are referred to as hybrid because the optical waveguide core is made of one semiconductor material and the light sensor and photodetector are each made of at least one additional semiconductor material that is different from the semiconductor material of the center portion. Also disclosed herein are methods of forming monolithic non-planar hybrid optoelectronic structures.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: January 9, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Ajey P. Jacob
  • Patent number: 9804330
    Abstract: According to the present invention, a semiconductor device includes a substrate comprising a front end face, a rear end face and side faces, a plurality of semiconductor lasers provided on the substrate, a forward optical multiplexer to multiplex forward output light of the plurality of semiconductor lasers and output the multiplexed light to the front end face, a backward optical multiplexer to multiplex backward output light of the plurality of semiconductor lasers and output the multiplexed light to the rear end face and a plurality of backward waveguides connected to an output section of the backward optical multiplexer, wherein the plurality of backward waveguides includes a main waveguide disposed at a center of the output section and a plurality of lateral waveguides disposed on both sides of the main waveguide to bend toward the side faces and output light from the side faces diagonally to the side faces.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: October 31, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Ryosuke Nagao, Yoshifumi Sasahata, Eitaro Ishimura
  • Patent number: 9690042
    Abstract: Disclosed are an optical input/output device and an opto-electronic system including the same. The device includes a bulk silicon substrate, at least one vertical-input light detection element monolithically integrated on a portion of the bulk silicon substrate, and at least one vertical-output light source element monolithically integrated on another portion of the bulk silicon substrate adjacent to the vertical-input light detection element. The vertical-output light source element includes a III-V compound semiconductor light source active layer combined with the bulk silicon substrate by a wafer bonding method.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: June 27, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Gyungock Kim, Hyundai Park, In Gyoo Kim, Sang Hoon Kim, Ki Seok Jang, Sang Gi Kim, Jiho Joo, Yongseok Choi, Hyuk Je Kwon, Jaegyu Park, Sun Ae Kim, Jin Hyuk Oh, Myung Joon Kwack
  • Patent number: 9632741
    Abstract: The wireless electronic retail price tag system is a display system for retail shelves. The wireless electronic retail price tag system is a wireless electronic display that attaches readily on shelves and that is used for displaying product, price, and marketing information items on the shelves. The wireless electronic retail price tag system is adapted to communicate with and to be updated by a master computer located in a secure location. The wireless electronic retail price tag system comprises an LCD, a microcontroller, a remote wireless interface, and a housing.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: April 25, 2017
    Inventor: Gerardo Alvarez
  • Patent number: 9601906
    Abstract: A first arm portion and a second arm portion are provided so as to have a distance therebetween greater than a distance between input ends of two output waveguides and greater than a distance between an output end of a first output portion and an output end of a second output portion, the first arm portion forming a traveling path of light from one of the two output waveguides to the first output portion through a first optical amplifier, the second arm portion forming a traveling path of light from another one of the two output waveguides to the second output portion through a second optical amplifier. The first optical amplifier and the second optical amplifier have curved portions in which the first output portion and the second output portion are curved in a direction toward each other, and the first optical amplifier and the second optical amplifier respectively output light from the output end of the first output portion and the output end of the second output portion.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: March 21, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Masakazu Takabayashi, Yuichiro Horiguchi, Mitsunobu Gotoda, Eitaro Ishimura
  • Patent number: 9443423
    Abstract: An information communication method for use in a portable terminal, e.g., a wristwatch, to obtain information includes a light receiving step of, by at least one of plural solar cells incorporated in the portable terminal and having respective directivities, receiving visible light that is emitted in a direction corresponding to the directivity of the relevant solar cell, and an information acquisition step of obtaining information by demodulating a signal that is specified by the received visible light.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: September 13, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Hideki Aoyama, Mitsuaki Oshima
  • Patent number: 9431629
    Abstract: Provided is an organic light-emitting display apparatus including: a substrate having one or more side walls; a display unit positioned on the substrate; and an encapsulation layer deposited over the display unit and contacting each of the one or more side walls, wherein a height of an outer end portion of the encapsulation layer is less than that of each of the side walls.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: August 30, 2016
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Seung-Jun Moon
  • Patent number: 8928893
    Abstract: The internal propagation of radiation between a radiation source and radiation detector mounted within a sensor package is prevented by the use of an optical isolator. The optical isolator is formed by the combination of a baffle mounted between the source and detector and a groove formed in an upper surface of the sensor package between the source and detector. A bottom of the groove is positioned adjacent to an upper edge of the baffle.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: January 6, 2015
    Assignees: STMicroelectronics (Research & Development) Limited, STMicroelectronics (Grenoble 2) SAS
    Inventors: Ewan Findlay, Colin Campbell, Gemma Ramsey, Eric Saugier
  • Patent number: 8916917
    Abstract: According to one embodiment, a solid-state imaging device includes a first element formation region surrounded by an element isolation region in a semiconductor substrate having a first and a second surface, an upper element isolation layer on the first surface in the element formation region, a lower element isolation layer between the second surface and the upper element isolation layer, a first photodiode in the element formation region, a floating diffusion in the element formation region, and a first transistor disposed between the first photodiode and the floating diffusion. A side surface of the lower element isolation layer protrudes closer to the transistor than a side surface of the upper element isolation layer.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: December 23, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shogo Furuya, Hirofumi Yamashita, Tetsuya Yamaguchi
  • Patent number: 8878265
    Abstract: According to one embodiment, a solid-state imaging device includes a first element formation region surrounded by an element isolation region in a semiconductor substrate having a first and a second surface, an upper element isolation layer on the first surface in the element formation region, a lower element isolation layer between the second surface and the upper element isolation layer, a first photodiode in the element formation region, a floating diffusion in the element formation region, and a first transistor disposed between the first photodiode and the floating diffusion. A side surface of the lower element isolation layer protrudes closer to the transistor than a side surface of the upper element isolation layer.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: November 4, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shogo Furuya, Hirofumi Yamashita, Tetsuya Yamaguchi
  • Patent number: 8779544
    Abstract: A photoelectric conversion apparatus comprises multiple photoelectric conversion portions (51) disposed in a semiconductor substrate (5B) wherein each photoelectric conversion portion (51) includes: a P-type charge accumulating area (107) containing a first impurity; and an N-type well portion (102) that, along with the P-type charge accumulating area, configures a photodiode, and each well portion has: an N-type first semiconductor region (102a) containing arsenic at a first density; an N-type second semiconductor region (102b,102C) disposed below the first semiconductor region and containing arsenic at a second density that is lower than the first density; and an N-type third semiconductor region (102d) disposed below the second semiconductor region and containing a second impurity at a third density that is higher than the first density.
    Type: Grant
    Filed: January 26, 2010
    Date of Patent: July 15, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yuichiro Yamashita, Takanori Watanabe, Mineo Shimotsusa, Takeshi Ichikawa
  • Patent number: 8692295
    Abstract: A double heterojunction bipolar transistor on a substrate comprises a collector formed of InGaAsP, a base in contact with the collector, an emitter in contact with the base, and electrodes forming separate electrical contacts with each of the collector, base, and emitter, respectively. A device incorporates this transistor and an opto-electronic device optically coupled with the collector of the transistor to interact with light transmitted therethrough.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: April 8, 2014
    Assignee: HRL Laboratories, LLC
    Inventors: Rajesh D. Rajavel, Stephen Thomas, III
  • Publication number: 20130313668
    Abstract: A photronic device includes a substrate having an opening through the substrate. The photronic device further includes an insulating layer over the substrate including over the opening. The photronic device further includes an active layer over the insulating layer. The photronic device further includes a photoactive device formed in the active layer, wherein the photoactive device is over the opening. The photronic device further includes active electronic circuitry formed in the active layer. The photronic device further includes a reflective layer on the insulating layer in the opening.
    Type: Application
    Filed: May 24, 2012
    Publication date: November 28, 2013
    Inventors: Gregory S. Spencer, John R. Alvis, Hsiao-Hui Chen, Joseph F. Orcutt, Srivatsa G. Kundalgurki
  • Patent number: 8552414
    Abstract: An electronically scannable multiplexing device is capable of addressing multiple bits within a volatile or non-volatile memory cell. The multiplexing device generates an electronically scannable conducting channel with two oppositely formed depletion regions. The depletion width of each depletion region is controlled by a voltage applied to a respective control gate at each end of the multiplexing device. The present multi-bit addressing technique allows, for example, 10 to 100 bits of data to be accessed or addressed at a single node. The present invention can also be used to build a programmable nanoscale logic array or for randomly accessing a nanoscale sensor array.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: October 8, 2013
    Assignee: International Business Machines Corporation
    Inventors: Hemantha Kumar Wickramasinghe, Kailash Gopalakrishnan
  • Publication number: 20130228887
    Abstract: Methods and structures for providing single-color or multi-color photo-detectors leveraging plasmon resonance for performance benefits. In one example, a radiation detector includes a semiconductor absorber layer having a first electrical conductivity type and an energy bandgap responsive to radiation in a first spectral region, a semiconductor collector layer coupled to the absorber layer and having a second electrical conductivity type, and a plasmonic resonator coupled to the collector layer and having a periodic structure including a plurality of features arranged in a regularly repeating pattern.
    Type: Application
    Filed: September 12, 2012
    Publication date: September 5, 2013
    Applicant: RAYTHEON COMPANY
    Inventors: Justin Gordon Adams Wehner, Edward Peter Gordon Smith
  • Publication number: 20130001731
    Abstract: A method of fabricating an optoelectronic device includes creating an optoelectronic structure on a first substrate. The optoelectronic structure includes a release layer and a plurality of inorganic semiconductor layers supported by the release layer. The plurality of inorganic semiconductor layers is configured to be active in operation of the optoelectronic device. The plurality of inorganic semiconductor layers are permanently attached to a second substrate, which is flexible. The plurality of inorganic semiconductor layers are released from the first substrate after the attaching step, and the second substrate is deformed to a non-planar configuration.
    Type: Application
    Filed: June 28, 2012
    Publication date: January 3, 2013
    Applicant: THE REGENTS OF THE UNIVERSITY OF MICHIGAN
    Inventors: Stephen Forrest, Jeramy D. Zimmerman, Xin Xu, Christopher Kyle Renshaw
  • Publication number: 20120228681
    Abstract: An image or light sensor chip package includes an image or light sensor chip having a non-photosensitive area and a photosensitive area surrounded by the non-photosensitive area. In the photosensitive area, there are light sensors, a layer of optical or color filter array over the light sensors and microlenses over the layer of optical or color filter array. In the non-photosensitive area, there are an adhesive polymer layer and multiple metal structures having a portion in the adhesive polymer layer. A transparent substrate is formed on a top surface of the adhesive polymer layer and over the microlenses. The image or light sensor chip package also includes wirebonded wires or a flexible substrate bonded with the metal structures of the image or light sensor chip.
    Type: Application
    Filed: May 18, 2012
    Publication date: September 13, 2012
    Applicant: Megica Corporation
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee
  • Publication number: 20120187517
    Abstract: In a photodetector 1, a low-resistance Si substrate 3, an insulating layer 4, a high-resistance Si substrate 5, and an Si photodiode 20 construct a hermetically sealed package for an InGaAs photodiode 30 placed within a recess 6, while an electric passage part 8 of the low-resistance Si substrate 3 and a wiring film 15 achieve electric wiring for the Si photodiode 20 and InGaAs photodiode 30. While a p-type region 22 of the Si photodiode 20 is disposed in a part on the rear face 21b side of an Si substrate 21, a p-type region 32 of the InGaAs photodiode 30 is disposed in a part on the front face 31a side of an InGaAs substrate 31.
    Type: Application
    Filed: July 7, 2010
    Publication date: July 26, 2012
    Applicant: HAMAMATSU PHOTONICS K.K.
    Inventors: Yoshihisa Warashina, Masatoshi Ishihara, Tomofumi Suzuki
  • Publication number: 20120168835
    Abstract: Optical structures having an array of protuberances between two layers having different refractive indices are provided. The array of protuberances has vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode of a CMOS image sensor. The array of protuberances provides high transmission of light with little reflection. The array of protuberances may be provided over a photodiode, in a back-end-of-line interconnect structure, over a lens for a photodiode, on a backside of a photodiode, or on a window of a chip package.
    Type: Application
    Filed: March 13, 2012
    Publication date: July 5, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James W. Adkisson, John J. Ellis-Monaghan, Jeffrey P. Gambino, Charles F. Musante
  • Publication number: 20120085890
    Abstract: An object is to reduce the size and manufacturing cost of a photodetector. In order to reduce the area where a visible light sensor and an infrared light sensor are provided, a first photodiode that detects visible light and a second photodiode that detects infrared light are arranged to overlap with each other so that visible light is absorbed first by the first photodiode, whereby significantly little visible light enters the second photodiode. Further, the first photodiode overlapping with the second photodiode is used as an optical filter for the second photodiode. Therefore, a semiconductor layer included in the first photodiode absorbs visible light and transmits infrared light, and a semiconductor layer included in the second photodiode absorbs infrared light.
    Type: Application
    Filed: October 5, 2011
    Publication date: April 12, 2012
    Inventor: Yoshiyuki Kurokawa
  • Patent number: 8120078
    Abstract: A photodiode structure including a semiconductor of a first conductivity type, the semiconductor having a main surface, a first well formed in the semiconductor at the main surface thereof, the first well being of a second conductivity type opposite to the first conductivity type. A second well formed in the semiconductor at the main surface thereof laterally outside the first well, the second well being of the second conductivity type, and a first terminal electrically connecting the first well and the second well, and a second terminal connecting the semiconductor such that a depletion region of laterally varying distance to the main surface results from applying a reverse voltage to the first and second terminals.
    Type: Grant
    Filed: November 19, 2007
    Date of Patent: February 21, 2012
    Assignee: Infineon Technologies AG
    Inventor: Stefan Hermann Groiss
  • Publication number: 20110309459
    Abstract: The present disclosure uses at least two cascaded photodetectors. Device area is increased to provide a bigger current than a single photodetector under the same bandwidth. Hence, bandwidth efficiency (BRP) and saturation current-bandwidth product (SCBP) are improved for a high speed, a high responsivity and a high bandwidth with simple structure and low cost.
    Type: Application
    Filed: December 1, 2010
    Publication date: December 22, 2011
    Applicant: NATIONAL CENTRAL UNIVERSITY
    Inventors: Jin-Wei Shi, Feng-Ming Kuo
  • Publication number: 20110234868
    Abstract: A photoelectric conversion apparatus comprises multiple photoelectric conversion portions (51) disposed in a semiconductor substrate (5B) wherein each photoelectric conversion portion (51) includes: a P-type charge accumulating area (107) containing a first impurity; and an N-type well portion (102) that, along with the P-type charge accumulating area, configures a photodiode, and each well portion has: an N-type first semiconductor region (102a) containing arsenic at a first density; an N-type second semiconductor region (102b,102C) disposed below the first semiconductor region and containing arsenic at a second density that is lower than the first density; and an N-type third semiconductor region (102d) disposed below the second semiconductor region and containing a second impurity at a third density that is higher than the first density.
    Type: Application
    Filed: January 26, 2010
    Publication date: September 29, 2011
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Yuichiro Yamashita, Takanori Watanabe, Mineo Shimotsusa, Takeshi Ichikawa
  • Publication number: 20110233609
    Abstract: The invention relates to a method for producing an infrared radiation sensor, said sensor comprising an infrared photodiode array formed in a first material and a reading circuit formed in a second material, said method comprising the steps of: sticking, through molecular adhesion, a first material side surface onto an optically transparent crystalline material side surface having infrared radiation and a coefficient of thermal expansion similar to that of the second material, give or take 20%; thinning the body of the first material side surface so that the latter is less that 25 ?m; producing infrared-sensitive photodiodes onto the thus-thinned first material side surface; depositing contact ball bearings onto the infrared photodiodes; and mounting the reading circuit onto the first material side surface through flip chip technology.
    Type: Application
    Filed: November 27, 2009
    Publication date: September 29, 2011
    Applicant: Sagem Defense Securite
    Inventors: Arnaud Cordat, Herve Sik, Stéphane Demiguel
  • Patent number: 7977693
    Abstract: A semiconductor light-emitting material includes a semiconductor substance including a matrix semiconductor whose constituent atoms are bonded to form a tetrahedral structure, an impurity atom S substituted for an atom in a lattice site of the matrix semiconductor, and an impurity atom I inserted in a interstitial site of the matrix semiconductor, the impurity atom S and the impurity atom I being bonded through charge transfer therebetween in a state that the impurity atom S has an electric charge coincident with that of the constituent atom of the matrix semiconductor and the impurity atom I has an electron configuration of a closed shell structure, in which the semiconductor substance is stretched in a direction of a bond forming the tetrahedral structure.
    Type: Grant
    Filed: September 13, 2006
    Date of Patent: July 12, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Kazushige Yamamoto, Shigeru Haneda
  • Patent number: 7875915
    Abstract: An integrated circuit includes at least one photodiode associated with a read transistor. The photodiode is formed from a stack of three semiconductor layers comprising a buried layer, an floating substrate layer and an upper layer. The drain region and/or the source region of the transistor are incorporated within the upper layer. The buried layer is electrically isolated from the upper layer so as to allow the buried layer to be biased independently of the upper layer.
    Type: Grant
    Filed: May 10, 2006
    Date of Patent: January 25, 2011
    Assignee: STMicroelectronics S.A.
    Inventors: François Roy, Arnaud Tournier
  • Patent number: 7868335
    Abstract: A bipolar junction transistor having an emitter, a base, and a collector includes a stack of one or more layer sets adjacent the collector. Each layer set includes a first material having a first band gap, wherein the first material is highly doped, and a second material having a second band gap narrower than the first band gap, wherein the second material is at most lightly doped.
    Type: Grant
    Filed: August 18, 2008
    Date of Patent: January 11, 2011
    Assignee: HRL Laboratories, LLC
    Inventors: James Chingwei Li, Marko Sokolich, Tahir Hussain, David H. Chow
  • Patent number: 7851810
    Abstract: A semiconductor light emitting device includes a multi-layered semiconductor layer having at least a first conductive type cladding layer, an active layer, a second conductive type first cladding layer, an etching stop layer, and a second conductive type second cladding layer on a substrate. An upper section of a ridge groove is formed by an anisotropic etching process, as a first groove in such a way as to have a depth from a surface of the multi-layered semiconductor layer and as not to cross the etching stop layer at the depth. A bottom groove of the ridge groove is formed by an isotropic etching process, as a second groove by performing etching in such a way as to be stopped by the etching stop layer.
    Type: Grant
    Filed: December 8, 2006
    Date of Patent: December 14, 2010
    Assignee: Sony Corporation
    Inventors: Mari Chiba, Hisashi Kudo, Shinichi Agatsuma
  • Patent number: 7692212
    Abstract: A double heterojunction bipolar transistor on a substrate comprises a collector formed of InGaAsP, a base in contact with the collector, an emitter in contact with the base, and electrodes forming separate electrical contacts with each of the collector, base, and emitter, respectively. A device incorporates this transistor and an opto-electronic device optically coupled with the collector of the transistor to interact with light transmitted therethrough.
    Type: Grant
    Filed: December 7, 2004
    Date of Patent: April 6, 2010
    Assignee: HRL Laboratories, LLC
    Inventors: Rajesh D. Rajavel, Stephen Thomas, III
  • Patent number: 7687302
    Abstract: A frame shutter type device provides a separated well in which the storage node is located. The storage node is also shielded by a light shield to prevent photoelectric conversion.
    Type: Grant
    Filed: May 9, 2008
    Date of Patent: March 30, 2010
    Assignee: Aptina Imaging Corporation
    Inventors: Eric R. Fossum, Sandor L. Barna
  • Patent number: 7592654
    Abstract: CMOS image sensor having high sensitivity and low crosstalk, particularly at far-red to infrared wavelengths, and a method for fabricating a CMOS image sensor. A CMOS image sensor has a substrate, an epitaxial layer above the substrate, and a plurality of pixels extending into the epitaxial layer for receiving light. The image sensor also includes at least one of a horizontal barrier layer between the substrate and the epitaxial layer for preventing carriers generated in the substrate from moving to the epitaxial layer, and a plurality of lateral barrier layers between adjacent ones of the plurality of pixels for preventing lateral diffusion of electrons in the epitaxial layer.
    Type: Grant
    Filed: November 15, 2007
    Date of Patent: September 22, 2009
    Assignee: Aptina Imaging Corporation
    Inventors: Sandeep R. Bahl, Fredrick P. LaMaster, David W. Bigelow
  • Publication number: 20090127597
    Abstract: A photodiode structure including a semiconductor of a first conductivity type, the semiconductor having a main surface, a first well formed in the semiconductor at the main surface thereof, the first well being of a second conductivity type opposite to the first conductivity type. A second well formed in the semiconductor at the main surface thereof laterally outside the first well, the second well being of the second conductivity type, and a first terminal electrically connecting the first well and the second well, and a second terminal connecting the semiconductor such that a depletion region of laterally varying distance to the main surface results from applying a reverse voltage to the first and second terminals.
    Type: Application
    Filed: November 19, 2007
    Publication date: May 21, 2009
    Inventor: Stefan Hermann Groiss
  • Patent number: 7492026
    Abstract: A light sensor located above an integrated circuit including a lower electrode, a heavily-doped amorphous silicon layer of a first conductivity type, and a lightly-doped amorphous silicon layer of a second conductivity type. The lightly-doped amorphous silicon layer rests on a planar surface at least above and in the vicinity of the lower electrode.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: February 17, 2009
    Assignee: STMicroelectronics S.A.
    Inventors: Danielle Thomas, Maurice Rivoire
  • Publication number: 20080251723
    Abstract: Electromagnetic radiation detecting and sensing systems using carbon nanotube fabrics and methods of making the same are provided. In certain embodiments of the invention, an electromagnetic radiation detector includes a substrate, a nanotube fabric disposed on the substrate, the nanotube fabric comprising a non-woven network of nanotubes, and first and second conductive terminals, each in electrical communication with the nanotube fabric, the first and second conductive terminals disposed in space relation to one another. Nanotube fabrics may be tuned to be sensitive to a predetermined range of electromagnetic radiation such that exposure to the electromagnetic radiation induces a change in impedance between the first and second conductive terminals. The detectors include microbolometers, themistors and resistive thermal sensors, each constructed with nanotube fabric. Nanotube fabric detector arrays may be formed for broad-range electromagnetic radiation detecting.
    Type: Application
    Filed: March 12, 2008
    Publication date: October 16, 2008
    Inventors: Jonathan W. Ward, Elwood James Egerton, Rahul Sen, Brent M. Segal
  • Patent number: 7388239
    Abstract: A frame shutter type device provides a separated well in which the storage node is located. The storage node is also shielded by a light shield to prevent photoelectric conversion.
    Type: Grant
    Filed: July 22, 2003
    Date of Patent: June 17, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Eric R. Fossum, Sandor L. Barna
  • Patent number: 7307327
    Abstract: CMOS image sensor having high sensitivity and low crosstalk, particularly at far-red to infrared wavelengths, and a method for fabricating a CMOS image sensor. A CMOS image sensor has a substrate, an epitaxial layer above the substrate, and a plurality of pixels extending into the epitaxial layer for receiving light. The image sensor also includes at least one of a horizontal barrier layer between the substrate and the epitaxial layer for preventing carriers generated in the substrate from moving to the epitaxial layer, and a plurality of lateral barrier layers between adjacent ones of the plurality of pixels for preventing lateral diffusion of electrons in the epitaxial layer.
    Type: Grant
    Filed: August 4, 2005
    Date of Patent: December 11, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Sandeep R. Bahl, Frederick P. LaMaster, David W. Bigelow