Abstract: A photoelectric conversion apparatus comprises multiple photoelectric conversion portions (51) disposed in a semiconductor substrate (5B) wherein each photoelectric conversion portion (51) includes: a P-type charge accumulating area (107) containing a first impurity; and an N-type well portion (102) that, along with the P-type charge accumulating area, configures a photodiode, and each well portion has: an N-type first semiconductor region (102a) containing arsenic at a first density; an N-type second semiconductor region (102b,102C) disposed below the first semiconductor region and containing arsenic at a second density that is lower than the first density; and an N-type third semiconductor region (102d) disposed below the second semiconductor region and containing a second impurity at a third density that is higher than the first density.
Abstract: A semiconductor light-emitting material includes a semiconductor substance including a matrix semiconductor whose constituent atoms are bonded to form a tetrahedral structure, an impurity atom S substituted for an atom in a lattice site of the matrix semiconductor, and an impurity atom I inserted in a interstitial site of the matrix semiconductor, the impurity atom S and the impurity atom I being bonded through charge transfer therebetween in a state that the impurity atom S has an electric charge coincident with that of the constituent atom of the matrix semiconductor and the impurity atom I has an electron configuration of a closed shell structure, in which the semiconductor substance is stretched in a direction of a bond forming the tetrahedral structure.
Abstract: An integrated circuit includes at least one photodiode associated with a read transistor. The photodiode is formed from a stack of three semiconductor layers comprising a buried layer, an floating substrate layer and an upper layer. The drain region and/or the source region of the transistor are incorporated within the upper layer. The buried layer is electrically isolated from the upper layer so as to allow the buried layer to be biased independently of the upper layer.
Abstract: A bipolar junction transistor having an emitter, a base, and a collector includes a stack of one or more layer sets adjacent the collector. Each layer set includes a first material having a first band gap, wherein the first material is highly doped, and a second material having a second band gap narrower than the first band gap, wherein the second material is at most lightly doped.
Type:
Grant
Filed:
August 18, 2008
Date of Patent:
January 11, 2011
Assignee:
HRL Laboratories, LLC
Inventors:
James Chingwei Li, Marko Sokolich, Tahir Hussain, David H. Chow
Abstract: A semiconductor light emitting device includes a multi-layered semiconductor layer having at least a first conductive type cladding layer, an active layer, a second conductive type first cladding layer, an etching stop layer, and a second conductive type second cladding layer on a substrate. An upper section of a ridge groove is formed by an anisotropic etching process, as a first groove in such a way as to have a depth from a surface of the multi-layered semiconductor layer and as not to cross the etching stop layer at the depth. A bottom groove of the ridge groove is formed by an isotropic etching process, as a second groove by performing etching in such a way as to be stopped by the etching stop layer.
Type:
Grant
Filed:
December 8, 2006
Date of Patent:
December 14, 2010
Assignee:
Sony Corporation
Inventors:
Mari Chiba, Hisashi Kudo, Shinichi Agatsuma
Abstract: A double heterojunction bipolar transistor on a substrate comprises a collector formed of InGaAsP, a base in contact with the collector, an emitter in contact with the base, and electrodes forming separate electrical contacts with each of the collector, base, and emitter, respectively. A device incorporates this transistor and an opto-electronic device optically coupled with the collector of the transistor to interact with light transmitted therethrough.
Abstract: A frame shutter type device provides a separated well in which the storage node is located. The storage node is also shielded by a light shield to prevent photoelectric conversion.
Abstract: CMOS image sensor having high sensitivity and low crosstalk, particularly at far-red to infrared wavelengths, and a method for fabricating a CMOS image sensor. A CMOS image sensor has a substrate, an epitaxial layer above the substrate, and a plurality of pixels extending into the epitaxial layer for receiving light. The image sensor also includes at least one of a horizontal barrier layer between the substrate and the epitaxial layer for preventing carriers generated in the substrate from moving to the epitaxial layer, and a plurality of lateral barrier layers between adjacent ones of the plurality of pixels for preventing lateral diffusion of electrons in the epitaxial layer.
Type:
Grant
Filed:
November 15, 2007
Date of Patent:
September 22, 2009
Assignee:
Aptina Imaging Corporation
Inventors:
Sandeep R. Bahl, Fredrick P. LaMaster, David W. Bigelow
Abstract: A photodiode structure including a semiconductor of a first conductivity type, the semiconductor having a main surface, a first well formed in the semiconductor at the main surface thereof, the first well being of a second conductivity type opposite to the first conductivity type. A second well formed in the semiconductor at the main surface thereof laterally outside the first well, the second well being of the second conductivity type, and a first terminal electrically connecting the first well and the second well, and a second terminal connecting the semiconductor such that a depletion region of laterally varying distance to the main surface results from applying a reverse voltage to the first and second terminals.
Abstract: A light sensor located above an integrated circuit including a lower electrode, a heavily-doped amorphous silicon layer of a first conductivity type, and a lightly-doped amorphous silicon layer of a second conductivity type. The lightly-doped amorphous silicon layer rests on a planar surface at least above and in the vicinity of the lower electrode.
Abstract: Electromagnetic radiation detecting and sensing systems using carbon nanotube fabrics and methods of making the same are provided. In certain embodiments of the invention, an electromagnetic radiation detector includes a substrate, a nanotube fabric disposed on the substrate, the nanotube fabric comprising a non-woven network of nanotubes, and first and second conductive terminals, each in electrical communication with the nanotube fabric, the first and second conductive terminals disposed in space relation to one another. Nanotube fabrics may be tuned to be sensitive to a predetermined range of electromagnetic radiation such that exposure to the electromagnetic radiation induces a change in impedance between the first and second conductive terminals. The detectors include microbolometers, themistors and resistive thermal sensors, each constructed with nanotube fabric. Nanotube fabric detector arrays may be formed for broad-range electromagnetic radiation detecting.
Type:
Application
Filed:
March 12, 2008
Publication date:
October 16, 2008
Inventors:
Jonathan W. Ward, Elwood James Egerton, Rahul Sen, Brent M. Segal
Abstract: A frame shutter type device provides a separated well in which the storage node is located. The storage node is also shielded by a light shield to prevent photoelectric conversion.
Abstract: CMOS image sensor having high sensitivity and low crosstalk, particularly at far-red to infrared wavelengths, and a method for fabricating a CMOS image sensor. A CMOS image sensor has a substrate, an epitaxial layer above the substrate, and a plurality of pixels extending into the epitaxial layer for receiving light. The image sensor also includes at least one of a horizontal barrier layer between the substrate and the epitaxial layer for preventing carriers generated in the substrate from moving to the epitaxial layer, and a plurality of lateral barrier layers between adjacent ones of the plurality of pixels for preventing lateral diffusion of electrons in the epitaxial layer.
Type:
Grant
Filed:
August 4, 2005
Date of Patent:
December 11, 2007
Assignee:
Micron Technology, Inc.
Inventors:
Sandeep R. Bahl, Frederick P. LaMaster, David W. Bigelow