Quantum Wire Structures (epo) Patents (Class 257/E29.07)
  • Patent number: 9012887
    Abstract: The present invention relates to growth of III-V semiconductor nanowires (2) on a Si substrate (3). Controlled vertical nanowire growth is achieved by a step, to be taken prior to the growing of the nanowire, of providing group III or group V atoms to a (111) surface of the Si substrate to provide a group III or group V 5 surface termination (4). A nanostructured device including a plurality of aligned III-V semiconductor nanowires (2) grown on, and protruding from, a (111) surface of a Si substrate (3) in an ordered pattern in compliance with a predetermined device layout is also presented.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: April 21, 2015
    Assignee: Qunano AB
    Inventors: Lars Samuelson, Jonas Ohlsson, Thomas Mårtensson, Patrik Svensson
  • Patent number: 8993991
    Abstract: Provided are semiconductor devices and methods of manufacturing the same. The semiconductor device includes a substrate including a first top surface, a second top surface lower in level than the first top surface, and a first perpendicular surface disposed between the first and second top surfaces, a first source/drain region formed under the first top surface, a first nanowire extended from the first perpendicular surface in one direction and being spaced apart from the second top surface, a second nanowire extended from a side surface of the first nanowire in the one direction, being spaced apart from the second top surface, and including a second source/drain region, a gate electrode on the first nanowire, and a dielectric layer between the first nanowire and the gate electrode.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: March 31, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Dongwoo Suh, Sung Bock Kim, Hojun Ryu
  • Patent number: 8993998
    Abstract: An electro-optic device includes a first electrode, an active layer formed over and electrically connected with the first electrode, a buffer layer formed over and electrically connected with the active layer, and a second electrode formed directly on the buffer layer. The second electrode includes a plurality of nanowires interconnected into a network of nanowires. The buffer layer provides a physical barrier between the active layer and the plurality of nanowires to prevent damage to the active layer while the second electrode is formed.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 31, 2015
    Assignee: The Regents of the University of California
    Inventors: Yang Yang, Rui Zhu, Chun Chao Chen, Letian Dou, Gang Li
  • Patent number: 8889564
    Abstract: A mandrel having vertical planar surfaces is formed on a single crystalline semiconductor layer. An epitaxial semiconductor layer is formed on the single crystalline semiconductor layer by selective epitaxy. A first spacer is formed around an upper portion of the mandrel. The epitaxial semiconductor layer is vertically recessed employing the first spacers as an etch mask. A second spacer is formed on sidewalls of the first spacer and vertical portions of the epitaxial semiconductor layer. Horizontal bottom portions of the epitaxial semiconductor layer are etched from underneath the vertical portions of the epitaxial semiconductor layer to form a suspended ring-shaped semiconductor fin that is attached to the mandrel. A center portion of the mandrel is etched employing a patterned mask layer that covers two end portions of the mandrel. A suspended semiconductor fin is provided, which is suspended by a pair of support structures.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: November 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, James J. Demarest, Balasubramanian S. Haran
  • Patent number: 8890115
    Abstract: Vapor-liquid-solid growth of nanowires is tailored to achieve complex one-dimensional material geometries using phase diagrams determined for nanoscale materials. Segmented one-dimensional nanowires having constant composition display locally variable electronic band structures that are determined by the diameter of the nanowires. The unique electrical and optical properties of the segmented nanowires are exploited to form electronic and optoelectronic devices. Using gold-germanium as a model system, in situ transmission electron microscopy establishes, for nanometer-sized Au—Ge alloy drops at the tips of Ge nanowires (NWs), the parts of the phase diagram that determine their temperature-dependent equilibrium composition. The nanoscale phase diagram is then used to determine the exchange of material between the NW and the drop. The phase diagram for the nanoscale drop deviates significantly from that of the bulk alloy.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: November 18, 2014
    Assignee: Brookhaven Science Associates, LLC
    Inventors: Eli Anguelova Sutter, Peter Werner Sutter
  • Patent number: 8816324
    Abstract: Disclosed is a semiconductor device (10) which comprises a glass substrate (12), a lower electrode layer (14), an n-type doped polycrystalline silicon semiconductor layer (16), a low-temperature insulating film (20) in which openings (22, 23) that serve as nuclei for growth of a nanowire (32) are formed, the nanowire (32) that is grown over the low-temperature insulating film (20) and has a core-shell structure, an insulating layer (50) that surrounds the nanowire (32), and an upper electrode layer (52). The nanowire (32) comprises an n-type GaAs core layer and a p-type GaAs shell layer. Alternatively, the nanowire can be formed as a nanowire having a quantum well structure, and InAs that can allow reduction of the process temperature can be used for the nanowire.
    Type: Grant
    Filed: February 23, 2011
    Date of Patent: August 26, 2014
    Assignees: National University Corporation Hokkaido University, Sharp Kabushiki Kaisha
    Inventors: Takashi Fukui, Katsuhiro Tomioka, Junichi Motohisa, Shinjiroh Hara
  • Patent number: 8754401
    Abstract: An Impact Ionization Field-Effect Transistor (I-MOS) device in which device degradation caused by hot carrier injection into a gate oxide is prevented. The device includes source, drain, and gate contacts, and a channel between the source and the drain. The channel has a dimension normal to the direction of a charge carrier transport in the channel such that the energy separation of the first two sub-bands equals or exceeds the effective energy band gap of the channel material.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: June 17, 2014
    Assignee: International Business Machines Corporation
    Inventors: Mikael T Bjoerk, Oliver Hayden, Joachim Knoch, Emanuel Loertscher, Heike E Riel, Walter Heinrich Riess, Heinz Schmid
  • Patent number: 8704204
    Abstract: Disclosed herein are nanoscale devices comprising one or more ferroelectric nanoshells characterized as having an extreme curvature in at least one spatial dimension. Also disclosed are ferroelectric field effect transistors and metal ferroelectric metal capacitors comprising one or more ferroelectric nanoshells. Methods for controlling spontaneous ferroelectric polarization in nanoshell devices are also disclosed.
    Type: Grant
    Filed: December 2, 2009
    Date of Patent: April 22, 2014
    Assignee: Drexel University
    Inventors: Jonathan E. Spanier, Stephen S. Nonnenmann, Oren David Leaffer
  • Patent number: 8569900
    Abstract: A nanowire device includes a nanowire having differently functionalized segments. Each of the segments is configured to interact with a species to modulate the conductance of a segment. The nanowire is grown from a single catalyst and the segments include a first segment at a non-linear angle from a second segment.
    Type: Grant
    Filed: July 20, 2009
    Date of Patent: October 29, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Nathaniel J. Quitoriano, Theodore I. Kamins, Hans S. Cho
  • Publication number: 20130256628
    Abstract: An epitaxial structure is provided. The epitaxial structure comprises a substrate, a carbon nanotube layer and an epitaxial layer stacked in that order. The substrate has an epitaxial growth surface and defines a plurality of first grooves and first bulges on the epitaxial growth surface. The carbon nanotube layer covers the epitaxial growth surface, wherein a first part of the carbon nanotube layer is attached on top surface of the first bulges, and a second part of the carbon nanotube layer is attached on bottom surface and side surface of the first grooves. The epitaxial layer is formed on the epitaxial growth surface, and the carbon nanotube layer is sandwiched between the epitaxial layer and the substrate.
    Type: Application
    Filed: October 9, 2012
    Publication date: October 3, 2013
    Inventors: YANG WEI, SHOU-SHAN FAN
  • Patent number: 8461569
    Abstract: A semiconductor device includes a quantum dot and a plurality of layers, wherein said plurality of layers includes: a first layer; a stressor layer; and a patterned layer wherein said stressor layer overlies said first layer and said patterned layer overlies said stressor layer; wherein said stressor layer has a substantially different lattice constant to said first layer and said patterned layer and has a pit provided in said layer; said quantum dot lying above said patterned layer aligned with said pit.
    Type: Grant
    Filed: May 10, 2011
    Date of Patent: June 11, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Joanna Krystyna Skiba-Szymanska, Andrew James Shields
  • Patent number: 8455857
    Abstract: The present invention relates to semiconductor devices comprising semiconductor nanoelements. In particular the invention relates to devices having a volume element having a larger diameter than the nanoelement arranged in epitaxial connection to the nanoelement. The volume element is being doped in order to provide a high charge carrier injection into the nanoelement and a low access resistance in an electrical connection. The nanoelement may be upstanding from a semiconductor substrate. A concentric layer of low resistivity material forms on the volume element forms a contact.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: June 4, 2013
    Assignee: QuNano AB
    Inventors: Lars Ivar Samuelson, Patrik Svensson, Jonas Ohlsson, Truls Lowgren
  • Patent number: 8450717
    Abstract: A resonant tunneling diode, and other one dimensional electronic, photonic structures, and electromechanical MEMS devices, are formed as a heterostructure in a nanowhisker by forming length segments of the whisker with different materials having different band gaps.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: May 28, 2013
    Assignee: QuNano AB
    Inventors: Lars Ivar Samuelson, Bjorn Jonas Ohlsson
  • Patent number: 8445967
    Abstract: A semiconductor device includes a semiconductor island having at least one electrical dopant atom and encapsulated by dielectric materials including at least one dielectric material layer. At least two portions of the at least one dielectric material layer have a thickness less than 2 nm to enable quantum tunneling effects. A source-side conductive material portion and a drain-side conductive material portion abuts the two portions of the at least one dielectric material layer. A gate conductor is located on the at least one dielectric material layer between the source-side conductive material portion and the drain-side conductive material portion. The potential of the semiconductor island responds to the voltage at the gate conductor to enable or disable tunneling current through the two portions of the at least one dielectric material layer. Design structures for the semiconductor device are also provided.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: May 21, 2013
    Assignee: International Business Machines Corporation
    Inventors: Zhong-Xiang He, Qizhi Liu
  • Patent number: 8421053
    Abstract: A system may include first and second qubits that cross one another and a first coupler having a perimeter that encompasses at least a part of the portions of the first and second qubits, the first coupler being operable to ferromagnetically or anti-ferromagnetically couple the first and the second qubits together. A multi-layered computer chip may include a first plurality N of qubits laid out in a first metal layer, a second plurality M of qubits laid out at least partially in a second metal layer that cross each of the qubits of the first plurality of qubits, and a first plurality N times M of coupling devices that at least partially encompasses an area where a respective pair of the qubits from the first and the second plurality of qubits cross each other.
    Type: Grant
    Filed: March 23, 2009
    Date of Patent: April 16, 2013
    Assignee: D-Wave Systems Inc.
    Inventors: Paul Bunyk, Richard David Neufeld, Felix Maibaum
  • Patent number: 8368049
    Abstract: A nanowire transistor according to the present invention includes: at least one nanowire 13 including a core portion 13a that functions as a channel region and an insulating shell portion 13b that covers the surface of the core portion 13a; source and drain electrodes 14 and 15, which are connected to the nanowire 13; and a gate electrode 21 for controlling conductivity in at least a part of the core portion 13a of the nanowire 13. The core portion 13a is made of semiconductor single crystals including Si and has a cross section with a curved profile on a plane that intersects with the longitudinal axis thereof. The insulating shell portion 13b is made of an insulator including Si and functions as at least a portion of a gate insulating film.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: February 5, 2013
    Assignee: Panasonic Corporation
    Inventors: Takahiro Kawashima, Tohru Saitoh, Kenji Harada, Norishige Nanai, Takayuki Takeuchi
  • Patent number: 8357954
    Abstract: A method for forming a nanowhisker of, e.g., a III-V semiconductor material on a silicon substrate, comprises: preparing a surface of the silicon substrate with measures including passivating the substrate surface by HF etching, so that the substrate surface is essentially atomically flat. Catalytic particles on the substrate surface are deposited from an aerosol; the substrate is annealed; and gases for a MOVPE process are introduced into the atmosphere surrounding the substrate, so that nanowhiskers are grown by the VLS mechanism. In the grown nanowhisker, the crystal directions of the substrate are transferred to the epitaxial crystal planes at the base of the nanowhisker and adjacent the substrate surface.
    Type: Grant
    Filed: May 16, 2011
    Date of Patent: January 22, 2013
    Assignee: QuNano AB
    Inventors: Lars Ivar Samuelson, Thomas M. I. Martensson
  • Patent number: 8350249
    Abstract: A semiconductor device, such as an LED, includes a plurality of first conductivity type semiconductor nanowire cores located over a support, a continuous second conductivity type semiconductor layer extending over and around the cores, a plurality of interstitial voids located in the second conductivity type semiconductor layer and extending between the cores, and first electrode layer that contacts the second conductivity type semiconductor layer and extends into the interstitial voids.
    Type: Grant
    Filed: September 26, 2011
    Date of Patent: January 8, 2013
    Assignee: GLO AB
    Inventor: Patrik Svensson
  • Publication number: 20120313078
    Abstract: Disclosed is a semiconductor device (10) which comprises a glass substrate (12), a lower electrode layer (14), an n-type doped polycrystalline silicon semiconductor layer (16), a low-temperature insulating film (20) in which openings (22, 23) that serve as nuclei for growth of a nanowire (32) are formed, the nanowire (32) that is grown over the low-temperature insulating film (20) and has a core-shell structure, an insulating layer (50) that surrounds the nanowire (32), and an upper electrode layer (52). The nanowire (32) comprises an n-type GaAs core layer and a p-type GaAs shell layer. Alternatively, the nanowire can be formed as a nanowire having a quantum well structure, and InAs that can allow reduction of the process temperature can be used for the nanowire.
    Type: Application
    Filed: February 23, 2011
    Publication date: December 13, 2012
    Inventors: Takashi Fukui, Katsuhiro Tomioka, Junichi Motohisa, Shinjiroh Hara
  • Patent number: 8330143
    Abstract: A nanowire wrap-gate transistor is realized in a semiconductor material with a band gap narrower than Si. The strain relaxation in the nanowires allows the transistor to be placed on a large variety of substrates and heterostructures to be incorporated in the device. Various types of heterostructures should be introduced in the transistor to reduce the output conductance via reduced impact ionization rate, increase the current on/off ratio, reduction of the sub-threshold slope, reduction of transistor contact resistance and improved thermal stability. The parasitic capacitances should be minimized by the use of semi-insulating substrates and the use of cross-bar geometry between the source and drain access regions. The transistor may find applications in digital high frequency and low power circuits as well as in analogue high frequency circuits.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: December 11, 2012
    Assignee: QuNano AB
    Inventors: Lars-Erik Wernersson, Tomas Bryllert, Erik Lind, Lars Samuelson
  • Patent number: 8304757
    Abstract: A semiconductor light-emitting device includes a GaAs substrate; and an active layer provided over the GaAs substrate, the active layer including: a lower barrier layer lattice-matched to the GaAs substrate; a quantum dot provided on the lower barrier layer; a strain relaxation layer covering a side of the quantum dot; and an upper barrier layer contacting the top of the quantum dot, at least a portion of the upper barrier layer contacting the top of the quantum dot being lattice-matched to the GaAs substrate, and having a band gap larger than a band gap of the quantum dot and smaller than a band gap of GaAs.
    Type: Grant
    Filed: September 8, 2010
    Date of Patent: November 6, 2012
    Assignee: Fujitsu Limited
    Inventors: Nobuaki Hatori, Tsuyoshi Yamamoto
  • Patent number: 8298881
    Abstract: In one embodiment, a method of providing a nanowire semiconductor device is provided, in which the gate structure to the nanowire semiconductor device has a trapezoid shape. The method may include forming a trapezoid gate structure surrounding at least a portion of a circumference of a nanowire. The first portion of the trapezoid gate structure that is in direct contact with an upper surface of the nanowire has a first width and a second portion of the trapezoid gate structure that is in direct contact with a lower surface of the nanowire has a second width. The second width of the trapezoid gate structure is greater than the first width of the trapezoid gate structure. The exposed portions of the nanowire that are adjacent to the portion of the nanowire that the trapezoid gate structure is surrounding are then doped to provide source and drain regions.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: October 30, 2012
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey W. Sleight, Sarunya Bangsaruntip, Sebastian U. Engelmann, Ying Zhang
  • Patent number: 8252636
    Abstract: A method of manufacturing at least one nanowire, the nanowire being parallel to its supporting substrate, the method including the formation on the supporting substrate of a structure comprising a bar and two regions, a first end of the bar being secured to one of the two regions and a second end of the bar being secured to the other region, the width of the bar being less than the width of the regions, the subjection of the bar to an annealing under gaseous atmosphere in order to transform the bar into a nanowire, the annealing being carried out under conditions allowing control of the sizing of the neck produced during the formation of the nanowire.
    Type: Grant
    Filed: November 7, 2008
    Date of Patent: August 28, 2012
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Erwan Dornel, Jean-Charles Barbe, Thomas Ernst
  • Patent number: 8242542
    Abstract: A semiconductor device includes a semiconductor island having at least one electrical dopant atom and encapsulated by dielectric materials including at least one dielectric material layer. At least two portions of the at least one dielectric material layer have a thickness less than 2 nm to enable quantum tunneling effects. A source-side conductive material portion and a drain-side conductive material portion abuts the two portions of the at least one dielectric material layer. A gate conductor is located on the at least one dielectric material layer between the source-side conductive material portion and the drain-side conductive material portion. The potential of the semiconductor island responds to the voltage at the gate conductor to enable or disable tunneling current through the two portions of the at least one dielectric material layer. Design structures for the semiconductor device are also provided.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: August 14, 2012
    Assignee: International Business Machines Corporation
    Inventors: Zhong-Xiang He, Qizhi Liu
  • Patent number: 8232561
    Abstract: Embodiments of the invention relate to vertical field effect transistor that is a light emitting transistor. The light emitting transistor incorporates a gate electrode for providing a gate field, a first electrode comprising a dilute nanotube network for injecting a charge, a second electrode for injecting a complementary charge, and an electroluminescent semiconductor layer disposed intermediate the nanotube network and the electron injecting layer. The charge injection is modulated by the gate field. The holes and electrons, combine to form photons, thereby causing the electroluminescent semiconductor layer to emit visible light. In other embodiments of the invention a vertical field effect transistor that employs an electrode comprising a conductive material with a low density of states such that the transistors contact barrier modulation comprises barrier height lowering of the Schottky contact between the electrode with a low density of states and the adjacent semiconductor by a Fermi level shift.
    Type: Grant
    Filed: September 10, 2008
    Date of Patent: July 31, 2012
    Assignee: University of Florida Research Foundation, Inc.
    Inventors: Andrew Gabriel Rinzler, Bo Liu, Mitchell Austin McCarthy, John Robert Reynolds, Franky So
  • Patent number: 8227817
    Abstract: The present invention relates to light emitting diodes comprising at least one nanowire. The LED according to the invention is an upstanding nanostructure with the nanowire protruding from a substrate. A bulb with a larger diameter than the nanowire is arranged in connection to the nanowire and at an elevated position with regards to the substrate. A pn-junction is formed by the combination of the bulb and the nanowire resulting in an active region to produce light.
    Type: Grant
    Filed: December 22, 2007
    Date of Patent: July 24, 2012
    Assignee: QuNano AB
    Inventors: Bo Pedersen, Lars Samuelson, Jonas Ohlsson, Patrik Svensson
  • Patent number: 8198622
    Abstract: A nanowire according to the present invention includes: a nanowire body made of a first material; and a plurality of semiconductor particle made of a second material and being contained in at least a portion of the interior of the nanowire body.
    Type: Grant
    Filed: November 29, 2007
    Date of Patent: June 12, 2012
    Assignee: Panasonic Corporation
    Inventors: Takahiro Kawashima, Tohru Saitoh
  • Patent number: 8193524
    Abstract: An electronic device and method of manufacturing the device. The device includes a semiconducting region, which can be a nanowire, a first contact electrically coupled to the semiconducting region, and at least one second contact capacitively coupled to the semiconducting region. At least a portion of the semiconducting region between the first contact and the second contact is covered with a dipole layer. The dipole layer can act as a local gate on the semiconducting region to enhance the electric properties of the device.
    Type: Grant
    Filed: September 22, 2009
    Date of Patent: June 5, 2012
    Assignee: International Business Machines Corporation
    Inventors: Mikael T Bjoerk, Joachim Knoch, Heike E Riel, Walter Heinrich Riess, Heinz Schmid
  • Patent number: 8193029
    Abstract: A PRAM device includes a lower electrode, a phase-change nanowire and an upper electrode. The phase-change nanowire may be electrically connected to the lower electrode and includes a single element. The upper electrode may be electrically connected to the phase-change nanowires.
    Type: Grant
    Filed: June 9, 2010
    Date of Patent: June 5, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Tae-Yon Lee
  • Publication number: 20120126199
    Abstract: Apparatus and methods for forming the apparatus include nanoparticles, catalyst nanoparticles, carbon nanotubes generated from catalyst nanoparticles, and methods of fabrication of such nanoparticles and carbon nanotubes.
    Type: Application
    Filed: November 18, 2011
    Publication date: May 24, 2012
    Applicant: The Trustees of Columbia University in the City of New York
    Inventors: Stephen O'Brien, Limin Huang, Brian Edward White, Samuel J. Wind
  • Patent number: 8158968
    Abstract: Methods and associated structures of forming microelectronic devices are described. Those methods may include method of forming a layered nanotube structure comprising a wetting layer disposed on a nanotube, a Shottky layer disposed on the wetting layer, a barrier layer disposed on the Shottky layer, and a matrix layer disposed on the barrier layer.
    Type: Grant
    Filed: March 21, 2007
    Date of Patent: April 17, 2012
    Assignee: Intel Corporation
    Inventors: Nachiket Raravikar, Daewoong Suh, Chris Matayabas
  • Patent number: 8154011
    Abstract: A thin film transistor includes a source electrode, a drain electrode, a semiconductor layer, a channel and a gate electrode. The drain electrode is spaced from the source electrode. The gate electrode is insulated from the source electrode, the drain electrode, and the semiconducting layer by an insulating layer. The channel includes a plurality of carbon nanotube wires, one end of each carbon nanotube wire is connected to the source electrode, and opposite end of each the carbon nanotube wire is connected to the drain electrode.
    Type: Grant
    Filed: April 2, 2009
    Date of Patent: April 10, 2012
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Kai-Li Jiang, Qun-Qing Li, Shou-Shan Fan
  • Patent number: 8154010
    Abstract: A memory device includes a first electrode, a second electrode spaced apart from the first electrode and a nanotube or nanowire network disposed between the first electrode and the second electrode, having a stacked structure of a P-type network and an N-type network, and having a diode characteristic. Since the nanotube or nanowire network has the stacked structure of the P-type network and the N-type network, and has the diode characteristic, it is possible to enhance a degree of integration of the memory device and simplify the fabrication processes without separately requiring a selection device.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: April 10, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seung-Hyun Lee
  • Patent number: 8148800
    Abstract: A nanowire-based device and method employ removal of residual carriers. The nanowire-based device includes a semiconductor nanowire having a semiconductor junction, and a residual carrier sink. The residual carrier sink is located at or adjacent to the semiconductor nanowire near the semiconductor junction and employs one or both of enhanced recombination and direct extraction of the residual carriers. The method includes providing a semiconductor nanowire, forming a semiconductor junction within the semiconductor nanowire, forming a residual carrier sink, and removing residual carriers from the semiconductor junction region using the residual carrier sink.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: April 3, 2012
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Theodore I. Kamins
  • Patent number: 8138493
    Abstract: The present invention provides an optoelectronic semiconductor device comprising at least one semiconductor nanowire, wherein the nanowire comprises a nanowire core and at least one shell layer arranged around at least a portion of the nanowire core. The nanowire core and the shell layer form a pn or pin junction that in operation provides an active region for carrier generation or carrier recombination. Quantum dots adapted to act as carrier recombination centres or carrier generation centres are arranged in the active region. By using the nanowire core as template for formation of the quantum dots and the shell layer, quantum dots of homogeneous size and uniform distribution can be obtained. Basically, the optoelectronic semiconductor device can be used for light generation or light absorption.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: March 20, 2012
    Assignee: QuNano AB
    Inventors: Jonas Ohlsson, Lars Samuelson
  • Patent number: 8124961
    Abstract: A single electron transistor includes source/drain layers disposed apart on a substrate, at least one nanowire channel connecting the source/drain layers, a plurality of oxide channel areas in the nanowire channel, the oxide channel areas insulating at least one portion of the nanowire channel, a quantum dot in the portion of the nanowire channel insulated by the plurality of oxide channel areas, and a gate electrode surrounding the quantum dot.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: February 28, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Dae Suk, Kyoung-Hwan Yeo, Ming Li, Yun-Young Yeoh
  • Patent number: 8119430
    Abstract: Provided are a method of manufacturing a semiconductor nanowire sensor device and a semiconductor nanowire sensor device manufactured according to the method. The method includes preparing a first conductive type single crystal semiconductor substrate, forming a line-shaped first conductive type single crystal pattern from the first conductive type single crystal semiconductor substrate, forming second conductive type epitaxial patterns on both sidewalls of the first conductive type single crystal pattern, and forming source and drain electrodes at both ends of the second conductive type epitaxial patterns.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: February 21, 2012
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Chan-Woo Park, Chang-Geun Ahn, Jong-Heon Yang, In-Bok Baek, Chil-Seong Ah, An-Soon Kim, Tae-Youb Kim, Gun-Yong Sung, Seon-Hee Park
  • Patent number: 8115198
    Abstract: In an array R of field-effect transistors for detecting analytes, each transistor of the array comprises a gate G, a semiconductor nanotube or nanowire element NT connected at one end to a source electrode S and at another end to a drain electrode D, in order to form, at each end, a junction J1, J2 with the channel. At least transistors FET1,1, FET1,2 of the array are differentiated by a different conducting material (m1, m2) of the source electrode S and/or drain electrode D.
    Type: Grant
    Filed: May 24, 2006
    Date of Patent: February 14, 2012
    Assignee: Thales and Ecole Polytechnique
    Inventors: Paolo Bondavalli, Pierre Legagneux, Pierre Le Barny, Didier Pribat, Julien Nagle
  • Publication number: 20120018702
    Abstract: Compound semiconductor devices and methods of doping compound semiconductors are provided. Embodiments of the invention provide post-deposition (or post-growth) doping of compound semiconductors, enabling nanoscale compound semiconductor devices including diodes and transistors. In one method, a self-limiting monolayer technique with an annealing step is used to form shallow junctions. By forming a sulfur monolayer on a surface of an InAs substrate and performing a thermal annealing to drive the sulfur into the InAs substrate, n-type doping for InAs-based devices can be achieved. The monolayer can be formed by surface chemistry reactions or a gas phase deposition of the dopant. In another method, a gas-phase technique with surface diffusion is used to form doped regions. By performing gas-phase surface diffusion of Zn into InAs, p-type doping for InAs-based devices can be achieved.
    Type: Application
    Filed: July 26, 2010
    Publication date: January 26, 2012
    Applicant: The Regents of the University of California
    Inventors: Ali Javey, Alexandra C. Ford, Johnny C. Ho
  • Publication number: 20120001153
    Abstract: Exemplary embodiments provide semiconductor devices including high-quality (i.e., defect free) group III-N nanowires and uniform group III-N nanowire arrays as well as their scalable processes for manufacturing, where the position, orientation, cross-sectional features, length and the crystallinity of each nanowire can be precisely controlled. A pulsed growth mode can be used to fabricate the disclosed group III-N nanowires and/or nanowire arrays providing a uniform length of about 10 nm to about 1000 microns with constant cross-sectional features including an exemplary diameter of about 10-1000 nm. In addition, high-quality GaN substrate structures can be formed by coalescing the plurality of GaN nanowires and/or nanowire arrays to facilitate the fabrication of visible LEDs and lasers. Furthermore, core-shell nanowire/MQW active structures can be formed by a core-shell growth on the nonpolar sidewalls of each nanowire.
    Type: Application
    Filed: September 13, 2011
    Publication date: January 5, 2012
    Applicant: STC. UNM
    Inventors: Stephen D. Hersee, Xin Wang, Xinyu Sun
  • Patent number: 8084337
    Abstract: The present invention relates to growth of III-V semiconductor nanowires (2) on a Si substrate (3). Controlled vertical nanowire growth is achieved by a step, to be taken prior of the growing of the nanowire, of providing group III or group V atoms to a (111) surface of the Si substrate to provide a group III or group V 5 surface termination (4). A nanostructured device comprising a plurality of aligned III-V semiconductor nanowires (2) grown on, and protruding from, a (111) surface of a Si substrate (3) in an ordered pattern in compliance with a predetermined device layout is also presented.
    Type: Grant
    Filed: October 27, 2008
    Date of Patent: December 27, 2011
    Assignee: QuNano AB
    Inventors: Lars Samuelson, Jonas Ohlsson, Thomas Mårtensson, Patrik Svensson
  • Patent number: 8049203
    Abstract: The present invention relates to semiconductor devices comprising semiconductor nanoelements. In particular the invention relates to devices having a volume element having a larger diameter than the nanoelement arranged in epitaxial connection to the nanoelement. The volume element is being doped in order to provide a high charge carrier injection into the nanoelement and a low access resistance in an electrical connection. The nanoelement may be upstanding from a semiconductor substrate. A concentric layer of low resistivity material forms on the volume element forms a contact.
    Type: Grant
    Filed: June 15, 2007
    Date of Patent: November 1, 2011
    Assignee: QuNano AB
    Inventors: Lars Ivar Samuelson, Patrik Svensson, Jonas Ohlsson, Truls Lowgren
  • Patent number: 8022393
    Abstract: The disclosure pertains to a method for making a nanoscale filed effect transistor structure on a semiconductor substrate. The method comprises disposing a mask on a semiconductor upper layer of a multi-layer substrate, and removing areas of the upper layer not covered by the mask in a nanowire lithography process. The mask includes two conductive terminals separated by a distance, and a nanowire in contact with the conductive terminals across the distance. The nanowire lithography may be carried out using a deep-reactive-ion-etching, which results in an integration of the nanowire mask and the underlying semiconductor layer to form a nanoscale semiconductor channel for the field effect transistor.
    Type: Grant
    Filed: July 29, 2008
    Date of Patent: September 20, 2011
    Assignee: Nokia Corporation
    Inventor: Alan Colli
  • Patent number: 8008650
    Abstract: An object of the present invention is to provide a new n-type transistor, different from the prior art, using a channel having a nanotube-shaped structure, and having n-type semiconductive properties. To realize this, a film of a nitrogenous compound 6 is formed directly on a channel 5 of a transistor 1 comprising a source electrode 2, a drain electrode 3, a gate electrode 4 and the n-type channel 5 having a nanotube-shaped structure and provided between the source electrode 2 and the drain electrode 3.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: August 30, 2011
    Assignee: Japan Science and Technology Agency
    Inventors: Kazuhiko Matsumoto, Atsuhiko Kojima, Satoru Nagao
  • Publication number: 20110180777
    Abstract: A semiconductor device includes a bonding surface, a semiconducting nanostructure including one of a nanowire and a nanocrystal, which is formed on the bonding surface, and a source electrode and a drain electrode which are formed on the nanostructure such that the nanostructure is electrically connected to the source and drain electrodes.
    Type: Application
    Filed: March 31, 2011
    Publication date: July 28, 2011
    Applicant: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Supratik Guha, Cherie R. Kagan, George S. Tulevski, Emanuel Tutuc
  • Publication number: 20110175059
    Abstract: A plurality of core-shell semiconductor nanowires each being fixed to a support includes II-VI materials for both the cores and the shells. Each nanowire terminates in a free end and a metal alloy nanoparticle is fixed to each nanowire at its free end.
    Type: Application
    Filed: January 19, 2010
    Publication date: July 21, 2011
    Inventors: Keith B. Kahen, Matthew Holland
  • Patent number: 7960251
    Abstract: Disclosed herein is a method for producing nanowires. The method comprises the steps of providing a porous template with a plurality of holes in the form of tubes, filling the tubes with nanoparticles or nanoparticle precursors, and forming the filled nanoparticles or nanoparticle precursors into nanowires. According to the method, highly rectilinear and well-ordered nanowires can be produced in a simple manner.
    Type: Grant
    Filed: June 6, 2006
    Date of Patent: June 14, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byoung Lyong Choi, Jong Min Kim, Eun Kyung Lee
  • Publication number: 20110133169
    Abstract: A method for forming a nanowire tunnel field effect transistor (FET) device includes forming a nanowire suspended by first and second pad regions over a semiconductor substrate, the nanowire including a core portion and a dielectric layer, forming a gate structure around a portion of the dielectric layer, forming a first spacer around portions of the nanowire extending from the gate structure, implanting ions in a first portion of the nanowire, implanting ions in the dielectric layer of a second portion of the nanowire, removing the dielectric layer from the second portion of the nanowire, removing the core portion of the second portion of the exposed nanowire to form a cavity, and epitaxially growing a doped semiconductor material in the cavity from exposed cross sections of the nanowire and the second pad region to connect the exposed cross sections of the nanowire to the second pad region.
    Type: Application
    Filed: December 4, 2009
    Publication date: June 9, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sarunya Bangsaruntip, Josephine B. Chang, Isaac Lauer, Jeffrey W. Sleight
  • Publication number: 20110073839
    Abstract: A high quality II-VI semiconductor nanowire is disclosed. A plurality of II-VI semiconductor nanowires is provided, with each being fixed to a support. Each nanowire terminates in a free end and a metal alloy nanoparticle is fixed to each nanowire at its free end.
    Type: Application
    Filed: September 30, 2009
    Publication date: March 31, 2011
    Inventor: Keith B. Kahen
  • Patent number: 7910932
    Abstract: Disclosed are fully transparent nanowire transistors having high field-effect mobilities. The fully transparent nanowire transistors disclosed herein include one or more nanowires, a gate dielectric prepared from a transparent inorganic or organic material, and transparent source, drain, and gate contacts fabricated on a transparent substrate. The fully transparent nanowire transistors disclosed herein also can be mechanically flexible.
    Type: Grant
    Filed: June 2, 2008
    Date of Patent: March 22, 2011
    Assignees: Northwestern University, Purdue Research Foundation, University of Southern California
    Inventors: Tobin J. Marks, David B. Janes, Sanghyun Ju, Peide Ye, Chongwu Zhou, Antonio Facchetti