Characterized By Materials Of Semiconductor Body (epo) Patents (Class 257/E29.068)

  • Patent number: 9640568
    Abstract: A mask set, a pixel unit and a manufacturing method thereof, an array substrate and a display device are provided to overcome the problem of low brightness of a display screen of a display device. In the pixel unit, the maximum size value of an overlapped area between an active layer and a drain electrode of a thin-film transistor (TFT) in the direction parallel to data line is less than the size value of one side, overlapped with the data line, in an overlapped area between the active layer and a source electrode; and the source electrode is the portion of the data line disposed in an overlapped area between the active layer and the data line. The pixel unit has the advantages of a larger opening area and higher light transmittance. Thus, the brightness of a display screen of the display device comprising the pixel units can be enhanced. Moreover, the problem of screen flicker can be avoided to some extent, and hence the display quality of images can be improved.
    Type: Grant
    Filed: July 4, 2014
    Date of Patent: May 2, 2017
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Yanna Xue, Xue Dong, Xiaochuan Chen, Hailin Xue
  • Patent number: 9299725
    Abstract: A method is provided for forming a circuit-on-wire (CoW) assembly. The method forms a flexible line with a plurality of periodic alignment marks used as a guide to place CoW devices overlying a surface of the flexible line. The CoW devices may be LEDs, capacitors, diodes, photodiodes, resistors, thin-film transistors, or combinations of the above-listed elements. The flexible line may be a conductive material, such as a metal wire, and the periodic alignment marks may be vias formed through the wire. If the flexible line is electrically conductive, an electrically conductive adhesive may be applied to the electrically conductive line, so that an electrical connection is formed between the CoW devices and the electrically conductive line. Subsequent to placing the CON devices, processes may be formed on the flexible line and CoW devices such as lithographic etching and thin-film deposition. An active matrix array using CoW devices is also presented.
    Type: Grant
    Filed: April 18, 2014
    Date of Patent: March 29, 2016
    Assignee: Sharp Laboratories of America, Inc.
    Inventor: Apostolos Voutsas
  • Patent number: 9012958
    Abstract: A semiconductor device of the invention includes an n-GaN layer provided on a substrate, a channel layer provided in contact with the upper surface of the n-GaN layer, an electron supply layer which is provided on the channel layer, and a gate electrode, a source electrode, and a drain electrode which are provided on the electron supply layer. The gate electrode is in contact with an underlying layer made from a nitride semiconductor. The semiconductor device has a ratio defined by the equation L/d1?7, where L is the width of the gate electrode in contact with the underlying layer in a direction between the source electrode and drain electrode; and d1 is the distance between a surface of the n-type gallium nitride layer and a boundary between the gate electrode and the underlying layer.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: April 21, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Kazutaka Inoue
  • Patent number: 9006728
    Abstract: It is an object to provide a semiconductor device having a new productive semiconductor material and a new structure. The semiconductor device includes a first conductive layer over a substrate, a first insulating layer which covers the first conductive layer, an oxide semiconductor layer over the first insulating layer that overlaps with part of the first conductive layer and has a crystal region in a surface part, second and third conductive layers formed in contact with the oxide semiconductor layer, an insulating layer which covers the oxide semiconductor layer and the second and third conductive layers, and a fourth conductive layer over the insulating layer that overlaps with part of the oxide semiconductor layer.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: April 14, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kei Takahashi, Yoshiaki Ito
  • Patent number: 9006732
    Abstract: In an embodiment, an insulating film is formed over a flat surface; a mask is formed over the insulating film; a slimming process is performed on the mask; an etching process is performed on the insulating film using the mask; a conductive film covering the insulating film is formed; a polishing process is performed on the conductive film and the insulating film, so that the conductive film and the insulating film have equal thicknesses; the conductive film is etched, so that a source electrode and a drain electrode which are thinner than the conductive film are formed; an oxide semiconductor film is formed in contact with the insulating film, the source electrode, and the drain electrode; a gate insulating film covering the oxide semiconductor film is formed; and a gate electrode is formed in a region which is over the gate insulating film and overlaps with the insulating film.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: April 14, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideomi Suzawa, Shinya Sasagawa
  • Patent number: 9006736
    Abstract: To give favorable electrical characteristics to a semiconductor device. The semiconductor device includes an insulating layer, a semiconductor layer over the insulating layer, a pair of electrodes over the semiconductor layer and each electrically connected to the semiconductor layer, a gate electrode over the semiconductor layer, and a gate insulating layer between the semiconductor layer and the gate electrode. The insulating layer includes an island-shaped projecting portion. A top surface of the projecting portion of the insulating layer is in contact with a bottom surface of the semiconductor layer, and is positioned on an inner side of the semiconductor layer when seen from above. The pair of electrodes covers part of a top surface and part of side surfaces of the semiconductor layer. Furthermore, the gate electrode and the gate insulating layer cover side surfaces of the projecting portion of the insulating layer.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: April 14, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinya Sasagawa, Motomu Kurata
  • Patent number: 9000591
    Abstract: A conductive film of an embodiment includes: a fine catalytic metal particle as a junction and a graphene extending in a network form from the junction.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: April 7, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuichi Yamazaki, Makoto Wada, Tatsuro Saito, Tadashi Sakai
  • Patent number: 8994021
    Abstract: An oxide semiconductor film which has more stable electric conductivity is provided. The oxide semiconductor film comprises a crystalline region. The oxide semiconductor film has a first peak of electron diffraction intensity with a full width at half maximum of greater than or equal to 0.4 nm?1 and less than or equal to 0.7 nm?1 in a region where a magnitude of a scattering vector is greater than or equal to 3.3 nm?1 and less than or equal to 4.1 nm?1. The oxide semiconductor film has a second peak of electron diffraction intensity with a full width at half maximum of greater than or equal to 0.45 nm?1 and less than or equal to 1.4 nm?1 in a region where a magnitude of a scattering vector is greater than or equal to 5.5 nm?1 and less than or equal to 7.1 nm?1.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: March 31, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masashi Tsubuku, Kengo Akimoto, Hiroki Ohara, Tatsuya Honda, Takatsugu Omata, Yusuke Nonaka, Masahiro Takahashi, Akiharu Miyanaga
  • Patent number: 8975727
    Abstract: A resistor structure incorporated into a resistive switching memory cell with improved performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory cell. A method is also provided for making such a memory cell. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory cell, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory cell. The incorporation of the resistor structure is very useful in obtaining desirable levels of switching currents that meet the switching specification of various types of memory cells. The memory cells may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: March 10, 2015
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Yun Wang, Tony P. Chiang, Imran Hashim, Tim Minvielle, Dipankar Pramanik, Takeshi Yamaguchi
  • Patent number: 8975674
    Abstract: A bridge structure for use in a semiconductor device includes a semiconductor substrate and a semiconductor structure layer. The semiconductor structure layer is formed on a surface of the semiconductor substrate and a lattice difference is formed between the semiconductor structure layer and the semiconductor substrate. The semiconductor structure layer includes at least a first block, at least a second block and at least a third block, wherein the first block and the third block are bonded on the surface of the semiconductor substrate, the second block is floated over the semiconductor substrate and connected with the first block and the third block.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: March 10, 2015
    Assignee: National Applied Research Laboratories
    Inventors: Chun-Lin Chu, Shu-Han Hsu, Guang-Li Luo, Chee-Wee Liu
  • Patent number: 8957416
    Abstract: Disclosed herein is a thin film transistor including: a channel layer made of a crystalline oxide semiconductor having a bixbyte structure, in which (222) planes of the channel layer are roughly parallel to the carrier travel direction.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 17, 2015
    Assignee: Sony Corporation
    Inventor: Mikihiro Yokozeki
  • Patent number: 8932919
    Abstract: A graphene field-effect transistor is disclosed. The graphene field-effect transistor includes a first graphene sheet, a first gate layer coupled to the first graphene sheet and a second graphene sheet coupled to the first gate layer opposite the first gate layer. The first gate layer is configured to influence an electric field within the first graphene sheet as well as to influence an electric field of the second graphene sheet.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: January 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Damon B. Farmer, Aaron D. Franklin, Sataoshi Oida, Joshua T. Smith
  • Patent number: 8927983
    Abstract: Disclosed herein is a thin film transistor array substrate. The thin film transistor array substrate includes a display area and a non-display area. The non-display area includes a signal line, a connecting line and a metal contact. The connecting line is formed in a first patterned metal layer. The signal line and the metal contact are formed in a second patterned metal layer. The connecting line is connected to the signal line by a first through-hole, and the connecting line is connected to the metal contact by a second through-hole. Furthermore, a method of fabricating the thin film transistor array substrate is also disclosed.
    Type: Grant
    Filed: August 19, 2012
    Date of Patent: January 6, 2015
    Assignee: E Ink Holdings Inc.
    Inventors: Wen-Chung Tang, Fang-An Shu, Yao-Chou Tsai, Ted-Hong Shinn
  • Patent number: 8927362
    Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a first region and a second region. The semiconductor device further includes a first buffer layer formed over the substrate and between first and second isolation regions in the first region and a second buffer layer formed over the substrate and between first and second isolation regions in the second region. The semiconductor device further includes a first fin structure formed over the first buffer layer and between the first and second isolation regions in the first region and a second fin structure formed over the second buffer layer and between the first and second isolation regions in the second region. The first buffer layer includes a top surface different from a top surface of the second buffer layer.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: January 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Shi Ning Ju, Cary Chia-Chiung Lo, Huicheng Chang, Chun Chung Su
  • Patent number: 8921849
    Abstract: A power MISFET using an oxide semiconductor is provided. A drain electrode and a gate electrode having a trapezoidal cross section are formed with a semiconductor layer provided therebetween, a semiconductor layer is formed on a side surface of the gate electrode, and a source electrode is in contact with the semiconductor layer at a portion which overlaps with the top of the gate electrode. Between the drain electrode and the source electrode of such a power MISFET, a power source of 500 V or more and a load are connected in series, and a control signal is input to the gate electrode. Other structures and operating methods are also disclosed.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: December 30, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yasuhiko Takemura
  • Patent number: 8901553
    Abstract: The present invention makes it possible to lower the on resistance of a semiconductor element without hindering the function of a diffusion prevention film in a semiconductor device having the semiconductor element that uses a wire in a wiring layer as a gate electrode and has a gate insulation film in an identical layer to the diffusion prevention film. A first wire and a gate electrode are embedded into the surface layer of an insulation layer comprising a first wiring layer. A diffusion prevention film is formed between the first wiring layer and a second wiring layer. A gate insulation film is formed by: forming a recess over the upper face of the diffusion prevention film in the region overlapping with the gate electrode and around the region; and thinning the part.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: December 2, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Naoya Inoue, Kishou Kaneko, Yoshihiro Hayashi
  • Patent number: 8901552
    Abstract: An object is to provide a semiconductor device including an oxide semiconductor film, which has stable electrical characteristics and high reliability. A stack of first and second material films is formed by forming the first material film (a film having a hexagonal crystal structure) having a thickness of 1 nm to 10 nm over an insulating surface and forming the second material film having a hexagonal crystal structure (a crystalline oxide semiconductor film) using the first material film as a nucleus. As the first material film, a material film having a wurtzite crystal structure (e.g., gallium nitride or aluminum nitride) or a material film having a corundum crystal structure (?-Al2O3, ?-Ga2O3, In2O3, Ti2O3, V2O3, Cr2O3, or ?-Fe2O3) is used.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: December 2, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yusuke Nonaka, Takayuki Inoue, Masashi Tsubuku, Kengo Akimoto, Akiharu Miyanaga
  • Patent number: 8890207
    Abstract: System and method for controlling the channel thickness and preventing variations due to formation of small features. An embodiment comprises a fin raised above the substrate and a capping layer is formed over the fin. The channel carriers are repelled from the heavily doped fin and confined within the capping layer. This forms a thin-channel that allows greater electrostatic control of the gate.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: November 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zhiqiang Wu, Ken-Ichi Goto, Wen-Hsing Hsieh, Jon-Hsu Ho, Chih-Ching Wang, Ching-Fang Huang
  • Patent number: 8866147
    Abstract: A semiconductor structure includes a III-nitride substrate and a drift region coupled to the III-nitride substrate along a growth direction. The semiconductor substrate also includes a channel region coupled to the drift region. The channel region is defined by a channel sidewall disposed substantially along the growth direction. The semiconductor substrate further includes a gate region disposed laterally with respect to the channel region.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: October 21, 2014
    Assignee: Avogy, Inc.
    Inventors: Richard J. Brown, Isik C. Kizilyalli, Hui Nie, Andrew P. Edwards, David P. Bour
  • Patent number: 8866138
    Abstract: One embodiment of the present invention provides a highly reliably display device in which a high mobility is achieved in an oxide semiconductor. A first oxide component is formed over a base component. Crystal growth proceeds from a surface toward an inside of the first oxide component by a first heat treatment, so that a first oxide crystal component is formed in contact with at least part of the base component. A second oxide component is formed over the first oxide crystal component. Crystal growth is performed by a second heat treatment using the first oxide crystal component as a seed, so that a second oxide crystal component is formed. Thus, a stacked oxide material is formed. A transistor with a high mobility is formed using the stacked oxide material and a driver circuit is formed using the transistor.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: October 21, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Jun Koyama, Shunpei Yamazaki
  • Patent number: 8853689
    Abstract: A thin film transistor (TFT) structure includes a metal oxide semiconductor layer, a gate, a source, a drain, a gate insulation layer, and a passivation layer. The metal oxide semiconductor layer has a crystalline surface which is constituted by a plurality of grains separated from one another. An indium content of the grains accounts for at least 50% of all metal elements of the metal oxide semiconductor layer. The gate is disposed on one side of the metal oxide semiconductor layer. The source and the drain are disposed on the other side of the metal oxide semiconductor layer. The gate insulation layer is disposed between the gate and the metal oxide semiconductor layer. The passivation layer is disposed on the gate insulation layer, and the crystalline surface of the metal oxide semiconductor layer is in direct contact with the gate insulation layer or the passivation layer.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: October 7, 2014
    Assignee: E Ink Holdings Inc.
    Inventors: Cheng-Hang Hsu, Tzung-Wei Yu, Ted-Hong Shinn
  • Patent number: 8847220
    Abstract: A semiconductor device including an oxide semiconductor can have stable electric characteristics and high reliability. A transistor in which an oxide semiconductor layer containing indium, titanium, and zinc is used as a channel formation region and a semiconductor device including the transistor are provided. As a buffer layer in contact with the oxide semiconductor layer, a metal oxide layer containing an oxide of one or more elements selected from titanium, aluminum, gallium, zirconium, hafnium, and a rare earth element can be used.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: September 30, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8841664
    Abstract: Provided is a highly reliable semiconductor device by giving stable electric characteristics to a transistor in which a semiconductor film whose threshold voltage is difficult to control is used as an active layer. By using a silicon oxide film having a negative fixed charge as a film in contact with the active layer of the transistor or a film in the vicinity of the active layer, a negative electric field is always applied to the active layer due to the negative fixed charge and the threshold voltage of the transistor can be shifted in the positive direction. Thus, the highly reliable semiconductor device can be manufactured by giving stable electric characteristics to the transistor.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: September 23, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hitomi Sato, Takayuki Saito, Kosei Noda, Toru Takayama
  • Patent number: 8835988
    Abstract: The present invention describes a hybrid integrated circuit comprising both CMOS and III-V devices, monolithically integrated in a single chip. It allows the almost complete elimination of the contamination issues related to the integration of different technologies, maintaining at the same time a good planarization of the structure. It further simplifies the fabrication process, allowing the growth of high quality III-V materials on (100) silicon substrates lowering the manufacturing cost. Moreover, differently from many prior art attempts, it does not require silicon on insulator technologies and/or other expensive process steps. This invention enables the consolidation on the same integrated circuit of a hybrid switching power converter that takes advantage of the established circuit topologies of CMOS circuitries and of the higher mobility and voltage withstanding of III-V HEMT devices.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: September 16, 2014
    Assignee: Eta Semiconductor Inc.
    Inventors: Fabio Alessio Marino, Paolo Menegoli
  • Patent number: 8829586
    Abstract: In a miniaturized transistor, a gate insulating layer is required to reduce its thickness; however, in the case where the gate insulating layer is a single layer of a silicon oxide film, a physical limit on thinning of the gate insulating layer might occur due to an increase in tunneling current, i.e. gate leakage current. With the use of a high-k film whose relative permittivity is higher than or equal to 10 is used for the gate insulating layer, gate leakage current of the miniaturized transistor is reduced. With the use of the high-k film as a first insulating layer whose relative permittivity is higher than that of a second insulating layer in contact with an oxide semiconductor layer, the thickness of the gate insulating layer can be thinner than a thickness of a gate insulating layer considered in terms of a silicon oxide film.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: September 9, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuta Endo, Takayuki Saito, Shunpei Yamazaki
  • Patent number: 8823016
    Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer of a first conductivity type and having a major surface, a second semiconductor layer of a second conductivity type, and a light emitting layer provided between the first and second semiconductor layers. The major surface is opposite to the light emitting layer. The first semiconductor layer has structural bodies provided in the major surface. The structural bodies are recess or protrusion. A centroid of a first structural body aligns with a centroid of a second structural body nearest the first structural. hb, rb, and Rb satisfy rb/(2·hb)?0.7, and rb/Rb<1, where hb is a depth of the recess, rb is a width of a bottom portion of the recess, and Rb is a width of the protrusion.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: September 2, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiki Hikosaka, Yoshiyuki Harada, Maki Sugai, Shinya Nunoue
  • Patent number: 8816349
    Abstract: By using a conductive layer including Cu as a long lead wiring, increase in wiring resistance is suppressed. Further, the conductive layer including Cu is provided in such a manner that it does not overlap with the oxide semiconductor layer in which a channel region of a TFT is formed, and is surrounded by insulating layers including silicon nitride, whereby diffusion of Cu can be prevented; thus, a highly reliable semiconductor device can be manufactured. Specifically, a display device which is one embodiment of a semiconductor device can have high display quality and operate stably even when the size or definition thereof is increased.
    Type: Grant
    Filed: October 5, 2010
    Date of Patent: August 26, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Masahiro Takahashi, Hideyuki Kishida, Akiharu Miyanaga, Junpei Sugao, Hideki Uochi, Yasuo Nakamura
  • Patent number: 8809837
    Abstract: A graphene field-effect transistor is disclosed. The graphene field-effect transistor includes a first graphene sheet, a first gate layer coupled to the first graphene sheet and a second graphene sheet coupled to the first gate layer opposite the first gate layer. The first gate layer is configured to influence an electric field within the first graphene sheet as well as to influence an electric field of the second graphene sheet.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: August 19, 2014
    Assignee: International Business Machines Corporation
    Inventors: Damon B. Farmer, Aaron D. Franklin, Sataoshi Oida, Joshua T. Smith
  • Patent number: 8796679
    Abstract: A method of manufacturing an IGZO active layer includes depositing ions including In, Ga, and Zn from a first target, and depositing ions including In from a second target having a different atomic composition from the first target. The deposition of ions from the second target may be controlled to adjust an atomic % of In in the IGZO layer to be about 45 atomic % to about 80 atomic %.
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: August 5, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jong-han Jeong, Jae-kyeong Jeong, Jin-seong Park, Yeon-gon Mo, Hui-won Yang, Min-kyu Kim, Tae-kyung Ahn, Hyun-soo Shin, Hun jung Lee
  • Patent number: 8785924
    Abstract: Disclosed are a high-sensitivity transparent gas sensor and a method for manufacturing the same. The transparent gas sensor includes a transparent substrate, a transparent electrode formed on the transparent substrate and a transparent gas-sensing layer formed on the transparent electrode. The transparent gas-sensing layer has a nanocolumnar structure having nanocolumns formed on the transparent electrode and gas diffusion pores formed between the nanocolumns.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: July 22, 2014
    Assignee: Korea Institute of Science and Technology
    Inventors: Ho Won Jang, Seok Jin Yoon, Jin Sang Kim, Chong Yun Kang, Ji Won Choi, Hi Gyu Moon
  • Patent number: 8778708
    Abstract: There is provided a process for forming a layer of electroactive material having a substantially flat profile. The process includes: providing a workpiece having at least one active area; depositing a liquid composition including the electroactive material onto the workpiece in the active area, to form a wet layer; treating the wet layer on the workpiece at a controlled temperature in the range of ?25 to 80° C. and under a vacuum in the range of 10?6 to 1,000 Torr, for a first period of 1-100 minutes, to form a partially dried layer; heating the partially dried layer to a temperature above 100° C. for a second period of 1-50 minutes to form a dried layer.
    Type: Grant
    Filed: March 8, 2010
    Date of Patent: July 15, 2014
    Assignee: E I du Pont de Nemours and Company
    Inventors: Reid John Chesterfield, Justin Butler, Paul Anthony Sant
  • Patent number: 8772830
    Abstract: A high-quality GaAs-type crystal thin film using an inexpensive Si wafer with good thermal release characteristics is achieved. Provided is a semiconductor wafer comprising an Si wafer; an inhibiting layer that is formed on the wafer and that inhibits crystal growth, the inhibiting layer including a covering region that covers a portion of the wafer and an open region that does not cover a portion of the wafer within the covering region; a Ge layer that is crystal-grown in the open region; a buffer layer that is crystal-grown on the Ge layer and is a group 3-5 compound semiconductor layer containing P; and a functional layer that is crystal-grown on the buffer layer. The Ge layer may be formed then annealing with a temperature and duration that enables movement of crystal defects.
    Type: Grant
    Filed: December 26, 2008
    Date of Patent: July 8, 2014
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Tomoyuki Takada, Sadanori Yamanaka, Masahiko Hata
  • Patent number: 8766318
    Abstract: The objective is to improve capabilities such as high-speed switching of a compound semiconductor device. Provided is a semiconductor wafer comprising a silicon wafer; an insulating film that is formed on the silicon wafer and that has an open portion reaching the silicon wafer; a Ge crystal formed in the open portion; a seed compound semiconductor crystal that is grown with the Ge crystal as a nucleus and that protrudes beyond a surface of the insulating film; and a laterally grown compound semiconductor layer that is laterally grown on the insulating film with a specified surface of the seed compound semiconductor crystal as a seed surface.
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: July 1, 2014
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Masahiko Hata, Tomoyuki Takada
  • Patent number: 8766230
    Abstract: Non-volatile multi-bit memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region; and a gate stack structure over the substrate and between the source region and drain region. The gate stack structure includes a first solid electrolyte cell and a second solid electrolyte cell. The solid electrolyte cells having a capacitance that is controllable between at least two states. A gate contact layer is electrically coupled to a voltage source. The first solid electrolyte cell and the second solid electrolyte cell separate the gate contact layer from the substrate.
    Type: Grant
    Filed: August 17, 2010
    Date of Patent: July 1, 2014
    Assignee: Seagate Technology LLC
    Inventors: Xuguang Wang, Shuiyuan Huang, Dimitar V. Dimitrov, Michael Xuefei Tang, Song S. Xue
  • Patent number: 8765028
    Abstract: Provided are a composition for an oxide semiconductor, a method of preparing the composition, methods of forming an oxide semiconductor thin film and an electronic device using the composition. The composition for an oxide semiconductor includes a tin compound, a zinc compound, and a low electronegativity metal compound containing a metal with an electronegativity lower than zinc.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: July 1, 2014
    Assignee: Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Hyun Jae Kim, You Seung Rim, Dong Lim Kim
  • Patent number: 8748889
    Abstract: It is an object to manufacture a semiconductor device in which a transistor including an oxide semiconductor has normally-off characteristics, small fluctuation in electric characteristics, and high reliability. First, first heat treatment is performed on a substrate, a base insulating layer is formed over the substrate, an oxide semiconductor layer is formed over the base insulating layer, and the step of performing the first heat treatment to the step of forming the oxide semiconductor layer are performed without exposure to the air. Next, after the oxide semiconductor layer is formed, second heat treatment is performed. An insulating layer from which oxygen is released by heating is used as the base insulating layer.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: June 10, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshinari Sasaki, Hitomi Sato, Kosei Noda, Yuta Endo, Mizuho Ikarashi, Keitaro Imai, Atsuo Isobe, Yutaka Okazaki
  • Patent number: 8748916
    Abstract: A light emitting device includes a conductive substrate, a plurality of light emitting cells disposed on the conductive substrate, wherein each of the plurality of light emitting device cells includes a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer, a protective layer disposed to cover a side of the first semiconductor layer and a side of the active layer, and a first electrode for connecting the second semiconductor layers of more than one of the light emitting cells to each other, wherein the protective layer includes protruding portions extending to an inside of each of the light emitting cells from the side of the first semiconductor layer and the side of the active layer.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: June 10, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventor: Hwan Hee Jeong
  • Patent number: 8742393
    Abstract: The SrTiO3 buffer layer is formed by lamination of the Sr2+O2? layer and the Ti4+O24? layer. The surface of the buffer layer is terminated with the Ti4+O24? layer. On the buffer layer, a LaAlO3 thin film layer is formed. The thin film layer includes a La3+O2? layer and an Al3+O24? layer alternately laminated in order on the SrTiO3 buffer layer.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: June 3, 2014
    Assignee: Tokyo Institute of Technology
    Inventors: Tomofumi Susaki, Hideo Hosono
  • Patent number: 8735866
    Abstract: A high-voltage electronic device comprising high-voltage electrodes, located in a dielectric envelope with an internal surface coated with a material having a conductivity which is greater than the conductivity of the envelope, characterized in that the areas subject to high field strength are coated with composite material, based on a polycrystalline material with a bulk conductivity of particles 10?9 to 10?13 Ohm?1 cm?1, each of which contains a surface nanolayer of bonding inorganic material. The high-voltage electrodes may be placed in a vacuum envelope and fixed on coated insulators. Preferred coating materials include materials from a group of materials comprising; oxides of chromium, boron or zirconium in the form of polycrystalline porous substance with a particle size of 30 nm-30 microns, connected to each other with an inorganic material, for instance silicon oxide (SiO2) with a layer thickness not more than 100 nm.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: May 27, 2014
    Inventor: Viktor D. Bochkov
  • Patent number: 8735896
    Abstract: According to present invention, system on panel without complicating the process of TFT can be realized, and a light-emitting device that can be formed by lower cost than that of the conventional light-emitting device can be provided. A light-emitting device is provided in which a pixel portion is provided with a pixel including a light-emitting element and a TFT for controlling supply of current to the light-emitting element; a TFT included in a drive circuit and a TFT for controlling supply of current to the light-emitting element include a gate electrode, a gate insulating film formed over the gate electrode, a first semiconductor film, which overlaps with the gate electrode via the gate insulating film, a pair of second semiconductor films formed over the first semiconductor film; the pair of second semiconductor films are doped with an impurity to have one conductivity type; and the first semiconductor film is formed by semiamorphous semiconductor.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: May 27, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8735903
    Abstract: Layer structures for use in density of states (“DOS”) engineered FETs are described. One embodiment comprises a layer structure for use in fabricating an n-channel transistor. The layer structure includes a first semiconductor layer having a conduction band minimum EC1; a second semiconductor layer having a discrete hole level H0; a wide bandgap semiconductor barrier layer disposed between the first and the second semiconductor layers; a gate dielectric layer disposed above the first semiconductor layer; and a gate metal layer disposed above the gate dielectric layer; wherein the discrete hole level H0 is positioned below the conduction band minimum Ec1 for zero bias applied to the gate metal layer.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: May 27, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Matthias Passlack
  • Patent number: 8735188
    Abstract: An atomic layer deposition apparatus and a sealing method of an organic light emitting device using the same are disclosed. In one embodiment, the atomic layer deposition apparatus improves a structure of the purge gas injection nozzle so as to increase the exhaust efficiency of the purge gas in an atomic layer deposition process, which increases a speed of a purge process. As a result, it is possible to improve a deposition speed and a quality of a sealing film when a sealing process for sealing the organic light emitting device is implemented by using the atomic layer deposition.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: May 27, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seung-Hun Kim, Sang-Joon Seo, Jin-Kwang Kim, Jun-Hyuk Cheon
  • Patent number: 8728861
    Abstract: A method is provided for fabricating a thin film transistor. A plurality of layers is deposited on a substrate. The plurality of layers includes a conductive gate contact layer, a gate insulator layer, an undoped channel layer, an etch-stop layer, and a conductive contact layer. The etch-stop layer is positioned between the conductive contact layer and the undoped channel layer. A portion of the conductive contact layer is selectively removed while removal of a portion of the undoped channel layer is prevented by the etch-stop layer during the selective removal. A portion of the etch-stop layer is selectively removed and an exposed portion of the etch-stop layer is converted from a conductor to an insulator by oxidizing the exposed portion of the etch-stop layer in air. A portion of remaining layers of the plurality of layers is selectively removed to form the thin film transistor.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: May 20, 2014
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: Burhan Bayraktaroglu, Kevin Leedy
  • Patent number: 8729566
    Abstract: A semiconductor switching arrangement includes a normally on semiconductor component of a first conduction type and a normally off semiconductor component of a second conduction type which is the complement of the first conduction type. A load path of the normally off semiconductor component is connected in series with the load path of the normally on semiconductor component. A first actuation circuit connected between the control connection of the normally on semiconductor component and a load path connection of the normally on semiconductor component. The load path connection of the normally on semiconductor component is arranged between the normally on and normally off semiconductor components. A second actuation circuit is connected between the control connection of the normally off semiconductor component and a load path connection of the normally off semiconductor component.
    Type: Grant
    Filed: April 14, 2011
    Date of Patent: May 20, 2014
    Assignee: Infineon Technologies AG
    Inventors: Daniel Domes, Uwe Jansen
  • Patent number: 8729670
    Abstract: Provided is a semiconductor substrate and a method for manufacturing the same. The semiconductor substrate includes a substrate, a discontinuously formed hemispheric metal layer on the substrate, and a semiconductor layer on the hemispheric metal layer. A plurality of voids on the interface of the substrate and discontinuous hemisphere are formed to absorb or relax the stain of interface. Accordingly, even if a subsequent layer is relatively thickly formed on the substrate, substrate bow or warpage can be minimized.
    Type: Grant
    Filed: April 15, 2009
    Date of Patent: May 20, 2014
    Assignee: Lumigntech Co., Ltd.
    Inventors: Hae Yong Lee, Young Jun Choi, Jung Gyu Kim
  • Publication number: 20140131768
    Abstract: A bridge structure for use in a semiconductor device includes a semiconductor substrate and a semiconductor structure layer. The semiconductor structure layer is formed on a surface of the semiconductor substrate and a lattice difference is formed between the semiconductor structure layer and the semiconductor substrate. The semiconductor structure layer includes at least a first block, at least a second block and at least a third block, wherein the first block and the third block are bonded on the surface of the semiconductor substrate, the second block is floated over the semiconductor substrate and connected with the first block and the third block.
    Type: Application
    Filed: November 9, 2012
    Publication date: May 15, 2014
    Applicant: National Applied Research Laboratories
    Inventors: Chun-Lin Chu, Shu-Han Hsu, Guang-Li Luo, Chee-Wee Liu
  • Patent number: 8723172
    Abstract: A display device including a thin film transistor array substrate, transparent electrode substrate and a display medium layer disposed therebetween is provided. The thin film transistor array substrate includes a plurality of thin film transistors with an oxide semiconductor layer respectively. In each thin film transistor, a gate electrode and a gate insulating layer are disposed on a substrate sequentially and the gate electrode is covered by the gate insulating layer. The oxide semiconductor layer is conformably covering on the gate insulating layer and has a channel region located above the gate electrode. A source electrode and a drain electrode of each thin film transistor are disposed on the oxide semiconductor layer and at one side of the channel region respectively. Since the oxide semiconductor layer is made of transparent material, the patterning process of the oxide semiconductor layer can be omitted during the manufacturing process of the reflective display device.
    Type: Grant
    Filed: February 3, 2010
    Date of Patent: May 13, 2014
    Assignee: E Ink Holdings Inc.
    Inventors: Fang-An Shu, Lee-Tyng Chen, Henry Wang, Wei-Chou Lan, Tung-Liang Lin
  • Patent number: 8723173
    Abstract: The semiconductor device includes a first conductive layer over a substrate; an oxide semiconductor layer which covers the first conductive layer; a second conductive layer in a region which is not overlapped with the first conductive layer over the oxide semiconductor layer; an insulating layer which covers the oxide semiconductor layer and the second conductive layer; and a third conductive layer in a region including at least a region which is not overlapped with the first conductive layer or the second conductive layer over the insulating layer.
    Type: Grant
    Filed: September 22, 2010
    Date of Patent: May 13, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kei Takahashi, Yoshiaki Ito
  • Patent number: 8716106
    Abstract: A method for producing a bonded substrate having a Si1-xGex (0<x?1) film in which a larger than ever biaxial strain has been introduced. Specifically, the method involves at least the steps of: providing a donor wafer and a handle wafer having a thermal expansion coefficient lower than the donor wafer, implanting ions of any one or both of hydrogen and a noble gas into the donor wafer to form an ion-implanted layer, performing a plasma activation treatment on at least one of bonding surfaces of the donor wafer and the handle wafer, bonding the donor wafer to the handle wafer, splitting the donor wafer through application of a mechanical impact to the ion-implanted layer, performing a surface treatment on a split surface of the donor wafer, and epitaxially growing a Si1-xGex (0<x?1) film on the split surface to thus form a strained Si1-xGex (0<x?1) film on the bonded wafers.
    Type: Grant
    Filed: November 27, 2008
    Date of Patent: May 6, 2014
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventor: Shoji Akiyama
  • Patent number: RE47455
    Abstract: A liquid crystal display includes first and second gate lines and first and second data lines, on a first substrate, a first thin film transistor connected to the first gate and data lines and including a first source and drain electrode, a second thin film transistor connected to the second gate and data lines and including a second source and drain electrode, first and second pixel electrodes contacting a portion of the first and second drain electrodes, respectively, a passivation layer on the first and second pixel electrodes and the first and second thin film transistors, and a reference electrode on a passivation layer and overlapping the first pixel electrode and the second pixel electrode. The reference electrode includes a plurality of branch electrodes. The first thin film transistor is right of the first data line and the second thin film transistor is left of the second data line.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: June 25, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hyun-Wuk Kim, Jang-Kun Song, Seon-Ah Cho, Eun-Je Jang, You-Sik Shin