Abstract: Disclosed is a resistive switching element. The resistive switching element includes a first oxide layer and a second oxide layer stacked one on top of the other such that an interface is present therebetween, wherein the first oxide layer and the second oxide layer are made of different metal oxides; two-dimensional electron gas (2DEG) present in the interface between the first oxide layer and the second oxide layer and functioning as an inactive electrode; and an active electrode disposed on the second oxide layer, wherein when a positive bias is applied to the active electrode, an electric field is generated between the active electrode and the two-dimensional electron gas, such that the second oxide layer is subjected to the electric field, and active metal ions from the active electrode are injected into the second oxide layer. The resistive switching element realizes highly uniform resistive switching operation.

Abstract: The present invention provides practical methods for n-type doping of graphene, either during graphene synthesis or following the formation of graphene. Some variations provide a method of n-type doping of graphene, comprising introducing a phosphorus-containing dopant fluid to a surface of graphene, under effective conditions to dope the graphene with phosphorus atoms or with phosphorus-containing molecules or fragments. It has been found that substitutional doping with phosphine can effectively modulate the electrical properties of graphene, such as graphene supported on Si or SiC substrates. Graphene sheet resistances well below 200 ohm/sq, and sheet carrier concentrations above 5×1013 cm?2, have been observed experimentally for n-doped graphene produced by the disclosed methods. This invention provides n-doped graphene for various electronic-device applications.

Abstract: Provided is an oxide electronic device, including: an oxide substrate; an oxide thin film layer formed on the oxide substrate and containing an oxide that is heterogeneous with respect to the oxide substrate; and a ferroelectric layer formed on the oxide thin film layer and controlling electric conductivity of two-dimensional electron gas (2DEG) generated at an interface between the oxide substrate and the oxide thin film layer. Provided also is a method for manufacturing an oxide electronic device, including: depositing, on an oxide substrate, an oxide that is heterogeneous with respect to the oxide substrate to form an oxide thin film layer; and forming a ferroelectric layer on the oxide thin film layer, wherein the ferroelectric layer controls electric conductivity of 2DEG generated at an interface between the oxide substrate and the oxide thin film layer.

Abstract: A light emitting diode includes a graphene layer, a first semiconductor layer, an active layer, a second semiconductor layer, a first electrode and a second electrode. The first semiconductor layer, the active layer, and the second semiconductor layer are stacked with each other in sequence. The first electrode is located on and electrically connected with the second semiconductor layer. The second electrode is located on and electrically connected with the first semiconductor layer. The graphene layer is located on at least one of the first semiconductor layer and the second semiconductor layer.

Abstract: A light emitting diode includes a substrate, graphene layer, a first semiconductor layer, an active layer, a second semiconductor layer, a first electrode and a second electrode. The first semiconductor layer is on the epitaxial growth layer of the substrate. The active layer is between the first semiconductor layer and the second semiconductor layer. The first electrode is electrically connected with the second semiconductor layer and the second electrode electrically is connected with the second part of the carbon nanotube layer. The graphene layer is located on at least one of the first semiconductor layer and the second semiconductor layer.

Abstract: A light emitting diode includes a substrate, graphene layer, a first semiconductor layer, an active layer, a second semiconductor layer, a first electrode, a second electrode, and a reflection layer. The first semiconductor layer, the active layer, and the second semiconductor layer are stacked on the substrate in sequence. The first electrode is electrically connected with the second semiconductor layer and the second electrode electrically is connected with the second part of the carbon nanotube layer. The graphene layer is located on at least one of the first semiconductor layer and the second semiconductor layer. The reflection layer covers the second semiconductor layer.

Abstract: A semiconductor device includes a first device and a second device, which are implemented laterally next to each other in a substrate. A recombination zone is implemented in the substrate between the first device and the second device, so that diffusing charge carriers recombine between the first device and the second device.

Abstract: Provided are a non-volatile memory device and a cross-point memory array including the same which have a diode characteristic enabling the non-volatile memory device and the cross-point memory array including the same to operate in a simple structure, without requiring a switching device separately formed so as to embody a high density non-volatile memory device. The non-volatile memory device includes a first electrode; a diode-storage node formed on the first electrode; and a second electrode formed on the diode-storage node.

Abstract: A semiconductor memory device and a method for accessing the same are disclosed. The semiconductor memory device includes an oxide heterojunction transistor which includes: an oxide substrate; an oxide film on the oxide substrate, wherein an interfacial layer between the oxide substrate and the oxide film behaves like two-dimensional electron gas; a source electrode and a drain electrode being located on the oxide film and electrically connected with the interfacial layer; a front gate on the oxide film; and a back gate on a lower surface of the oxide substrate, wherein the source electrode and the drain electrode of the oxide heterojunction transistor are respectively connected with a first word line and a first bit line for reading operation, and wherein the front gate and the back gate are respectively connected with a second word line and a second bit line for writing operation.

Abstract: A method and an apparatus for doping a graphene or nanotube thin-film field-effect transistor device to improve electronic mobility. The method includes selectively applying a dopant to a channel region of a graphene or nanotube thin-film field-effect transistor device to improve electronic mobility of the field-effect transistor device.

Abstract: Methods of forming and tuning a multilayer select device are provided, along with apparatus and systems which include them. As is broadly disclosed in the specification, one such method can include forming a first region having a first conductivity type; forming a second region having a second conductivity type and located adjacent to the first region; and forming a third region having the first conductivity type and located adjacent to the second region and, such that the first, second and third regions form a structure located between a first electrode and a second electrode, wherein each of the regions have a thickness configured to achieve a current density in a range from about 1×e4 amps/cm2 up to about 1×e8 amps/cm2 when a voltage in a selected voltage range is applied between the first electrode and the second electrode.

Abstract: Methods of forming and tuning a multilayer select device are provided, along with apparatus and systems which include them. As is broadly disclosed in the specification, one such method can include forming a first region having a first conductivity type; forming a second region having a second conductivity type and located adjacent to the first region; and forming a third region having the first conductivity type and located adjacent to the second region and, such that the first, second and third regions form a structure located between a first electrode and a second electrode, wherein each of the regions have a thickness configured to achieve a current density in a range from about 1×e4 amps/cm2 up to about 1×e8 amps/cm2 when a voltage in a selected voltage range is applied between the first electrode and the second electrode.

Abstract: First and second synthetic diamond regions are doped with boron. The second synthetic diamond region is doped with boron to a greater degree than the first synthetic diamond region, and in physical contact with the first synthetic diamond region. In a further example embodiment, the first and second synthetic diamond regions form a diamond semiconductor, such as a Schottky diode when attached to at least one metallic lead.

Abstract: A device and method for semiconductor fabrication includes forming a buffer layer on a semiconductor substrate and depositing an amorphous elemental layer on the buffer layer. Elements of the elemental layer are diffused through the buffer layer and into the semiconductor layer.

Abstract: A semiconductor graphene is used for a channel layer, and a metal graphene is used for electrode layers for a source, a drain, and a gate which serve as interconnections as well. An oxide is used for a gate insulating layer. The channel layer and the electrode layers are located on the same plane.

Abstract: A graphene transparent electrode, which comprises: at least one graphene sheet; wherein the graphene sheets electrically connect with each other by overlapping with each other, each of the graphene sheets has a diameter from 10 ?m to 1 mm, the quantity of the graphene sheets in the graphene transparent electrode is from 1 to 1000, the electrical resistance of the graphene transparent electrode is 1 ?/cm or below, and the light transmittance of the graphene transparent electrode is 70% or above. A graphene light emitting diode (gLED) and a method of fabricating the same are also disclosed.

Abstract: A silicon substrate is manufactured from a single crystal silicon that is doped with phosphorus (P) and is grown by a CZ method to have a predetermined carbon concentration and a predetermined initial oxygen concentration. An n+ epitaxial layer or an n+ implantation layer that is doped with phosphorus (P) at a predetermined concentration or more is formed on the silicon substrate. An n epitaxial layer that is doped with phosphorus (P) at a predetermined concentration is formed on the n+ layer.

Abstract: Semiconductor devices including a light emitting layer, and at least one surface plasmon metal layer in contact with the light emitting layer are provided. The light emitting layer includes an active layer having a first band gap, and one or more barrier layers having a second band gap. The first band gap is smaller than the second band gap. Methods for fabricating semiconductor devices are also provided.

Abstract: A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of dopant elements. Selection of a plurality of dopant elements includes selecting a first dopant element with a first atomic radius larger than a host matrix atomic radius and selecting a second dopant element with a second atomic radius smaller than a host matrix atomic radius. The methods and devices further include selecting amounts of each dopant element of the plurality of dopant elements wherein amounts and atomic radii of each of the plurality of dopant elements complement each other to reduce a host matrix lattice strain. The methods and devices further include introducing the plurality of dopant elements to a selected region of the host matrix and annealing the selected region of the host matrix.

Abstract: Embodiments of the present invention provide a method that cools a substrate to a temperature below 10° C. and then implants ions into the substrate while the temperature of the substrate is below 10° C. The implanting causes damage to a first depth of the substrate to create an amorphized region in the substrate. The method forms a layer of metal on the substrate and heats the substrate until the metal reacts with the substrate and forms a silicide region within the amorphized region of the substrate. The depth of the silicide region is at least as deep as the first depth.

Abstract: Methods of making Si-containing films that contain relatively high levels of Group III or Group V dopants involve chemical vapor deposition using trisilane and a dopant precursor. Extremely high levels of substitutional incorporation may be obtained, including crystalline silicon films that contain at least about 3×1020 atoms cm?3 of an electrically active dopant. Substitutionally doped Si-containing films may be selectively deposited onto the crystalline surfaces of mixed substrates by introducing an etchant gas during deposition.

Abstract: A semiconductor graphene is used for a channel layer, and a metal graphene is used for electrode layers for a source, a drain, and a gate which serve as interconnections as well. An oxide is used for a gate insulating layer. The channel layer and the electrode layers are located on the same plane.

Abstract: A method for growing an epitaxial layer patterns a mask over a substrate. The mask protects first areas (N-type areas) of the substrate where N-type field effect transistors (NFETs) are to be formed and exposes second areas (P-type areas) of the substrate where P-type field effect transistors (PFETs) are to be formed. Using the mask, the method can then epitaxially grow the Silicon Germanium layer only on the P-type areas. The mask is then removed and shallow trench isolation (STI) trenches are patterned (using a different mask) in the N-type areas and in the P-type areas. This STI patterning process positions the STI trenches so as to remove edges of the epitaxial layer. The trenches are then filled with an isolation material. Finally, the NFETs are formed to have first metal gates and the PFETs are formed to have second metal gates that are different than the first metal gates. The first metal gates have a different work function than the second metal gates.

Abstract: A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of dopant elements. Selection of a plurality of dopant elements includes selecting a first dopant element with a first atomic radius larger than a host matrix atomic radius and selecting a second dopant element with a second atomic radius smaller than a host matrix atomic radius. The methods and devices further include selecting amounts of each dopant element of the plurality of dopant elements wherein amounts and atomic radii of each of the plurality of dopant elements complement each other to reduce a host matrix lattice strain. The methods and devices further include introducing the plurality of dopant elements to a selected region of the host matrix and annealing the selected region of the host matrix.

Abstract: Semiconductor wafer of monocrystalline silicon contain fluorine, the fluorine concentration being 1·1010 to 1·1016 atoms/cm3, and is free of agglomerated intrinsic point defects whose diameter is greater than or equal to a critical diameter. The semiconductor wafers are produced by providing a melt of silicon which is doped with fluorine, and crystallizing the melt to form a single crystal which contains fluorine within the range of 1·1010 to 1·1016 atoms/cm3, at a growth rate at which agglomerated intrinsic point defects having a critical diameter or larger would arise if fluorine were not present or present in too small an amount, and separating semiconductor wafers from the single crystal.

Abstract: A silicon substrate is manufactured from a single crystal silicon that is doped with phosphorus (P) and is grown by a CZ method to have a predetermined carbon concentration and a predetermined initial oxygen concentration. An n+ epitaxial layer or an n+ implantation layer that is doped with phosphorus (P) at a predetermined concentration or more is formed on the silicon substrate. An n epitaxial layer that is doped with phosphorus (P) at a predetermined concentration is formed on the n+ layer.

Abstract: The aim of the invention is to improve the energy yield efficiency of solar cells. According to the invention, the silicon material is doped with one or more different lanthanides such that said material penetrates into a layer approximately 60 nm deep. Photons, whose energy is at least double that of the 1.2 eV silicon material band gap, are thus converted into at least two photons having energy in the region of the silicon band gap, by excitation and recombination of the unpaired 4f electrons of the lanthanides. As a result, additional photons having advantageous energy close to the silicon band gap are provided for electron-hole pair formation.

Abstract: A substrate 103 is set in a film-forming apparatus, such as a metal organic vapor phase epitaxy system 101, and a GaN buffer film 105, an undoped GaN film 107, and a GaN film 109 containing a p-type dopant are successively grown on the substrate 103 to form an epitaxial substrate E1. The semiconductor film 109 also contains hydrogen, which was included in a source gas, in addition to the p-type dopant. Then the epitaxial substrate E1 is placed in a short pulsed laser beam emitter 111. A laser beam LB1 is applied to a part or the whole of a surface of the epitaxial substrate E1 to activate the p-type dopant by making use of a multiphoton absorption process. When the substrate is irradiated with the pulsed laser beam LB1 which can induce multiphoton absorption, a p-type GaN film 109a is formed. There is thus provided a method of optically activating the p-type dopant in the semiconductor film to form the p-type semiconductor region, without use of thermal annealing.

Abstract: A method is provided capable of universally controlling the proximity gettering structure, the need for which can vary from manufacturer to manufacturer, by arbitrarily controlling an M-shaped distribution in a depth direction of a wafer BMD density after RTA in a nitrogen-containing atmosphere. The heat-treatment method is provided for forming a desired internal defect density distribution by controlling a nitrogen concentration distribution in a depth direction of the silicon wafer for heat-treatment, the method including heat-treating a predetermined silicon wafer used for manufacturing a silicon wafer having a denuded zone in the vicinity of the surface thereof.

Abstract: A bulk-doped semiconductor that is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers. Such a semiconductor may comprise an interior core comprising a first semiconductor; and an exterior shell comprising a different material than the first semiconductor. Such a semiconductor may be elongated and may have, at any point along a longitudinal section of such a semiconductor, a ratio of the length of the section to a longest width is greater than 4:1, or greater than 10:1, or greater than 100:1, or even greater than 1000:1.