Abstract: A phase change memory cell includes a first contact, a phase change region above and in contact with the first contact, an electrode region, and a second contact above and in contact with the electrode region. The phase change region surrounds the electrode region. The electrode region has a first surface in contact with the phase change region and a second surface in contact with the second contact, and the second surface is wider than the first surface.

Abstract: A memory device includes a first conductor, a diode, a memory element, and a second conductor arranged in series. The diode includes a first semiconductor layer over and in electrical communication with the first conductor. A patterned insulating layer has a sidewall over the first semiconductor layer. The diode includes an intermediate semiconductor layer on a first portion of the sidewall, and in contact with the first semiconductor layer. The intermediate semiconductor layer has a lower carrier concentration than the first semiconductor layer, and can include an intrinsic semiconductor. A second semiconductor layer on a second portion of the sidewall, and in contact with the intermediate semiconductor layer, has a higher carrier concentration than the intermediate semiconductor layer. A memory element is electrically coupled to the second semiconductor layer. The second conductor is electrically coupled to the memory element.

Abstract: An array of phase change memory cells is manufactured by forming a separation layer over an array of contacts, forming a patterning layer on the separation layer and forming an array of mask openings in the patterning layer using lithographic process. Etch masks are formed within the mask openings by a process that compensates for variation in the size of the mask openings that result from the lithographic process. The etch masks are used to etch through the separation layer to define an array of electrode openings exposing the underlying contacts. Electrode material is deposited within the electrode openings; and memory elements are formed over the bottom electrodes. Finally, bit lines are formed over the memory elements to complete the memory cells. In the resulting memory array, the critical dimension of the top surface of bottom electrode varies less than the width of the memory elements in the mask openings.

Abstract: On a first structure having a first dielectric layer, a second dielectric layer, and a third dielectric layer a crown is formed through the third dielectric layer and the second dielectric layer. A fourth dielectric layer is deposited over the first structure and thereby is over the crown. A portion of the fourth dielectric layer is removed to form a first spacer having a remaining portion of the fourth dielectric layer. A portion of the third electric layer is also removed during the removal of the portion the fourth dielectric layer, resulting in a second spacer having a remaining portion of the third dielectric layer. A second structure is thereby formed. A phase change material layer is deposited over the second structure. An electrode layer is deposited over the phase change layer.

Abstract: A phase change memory device having a heater that exhibits a temperature dependent resistivity which provides a way of reducing a reset current is presented. The phase change memory device includes a phase change pattern and a heating electrode contacted with the phase change pattern. The heating electrode includes a smart heating electrode such that the smart heating layer is formed of a conduction material that exhibits an increase in resistance as a function of an increase in temperature, i.e., a positive temperature dependent resistivity.

Abstract: The method and system for selenization in fabricating CIS and/or CIGS based thin film solar cell overlaying cylindrical glass substrates. The method includes providing a substrate, forming an electrode layer over the substrate and depositing a precursor layer of copper, indium, and/or gallium over the electrode layer. The method also includes disposing the substrate vertically in a furnace. Then a gas including a hydrogen species, a selenium species and a carrier gas are introduced into the furnace and heated to between about 350° C. and about 450° C. to at least initiate formation of a copper indium diselenide film from the precursor layer.

Abstract: A bulk barium copper sulfur fluoride (BCSF) material can be made by combining Cu2S, BaS and BaF2, heating the ampoule between 400 and 550° C. for at least two hours, and then heating the ampoule at a temperature between 550 and 950° C. for at least two hours. The BCSF material may be doped with potassium, rubidium, or sodium. Additionally, a p-type transparent conductive material can comprise a thin film of BCSF on a substrate where the film has a conductivity of at least 1 S/cm. The substrate may be a plastic substrate, such as a polyethersulfone, polyethylene terephthalate, polyimide, or some other suitable plastic or polymeric substrate.

Abstract: A programmable metallization device, comprises a first electrode; a memory layer electrically coupled to the first electrode and adapted for electrolytic formation and destruction of a conducting bridge therethrough; an ion-supplying layer containing a source of ions of a first metal element capable of diffusion into and out of the memory layer; a conductive ion buffer layer between the ion-supplying layer and the memory layer, and which allows diffusion therethrough of said ions; and a second electrode electrically coupled to the ion-supplying layer. Circuitry is coupled to the device to apply bias voltages to the first and second electrodes to induce creation and destruction of conducting bridges including the first metal element in the memory layer. The ion buffer layer can improve retention of the conducting bridge by reducing the likelihood that the first metallic element will be absorbed into the ion supplying layer.

Abstract: A programmable metallization device, comprises a first electrode; a memory layer electrically coupled to the first electrode and adapted for electrolytic formation and destruction of a conducting bridge therethrough; an ion-supplying layer containing a source of ions of a first metal element capable of diffusion into and out of the memory layer; a conductive ion buffer layer between the ion-supplying layer and the memory layer, and which allows diffusion therethrough of said ions; and a second electrode electrically coupled to the ion-supplying layer. Circuitry is coupled to the device to apply bias voltages to the first and second electrodes to induce creation and destruction of conducting bridges including the first metal element in the memory layer. The ion buffer layer can improve retention of the conducting bridge by reducing the likelihood that the first metallic element will be absorbed into the ion supplying layer.

Abstract: A method for formation of a phase change memory (PCM) cell includes depositing amorphous phase change material in a via hole, the via hole comprising a bottom and a top, such that the amorphous phase change material is grown on an electrode located at the bottom of the via hole; melt-annealing the amorphous phase change material; and crystallizing the phase change material starting at the electrode at the bottom of the via hole and ending at the top of the via hole.

Abstract: A method for fabricating a multi-layer phase change memory device includes forming a phase change memory layer including a plurality of phase change memory elements on a word line formed on a plurality of semiconductor devices on a first semiconductor substrate, each phase change element having a notch formed at an upper surface thereof, forming an access device layer including plurality of access devices on a second semiconductor substrate, each access device having a conductive bump formed thereon, and combining the first and second semiconductor substrates and slidably inserting and locking each conductive bump of the plurality of access devices into each notch of the plurality of phase change memory elements to electrically connect the access devices to the phase change memory elements.

Abstract: A phase change memory device having a heater that exhibits a temperature dependent resistivity which provides a way of reducing a reset current is presented. The phase change memory device includes a phase change pattern and a heating electrode contacted with the phase change pattern. The heating electrode includes a smart heating electrode such that the smart heating layer is formed of a conduction material that exhibits an increase in resistance as a function of an increase in temperature, i.e., a positive temperature dependent resistivity.

Abstract: A nonvolatile memory device according to an embodiment of the present invention includes a first wire that extends in a first direction, a second wire that is formed at a height different from the first wire and extends in a second direction, and a nonvolatile memory cell that is arranged to be sandwiched between the first wire and the second wire at a position at which the first wire and the second wire intersect with each other. The nonvolatile memory cell includes a structure in which a nonvolatile storage element is sandwiched by semiconductor layers having different polarities.

Abstract: A phase change memory device having an improved word line resistance and a fabrication method of making the same are presented. The phase change memory device includes a semiconductor substrate, a word line, an interlayer insulation film, a strapping line, a plurality of current paths, a switching element, and a phase change variable resistor. The word line is formed in a cell area of the semiconductor substrate. The interlayer insulation film formed on the word line. The strapping line is formed on the interlayer insulation film such that the strapping line overlaps on top of the word line. The current paths electrically connect together the word line with the strapping line. The switching element is electrically connected to the strapping line. The phase change variable resistor is electrically connected to the switching element.

Abstract: A phase change memory apparatus is provided that includes a first electrode of a bar type having a trench formed on an active region of a semiconductor substrate, a second electrode formed in a bottom portion of the trench, and a bottom electrode contact formed on the second electrode.

Abstract: A phase change memory structure and method for forming the same, the method including providing a substrate comprising a conductive area; forming a spacer having a partially exposed sidewall region at an upper portion of the spacer defining a phase change memory element contact area; and, wherein the spacer bottom portion partially overlaps the conductive area. Both these two methods can reduce active area of a phase change memory element, therefore, reducing a required phase changing electrical current.

Abstract: A variable resistance memory cell structure and a method of forming it. The method includes forming a first electrode, forming an insulating material over the first electrode, forming a via in the insulating material to expose a surface of the first electrode, forming a heater material within the via using gas cluster ion beams, forming a variable resistance material within the via, and forming a second electrode such that the heater material and variable resistance material are provided between the first and second electrodes.

Abstract: A solid memory may include a recording layer including Ge, Sb and Te as major components. The recording layer may include a superlattice. The recording layer may include multi-layers each having a parent phase showing a phase transformation in solid-states, the phase transformation causing change in electrical property of the recording layer. The recording layer may include an Sb2Te3 layer that includes at least one period of a first lamination of a first Te-atomic layer, a first Sb-atomic layer, a second Te-atomic layer, a second Sb-atomic layer, and a third Te-atomic layer in these order, a GeTe layer that includes at least one period of a second lamination of a fourth Te-atomic layer and a Ge-atomic layer, and an Sb layer that includes a plurality of Sb-atomic layers.

Abstract: A resistance variable memory device includes at least one bottom electrode, a first insulating layer containing a trench which exposes the at least one bottom electrode, and a resistance variable material layer including respective first and second portions located on opposite sidewalls of the trench, respectively, where the first and second portions of the resistance variable material layer are electrically connected to the at least one bottom electrode.

Abstract: A chalcogenide alloy that optimizes operating parameters of an ovonic threshold switch includes an atomic percentage of arsenic in the range of 9 to 39, an atomic percentage of germanium in the range of 10 and 40, an atomic percentage of silicon in the range of 5 and 18, an atomic percentage of nitrogen in the range of 0 and 10, and an alloy of sulfur, selenium, and tellurium. A ratio of sulfur to selenium in the range of 0.25 and 4, and a ration of sulfur to tellurium in the alloy of sulfur, selenium, and tellurium is in the range of 0.11 and 1.

Abstract: According to one embodiment of the present invention, a memory cell array comprises a plurality of voids, the spatial positions and dimensions of the voids being chosen such that mechanical stress occurring within the memory cell array is at least partly compensated by the voids.

Abstract: A memory device 10 has an arrangement in which a memory thin film 4 is sandwiched between first and second electrodes 2 and 6, the memory thin film 6 contains at least rare earth elements, the memory thin film 4 or a layer 3 in contact with the memory thin film 4 contains any one of elements selected from Cu, Ag, Zn and the memory thin film 4 or the layer 3 in contact with the memory thin film 4 contains any one of elements selected from Te, S, Se. The memory device can record and read information with ease stably, and this memory device can be manufactured easily by a relatively simple manufacturing method.

Abstract: A memory cell includes a current-steering device, a phase-change material disposed thereover, and a heating element and/or a cooling element.

Abstract: A device consists a disordered relaxation insulator or/and a polyamorphous solid between two or more electrodes. Invented devices can perform passive, logic and memory functions in an electronic integrated circuit.

Abstract: A method of programming a one-time programmable device is provided. A switching device disposed in a substrate is turned on and a program current is applied to a fuse electrically connected to the switching device, thereby cutting the fuse. The fuse includes a first electrode electrically connected to the switching device, a second electrode spaced apart from the first electrode, and a chalcogenide pattern disposed between the first and second electrodes. Related one-time programmable devices, phase change memory devices and electronic systems are also disclosed.

Abstract: An electronic circuit with repetitive patterns formed by shadow mask vapor deposition includes a repetitive pattern of electronic circuit elements formed on a substrate. Each electronic circuit element includes the following elements in the desired order of deposition: a first semiconductor segment, a second semiconductor segment, a first metal segment, a second metal segment, a third metal segment, a fourth metal segment, a fifth metal segment, a sixth metal segment, a first insulator segment, a second insulator segment, a third insulator segment, a seventh metal segment, an eighth metal segment, a ninth metal segment and a tenth metal segment. All of the above segments may be deposited via a shadow mask deposition process. The electronic circuit element may be an element of an array of like electronic circuit elements.

Abstract: A Phase Change Memory (PCM) cell structure comprises both a lower electrode composed of a PCM layer and a conductive encapsulating upper electrode layer. The PCM layer is protected from damage by the conductive encapsulating layer. Electrical isolation between adjacent PCM cells is provided by high electrical resistance regions which were formed by modifying the conductivity of both the PCM layer and the conductive encapsulating upper electrode layer subsequent to deposition thereof.

Abstract: Semiconductor materials suitable for being used in radiation detectors are disclosed. A particular example of the semiconductor materials includes tellurium, cadmium, and zinc. Tellurium is in molar excess of cadmium and zinc. The example also includes aluminum having a concentration of about 10 to about 20,000 atomic parts per billion and erbium having a concentration of at least 10,000 atomic parts per billion.

Abstract: A solution of a hydrazine-based precursor of a metal chalcogenide is prepared by adding an elemental metal and an elemental chalcogen to a hydrazine compound. The precursor solution can be used to form a film. The precursor solutions can be used in preparing field-effect transistors, photovoltaic devices and phase-change memory devices.

Abstract: A phase change memory device and a method of fabricating the same are disclosed. The phase change memory device includes a first conductor pattern having a first conductivity type and a sidewall. A second conductor pattern is connected to the sidewall of the first conductor pattern to form a diode. A phase change layer is electrically connected to the second conductor pattern and a top electrode is connected to the phase change layer.

Abstract: A memory cell includes a FinFET select device and a memory element. In some embodiments a memory cell has a contact element coupled between a surface of the fin and the memory element.

Abstract: A memory cell comprises a lower electrode, a phase change feature, a spacer feature, and a dielectric layer. The lower electrode comprises a first surface region as well as a second surface region that is raised in relation to the first surface region. The phase change feature is disposed on the second surface region of the lower electrode and has one or more sidewalls. The spacer feature is also disposed on the second surface region of the lower electrode and against the one or more sidewalls of the phase change feature. The dielectric layer is formed at least partially on top of the first surface region of the lower electrode and abutting the spacer feature.

Abstract: A phase change memory may have reduced reverse bias current by providing a N-channel field effect transistor coupled between a bipolar transistor and a conductive line such a row line. By coupling the gate of the MOS transistor to the row line, reverse bias current in unselected cells or in the standby mode may be reduced.