Abstract: An electrostatic discharge protection structure includes a semiconductor substrate, a gate structure disposed on the semiconductor substrate, a first well region of a first conductivity type disposed in the semiconductor substrate, a first doped region of the first conductivity type, a second doped region of a second conductivity type, a third doped region of the first conductivity type, and a fourth doped region of the second conductivity type. The first and second doped regions are disposed in the first well region and connected with each other. The second doped region is an emitter of a first bipolar junction transistor. The third and fourth doped regions are disposed in the semiconductor substrate and connected with each other. The third and second doped regions are located at two opposite sides of the gate structure in a first horizontal direction. The third doped region is an emitter of a second bipolar junction transistor.

Abstract: A light emitting device includes plural light emitting elements arranged on a substrate in lines and individually emit light each other. The light emitting device includes a single continuous n-type semiconductor layer on the substrate shared by the plural light emitting elements, a single continuous light emitting layer on the n-type semiconductor layer shared by the plural light emitting elements, a single continuous p-type semiconductor layer on the light emitting layer shared by the plural light emitting elements, a single continuous contact electrode film on the p-type semiconductor layer shared by the plural light emitting elements, and plural p-side bonding electrodes on the contact electrode film respectively used for the plural light emitting elements. The contact electrode film and the p-type semiconductor layer are configured so as to control current diffusion in in-plane directions thereof.

Abstract: A method for forming a fin transistor in a bulk substrate includes forming a super steep retrograde well (SSRW) on a bulk substrate. The well includes a doped portion of a first conductivity type dopant formed below an undoped layer. A fin material is grown over the undoped layer. A fin structure is formed from the fin material, and the fin material is undoped or doped. Source and drain regions are provided adjacent to the fin structure to form a fin field effect transistor.

Abstract: Disclosed are embodiments of a metal oxide semiconductor field effect transistor (MOSFET) structure and a method of forming the structure. The structure incorporates source/drain regions and a channel region between the source/drain regions. The source/drain regions can comprise silicon, which has high diffusivity to the source/drain dopant. The channel region can comprise a silicon alloy selected for optimal charge carrier mobility and band energy and for its low source/drain dopant diffusivity. During processing, the source/drain dopant can diffuse into the edge portions of the channel region. However, due to the low diffusivity of the silicon alloy to the source/drain dopant, the dopant does not diffuse deep into channel region. Thus, the edge portions of the silicon alloy channel region can have essentially the same dopant profile as the source/drain regions, but a different dopant profile than the center portion of the silicon alloy channel region.

Abstract: A method of forming an epitaxial layer includes the following steps. At first, a first epitaxial growth process is performed to form a first epitaxial layer on a substrate, and a gas source of silicon, a gas source of carbon, a gas source of phosphorous and a gas source of germanium are introduced during the first epitaxial growth process to form the first epitaxial layer including silicon, carbon, phosphorous and germanium. Subsequently, a second epitaxial growth process is performed to form a second epitaxial layer, and a number of elements in the second epitaxial layer is smaller than a number of elements in the first epitaxial layer.

Abstract: This description relates to a gate electrode of a field effect transistor. An exemplary structure for a field effect transistor includes a substrate; a gate electrode over the substrate including a first top surface and a sidewall; a source/drain (S/D) region at least partially disposed in the substrate on one side of the gate electrode; a spacer on the sidewall distributed between the gate electrode and the S/D region; and a contact etch stop layer (CESL) adjacent to the spacer and further comprising a portion extending over the S/D region, wherein the portion has a second top surface substantially coplanar with the first top surface.

Abstract: A method of forming a template on a silicon substrate includes epitaxially growing a template of single crystal ternary rare earth oxide on a silicon substrate and epitaxially growing a single crystal semiconductor active layer on the template. The active layer has either a cubic or a hexagonal crystal structure. During the epitaxial growth of the template, a partial pressure of oxygen is selected and a ratio of metals included in the ternary rare earth oxide is selected to match crystal spacing and structure of the template at a lower interface to the substrate and to match crystal spacing and structure of the template at an upper interface to crystal spacing and structure of the semiconductor active layer. A high oxygen partial pressure during growth of the template produces a stabilized cubic crystal structure and a low oxygen partial pressure produces a predominant peak with a hexagonal crystal structure.

Abstract: A semiconductor device includes a device region. The device region includes at least one device region section including dopant atoms of a first doping type and with a first doping concentration of at least 1E16 cm?3 and dopant atoms of a second doping type and with a second doping concentration of at least 1E16 cm?3.

Abstract: Silicon carbide single crystal is prepared. Using the silicon carbide single crystal as a material, a silicon carbide substrate having a first face and a second face located at a side opposite to the first face is formed. In the formation of the silicon carbide substrate, a first processed damage layer and a second processed damage layer are formed at the first face and second face, respectively. The first face is polished such that at least a portion of the first processed damage layer is removed and the surface roughness of the first face becomes less than or equal to 5 nm. At least a portion of the second processed damage layer is removed while maintaining the surface roughness of the second plane greater than or equal to 10 nm.

Abstract: A light emitting diode device includes a first diode structure, a second diode structure on the first diode structure, and a conductive junction between the first diode structure and the second diode structure. The conductive junction includes a transparent conductive layer between the first diode structure and the second diode structure. Low resistance heterojunction tunnel junction structures including delta-doped layers are also disclosed.

Abstract: Disclosed are a growth substrate and a light emitting device. The light emitting device includes a silicon substrate, a first buffer layer disposed on the silicon substrate and having an exposing portions of the silicon substrate, a second buffer layer covering the first buffer layer and the exposed portions of the silicon substrate, wherein the second buffer layer is formed of a material causing a eutectic reaction with the silicon substrate, a third buffer layer disposed on the second buffer layer, and a light emitting structure disposed on the third buffer layer, and the second buffer layer includes voids.

Abstract: A method of manufacturing a silicon carbide structure includes forming a silicon carbide layer by depositing silicon carbide on a base plate by chemical vapor deposition, removing the base plate, decreasing electrical conductivity by heat-treating the silicon carbide structure, and removing a thickness of 200 ?m from an upper surface and a lower surface of the silicon carbide structure. In the present invention, silicon carbide is deposited by a CVD method, and the electrical conductivity of the silicon carbide is reduced to the electrical conductivity required for a protection ring of a plasma device through a post-treatment and a post-process. The electrical conductivity may be adjusted even without using separate additives.

Abstract: A semiconductor device includes a semiconductor substrate having a principal surface, and an insulating film formed on the principal surface and continuously covering a top surface of a first boundary region and a top surface of a second boundary region, the first boundary region including a boundary between a well layer and a RESURF layer, the second boundary region including a boundary between the RESURF layer and a first impurity region. The semiconductor device further includes a plurality of lower field plates formed in the insulating film in such a manner that the plurality of lower field plates do not lie directly above the first and second boundary regions, and a plurality of upper field plates formed on the insulating film in such a manner that the plurality of upper field plates do not lie directly above the first and second boundary regions.

Abstract: Disclosed is a semiconductor device which includes a silicon carbide layer, a trench formed in the silicon carbide layer, and a channel formed on at least one of a bottom of the trench, a side-wall surface, or the silicon carbide layer, in which an electrical conduction direction of the channel is parallel to a surface of the silicon carbide layer.

Abstract: An oxide semiconductor includes a first material including at least one selected from the group consisting of zinc (Zn) and tin (Sn), and a second material, where a value acquired by subtracting an electronegativity difference value between the second material and oxygen (O) from the electronegativity difference value between the first material and oxygen (O) is less than about 1.3.

Abstract: An edge region has a width of 5 mm. A valid region is surrounded by the edge region, and has an area greater than or equal to 100 cm2. At the valid region, a micropipe having a cross-sectional area exceeding 1 ?m2 is not present. The valid region includes a plurality of high-quality regions occupying 70% or more of the valid region. Each of the plurality of high-quality regions has a square shape, an area greater than or equal to 1 cm2, and a micropipe density less than or equal to 1 micropipe per 1 cm2.

Abstract: Silicon carbide single crystal is prepared. Using the silicon carbide single crystal as a material, a silicon carbide substrate having a first face and a second face located at a side opposite to the first face is formed. In the formation of the silicon carbide substrate, a first processed damage layer and a second processed damage layer are formed at the first face and second face, respectively. The first face is polished such that at least a portion of the first processed damage layer is removed and the surface roughness of the first face becomes less than or equal to 5 nm. At least a portion of the second processed damage layer is removed while maintaining the surface roughness of the second plane greater than or equal to 10 nm.

Abstract: A silicon carbide substrate capable of reducing on-resistance and improving yield of semiconductor devices is made of single-crystal silicon carbide, and sulfur atoms are present in one main surface at a ratio of not less than 60×1010 atoms/cm2 and not more than 2000×1010 atoms/cm2, and oxygen atoms are present in the one main surface at a ratio of not less than 3 at % and not more than 30 at %.

Abstract: A germanium-containing layer is deposited on a single crystalline bulk silicon substrate in an ambient including a level of oxygen partial pressure sufficient to incorporate 1%-50% of oxygen in atomic concentration. The thickness of the germanium-containing layer is preferably limited to maintain some degree of epitaxial alignment with the underlying silicon substrate. Optionally, a graded germanium-containing layer can be grown on, or replace, the germanium-containing layer. An at least partially crystalline silicon layer is subsequently deposited on the germanium-containing layer. A handle substrate is bonded to the at least partially crystalline silicon layer. The assembly of the bulk silicon substrate, the germanium-containing layer, the at least partially crystalline silicon layer, and the handle substrate is cleaved within the germanium-containing layer to provide a composite substrate including the handle substrate and the at least partially crystalline silicon layer.

Abstract: A semiconductor component is provided having a substrate and at least one semiconductor layer realized to be polycrystalline on one side of the substrate. The polycrystalline semiconductor layer contains the crystal nuclei.

Abstract: A method for forming a substrate includes forming a base layer comprising a Group III-V material on a substrate, cooling the base layer and inducing cracks in the base layer, and forming a bulk layer comprising a Group III-V material on the base layer after cooling.

Abstract: Disclosed is a nanorod semiconductor device having a contact structure, and a method for manufacturing the same. The nanorod semiconductor device having a contact structure according to one embodiment of the present disclosure includes: a transparent wafer; a transparent electrode layer formed on the transparent wafer; a nanorod layer including a plurality of semiconductor nanorods doped with dopants having a first polarity and grown on the transparent electrode layer; and a single crystal semiconductor layer doped with dopants having a second polarity and forming a certain physical contact with the ends of the semiconductor nanorods.

Abstract: A manufacturing process for a semiconductor-on-insulator structure having reduced electrical losses and which includes a support substrate made of silicon, an oxide layer and a thin layer of semiconductor material, and a polycrystalline silicon layer interleaved between the support substrate and the oxide layer. The process includes a treatment capable of conferring high resistivity to the support substrate prior to formation of the polycrystalline silicon layer, and then conducting at least one long thermal stabilization on the structure at a temperature not exceeding 950° C. for at least 10 minutes.

Abstract: According to an embodiment, a semiconductor light emitting device includes a foundation layer, a first semiconductor layer, a light emitting layer, and a second semiconductor layer. The foundation layer has an unevenness having recesses, side portions, and protrusions. A first major surface of the foundation layer has an overlay-region. The foundation layer has a plurality of dislocations including first dislocations whose one ends reaching the recess and second dislocations whose one ends reaching the protrusion. A proportion of a number of the second dislocations reaching the first major surface to a number of all of the second dislocations is smaller than a proportion of a number of the first dislocations reaching the first major surface to a number of all of the first dislocations. A number of the dislocations reaching the overlay-region of the first major surface is smaller than a number of all of the first dislocations.

Abstract: Provided is a silicon wafer which is stabilized in quality exerting no adverse influence on device characteristics and manufactured by restricting a boron contamination from the environment, and a manufacturing process therefor. Concretely, the silicon wafer is characterized by an attached boron amount thereon being 1×1010 atoms/cm2 or less. In order to manufacture such a wafer as contains a small amount of boron attached on the wafer surface, the wafer is treated in an atmosphere of boron concentration of 15 ng/m3 or less. Boron-less filters and boron adsorbing filters are used as filters in a clean room and the like so as to lower the boron concentration in the atmosphere.

Abstract: A nitride semiconductor device includes: a silicon substrate; a buffer layer formed on the silicon substrate and comprised of a nitride semiconductor; and an active layer formed on the buffer layer and comprised of a nitride semiconductor. The buffer layer includes a first layer formed in contact with the silicon substrate, and a second layer formed in contact with the first layer and the active layer. The carbon concentration at an interface between the first layer and the second layer is in the range of 1×1019 atoms/cm3 to 1×1021 atoms/cm3, both inclusive. The first layer has the highest carbon concentration in a portion in contact with the silicon substrate. The second layer has the highest carbon concentration in a portion in contact with the first layer, and has the lowest carbon concentration in a portion in contact with the active layer.

Abstract: An epitaxial substrate for an electronic device, in which a lateral direction of the substrate is defined as a main current conducting direction and a warp configuration of the epitaxial substrate is adequately controlled, as well as a method of producing the epitaxial substrate. Specifically, the epitaxial substrate for an electron device, including: a Si single crystal substrate; and a Group III nitride laminated body formed by epitaxially growing plural Group III nitride layers on the Si single crystal substrate, wherein a lateral direction of the epitaxial substrate is defined as a main current conducting direction, is characterized in that the Si single crystal substrate is a p-type substrate having a specific resistance value of not larger than 0.01 ?·cm.

Abstract: To provide an oxide semiconductor film having stable electric conductivity and a highly reliable semiconductor device having stable electric characteristics by using the oxide semiconductor film. The oxide semiconductor film contains indium (In), gallium (Ga), and zinc (Zn) and includes a c-axis-aligned crystalline region aligned in the direction parallel to a normal vector of a surface where the oxide semiconductor film is formed. Further, the composition of the c-axis-aligned crystalline region is represented by In1+?Ga1??O3(ZnO)m (0<?<1 and m=1 to 3 are satisfied), and the composition of the entire oxide semiconductor film including the c-axis-aligned crystalline region is represented by InxGayO3(ZnO)m (0<x<2, 0<y<2, and m=1 to 3 are satisfied).

Abstract: Disclosed are an SiC semiconductor element and manufacturing method for an SiC semiconductor element in which the interface state density of the interface of the insulating film and the SiC is reduced, and channel mobility is improved. Phosphorus (30) is added to an insulating film (20) formed on an SiC semiconductor (10) substrate in a semiconductor element. The addition of phosphorous to the insulating film makes it possible to significantly reduce the defects (interface state density) in the interface (21) of the insulating film and the SiC, and to dramatically improve the channel mobility when compared with conventional SiC semiconductor elements. The addition of phosphorus to the insulating film is carried out by heat treatment. The use of heat treatment to add phosphorous to the insulating film makes it possible to maintain the reliability of the insulating film, and to avoid variation in channel mobility and threshold voltage.

Abstract: A semiconductor device includes: a substrate made of silicon carbide and having a main surface having an off angle of not less than ?° and not more than +5° relative to a (0-33-8) plane in a <01-10> direction; a p type layer made of silicon carbide and formed on the main surface of the substrate by means of epitaxial growth; and an oxide film formed in contact with a surface of the p type layer. A maximum value of nitrogen atom concentration is 1×1021 cm?3 or greater in a region within 10 nm from an interface between the p type layer and the oxide film.

Abstract: Semipolar wurtzite Group III nitride-based semiconductor layers and semiconductor components based thereon are described. Group III nitride layers have a broad range of applications in electronics and optoelectronics. Such layers are generally grown on substrates such as sapphire, SiC and, more recently, Si(111). The layers obtained are generally polar or have c-axis orientation in the direction of growth. For many applications in the field of optoelectronics, as well as acoustic applications in SAWs, the growth of non-polar or semipolar Group III nitride layers is interesting or necessary. The process according to the invention permits simple and inexpensive growth of polarisation-reduced Group III nitride layers without prior structuring of the substrate.

Abstract: Disclosed are a growth substrate and a light emitting device. The light emitting device includes a silicon substrate, a first buffer layer disposed on the silicon substrate and having an exposing portions of the silicon substrate, a second buffer layer covering the first buffer layer and the exposed portions of the silicon substrate, wherein the second buffer layer is formed of a material causing a eutectic reaction with the silicon substrate, a third buffer layer disposed on the second buffer layer, and a light emitting structure disposed on the third buffer layer, and the second buffer layer includes voids.

Abstract: A method for fabricating a semiconductor device according to the present invention includes the steps of: (a) providing a substrate (11a) in a chamber (26); (b) supplying a microwave into the chamber (26) through a dielectric plate (24), of which one surface that faces the chamber is made of alumina, thereby depositing a microcrystalline silicon film (14) with an aluminum concentration of 1.0×1016 atoms/cm3 or less on the substrate (11a) by high-density plasma CVD process; and (c) making a thin-film transistor that uses the microcrystalline silicon film as its active layer. As a result, a semiconductor device including a TFT that uses a microcrystalline silicon film with a mobility of more than 0.5 cm2/Vs as its active layer is obtained.

Abstract: A hybrid silicon wafer which is a silicon wafer having a structure wherein monocrystalline silicon is embedded in polycrystalline silicon that is prepared by the unidirectional solidification/melting method. The longitudinal plane of crystal grains of the polycrystalline portion prepared by the unidirectional solidification/melting method is used as the wafer plane, and the monocrystalline silicon is embedded so that the longitudinal direction of the crystal grains of the polycrystalline portion forms an angle of 120° to 150° relative to the cleaved surface of the monocrystalline silicon. Thus provided is a hybrid silicon wafer comprising the functions of both a polycrystalline silicon wafer and a monocrystalline wafer.

Abstract: Semiconductor device structures including a semiconductor body that is partially depleted to define a floating charge-neutral region supplying a floating body for charge storage and methods for forming such semiconductor device structures. The width of the semiconductor body is modulated so that different sections of the body have different widths. When electrically biased, the floating charge-neutral region at least partially resides in the wider section of the semiconductor body.

Abstract: A semiconductor device having a substrate including a major surface, a gate stack comprising a sidewall over the substrate and a spacer over the substrate adjoining the sidewall of the gate stack. The spacer having a bottom surface having an outer point that is the point on the bottom surface farthest from the gate stack. An isolation structure in the substrate on one side of the gate stack has an outer edge closest to the spacer. A strained material below the major surface of the substrate disposed between the spacer and the isolation structure having an upper portion and a lower portion separated by a transition plane at an acute angle to the major surface of the substrate.

Abstract: An epitaxial substrate for electronic devices, in which current flows in a lateral direction and of which warpage configuration is properly controlled, and a method of producing the same. The epitaxial substrate for electronic devices is produced by forming a bonded substrate by bonding a low-resistance Si single crystal substrate and a high-resistance Si single crystal substrate together; forming a buffer as an insulating layer on a surface of the bonded substrate on the high-resistance Si single crystal substrate side; and producing an epitaxial substrate by epitaxially growing a plurality of III-nitride layers on the buffer to form a main laminate. The resistivity of the low-resistance Si single crystal substrate is 100 ?·cm or less, and the resistivity of the high-resistance Si single crystal substrate is 1000 ?·cm or more.

Abstract: A semiconductor structure is provided that includes a semiconductor oxide layer having features. The semiconductor oxide layer having the features is located between an active semiconductor layer and a handle substrate. The semiconductor structure includes a planarized top surface of the active semiconductor layer such that the semiconductor oxide layer is beneath the planarized top surface. The features within the semiconductor oxide layer are mated with a surface of the active semiconductor layer.

Abstract: A semiconductor device substrate is presented here. The semiconductor device substrate includes a layer of first semiconductor material having a first lattice constant, a region of second semiconductor material located in the layer of first semiconductor material, and a layer of epitaxially grown third semiconductor material overlying the layer of first semiconductor material and overlying the region of second semiconductor material. The second semiconductor material has a second lattice constant that is different than the first lattice constant. Moreover, the layer of epitaxially grown third semiconductor material exhibits a stressed zone overlying the region of second semiconductor material. The stressed zone has a third lattice constant that is different than the first lattice constant.

Abstract: Memory devices are described along with manufacturing methods. A memory device as described herein includes a bottom electrode and a first phase change layer comprising a first phase change material on the bottom electrode. A resistive heater comprising a heater material is on the first phase change material. A second phase change layer comprising a second phase change material is on the resistive heater, and a top electrode is on the second phase change layer. The heater material has a resistivity greater than the most highly resistive states of the first and second phase change materials.

Abstract: The semiconductor device of the present invention includes: a gate insulating film formed on a semiconductor region of a first conductivity type; a gate electrode formed on the gate insulating film; and a channel doped layer of the first conductivity type formed in the semiconductor region beneath the gate electrode. The channel doped layer contains carbon as an impurity.

Abstract: In a method of manufacturing a semiconductor device, forming a film of amorphous Si on a substrate including an insulating upper surface; injecting a first impurity of a first conductivity in a first region and a second region of the film; crystallizing the film by melting and solidifying the film and activating the first impurity by scanning a first laser light in a first direction and radiating the first laser light over the film; injecting a second impurity of a second conductivity at a higher concentration than the first impurity, the second impurity being a lighter element than the first impurity in the first region with masking the second region; and activating the second impurity.

Abstract: One embodiment is a phase change memory that includes a heater element transversely contacting a storage element of phase change material. In particular, an end of the storage element contacts an end of the heater element. A first pair of dielectric spacers is positioned on opposite sides of the first heater element and a second pair of dielectric spacers is positioned on opposite sides of the first storage element. The storage element, heater element, and first and second pairs of dielectric spacers can be made by a spacer patterning technique.

Abstract: An epitaxial structure having a low defect density includes: a base layer; a first epitaxial layer having a plurality of concentrated defect groups, and an epitaxial surface that has a plurality of first recesses corresponding in position to the concentrated defect groups, the sizes of the first recesses being close to each other; and a plurality of defect-termination blocks respectively and filling the first recesses and having polished surfaces. The defect-termination blocks are made of a material which is different in removal rate from that of the first epitaxial layer.

Abstract: According to one embodiment, a semiconductor device provided with a structure, which prevents withstand voltage deterioration and may be manufactured at a low cost, is provided.

Abstract: A p-type SiC semiconductor includes a SiC crystal that contains Al and Ti as impurities, wherein the atom number concentration of Ti is equal to or less than the atom number concentration of Al. It is preferable that the concentration of Al and the concentration of Ti satisfy the following relations: (Concentration of Al)?5×1018/cm3; and 0.01%?(Concentration of Ti)/(Concentration of Al)?20%. It is more preferable that the concentration of Al and the concentration of Ti satisfy the following relations: (Concentration of Al)?5×1018/cm3; and 1×1017/cm3?(Concentration of Ti)?1×1018/cm3.

Abstract: Large area single crystal III-V nitride material having an area of at least 2 cm2, having a uniformly low dislocation density not exceeding 3×106 dislocations per cm2 of growth surface area, and including a plurality of distinct regions having elevated impurity concentration, wherein each distinct region has at least one dimension greater than 50 microns, is disclosed. Such material can be formed on a substrate by a process including (i) a first phase of growing the III-V nitride material on the substrate under pitted growth conditions, e.g., forming pits over at least 50% of the growth surface of the III-V nitride material, wherein the pit density on the growth surface is at least 102 pits/cm2 of the growth surface, and (ii) a second phase of growing the III-V nitride material under pit-filling conditions.

Abstract: By making an ovonic threshold switch using a carbon interfacial layer having a thickness of less than or equal to ten percent of the thickness of the associated electrode, cycle endurance may be improved. In some embodiments, a glue layer may be used between the carbon and the chalcogenide of the ovonic threshold switch. The glue layer may be effective to improve adherence between carbon and chalcogenide.

Abstract: A composite wafer comprises a single crystal substrate having first and second sides; a first III-nitride single crystal layer disposed on the first side of the substrate and being defined by a thickness; and a second III-nitride single crystal layer disposed on the second side of the single crystal substrate and being defined by a thickness. The thickness of each III-nitride single crystal layer is substantially the same. The composite wafer may be used in the manufacture of a semiconductor device or a freestanding wafer.

Abstract: A microelectronic assembly in which a semiconductor device structure is directionally positioned on an off-axis substrate. In an illustrative implementation, a laser diode is oriented on a GaN substrate wherein the GaN substrate includes a GaN (0001) surface off-cut from the <0001> direction predominantly towards either the <11 20> or the <1 100> family of directions. For a <11 20> off-cut substrate, a laser diode cavity may be oriented along the <1 100> direction parallel to lattice surface steps of the substrate in order to have a cleaved laser facet that is orthogonal to the surface lattice steps. For a <1 100> off-cut substrate, the laser diode cavity may be oriented along the <1 100> direction orthogonal to lattice surface steps of the substrate in order to provide a cleaved laser facet that is aligned with the surface lattice steps.