Abstract: The present teaching provides a semiconductor device capable of relaxing stress transferred to a contact region during wire bonding and improving reliability of wire bonding. A semiconductor device comprises contact regions, an interlayer insulating film, an emitter electrode, and a stress relaxation portion. The contact regions are provided at a certain interval in areas exposing at a surface of a semiconductor substrate. The interlayer insulating film is provided on the surface of the semiconductor substrate between adjacent contact regions. The emitter electrode is provided on an upper side of the semiconductor substrate and electrically connected to each of the contact regions. The stress relaxation portion is provided on an upper surface of the emitter electrode in an area only above the contact regions. The stress relaxation portion is formed of a conductive material.

Abstract: A semiconductor device implemented with structures to suppress leakage current generation during operation and a method of making the same is provided. The semiconductor device includes a semiconductor substrate of first conductivity type, a second insulation film, which has at least one aperture between first and second apertures, formed on top of a first insulation film. The semiconductor device layer structure accommodates tensile stress differences between device layers to suppress lattice dislocation defects during device manufacturing and thus improves device reliability and performance.

Abstract: An RF-power device includes a semiconductor substrate having a plurality of active regions arranged in an array. Each active region includes one or more RF-power transistors. The active regions are interspersed with inactive regions for reducing mutual heating of the RF-power transistors in separate active regions. The devices also includes at least one impedance matching component located in one of the inactive regions of the substrate.

Abstract: Insufficient gain in bipolar transistors (20) is improved by providing an alloyed (e.g., silicided) emitter contact (452) smaller than the overall emitter (42) area. The improved emitter (42) has a first emitter (FE) portion (42-1) of a first dopant concentration CFE, and a second emitter (SE) portion (42-2) of a second dopant concentration CSE. Preferably CSE?CFE. The SE portion (42-2) desirably comprises multiple sub-regions (45i, 45j, 45k) mixed with multiple sub-regions (47m, 47n, 47p) of the FE portion (42-1). A semiconductor-metal alloy or compound (e.g., a silicide) is desirably used for Ohmic contact (452) to the SE portion (42-2) but substantially not to the FE portion (42-1). Including the FE portion (42-1) electrically coupled to the SE portion (42-2) but not substantially contacting the emitter contact (452) on the SE portion (42-2) provides gain increases of as much as ˜278.

Abstract: The present disclosure provides a bipolar junction transistor (BJT) device and methods for manufacturing the BJT device. In an embodiment, the BJT device includes: a semiconductor substrate having a collector region, and a material layer disposed over the semiconductor layer. The material layer has a trench therein that exposes a portion of the collector region. A base structure, spacers, and emitter structure are disposed within the trench of the material layer. Each spacer has a top width and a bottom width, the top width being substantially equal to the bottom width.

Abstract: An IGBT comprises trenches arranged in strips, first emitter diffusion layers formed so as to extend in a direction intersecting the trenches, and contact regions formed to have a rectangular shape. The portions of the contact regions on the first emitter diffusion layers have a smaller width than the other portions, the width extending in the direction intersecting the trenches. This configuration allows for an increase in the emitter ballast resistance of the emitter diffusion layers, resulting in enhanced resistance to electrical breakdown due to short circuit.

Abstract: A bidirectional power transistor formed horizontally in a semiconductor layer disposed on a heavily-doped semiconductor wafer with an interposed insulating layer, the wafer being capable of being biased to a reference voltage, the product of the average dopant concentration and of the thickness of the semiconductor layer ranging between 5·1011 cm?2 and 5·1012 cm?2.

Abstract: Insufficient gain in bipolar transistors (20) is improved by providing an alloyed (e.g., silicided) emitter contact (452) smaller than the overall emitter (42) area. The improved emitter (42) has a first emitter (FE) portion (42-1) of a first dopant concentration CFE, and a second emitter (SE) portion (42-2) of a second dopant concentration CSE. Preferably CSE?CFE. The SE portion (42-2) desirably comprises multiple sub-regions (45i, 45j, 45k) mixed with multiple sub-regions (47m, 47n, 47p) of the FE portion (42-1). A semiconductor-metal alloy or compound (e.g., a silicide) is desirably used for Ohmic contact (452) to the SE portion (42-2) but substantially not to the FE portion (42-1). Including the FE portion (42-1) electrically coupled to the SE portion (42-2) but not substantially contacting the emitter contact (452) on the SE portion (42-2) provides gain increases of as much as ˜278.

Abstract: A bipolar transistor at least includes a semiconductor substrate including an N? epitaxial growth layer and a P? silicon substrate, an N+ polysilicon layer, a tungsten layer, two silicide layers, a base electrode, an emitter electrode, and a collector electrode. The N+ polysilicon layer formed on the semiconductor substrate is covered with one of the silicide layers. The tungsten layer that is formed on the silicide layer is covered with the other silicide layer.

Abstract: Vertical heterojunction bipolar transistors with reduced base-collector junction capacitance, as well as fabrication methods for vertical heterojunction bipolar transistors and design structures for BiCMOS integrated circuits. The vertical heterojunction bipolar transistor includes a barrier layer between the intrinsic base and the extrinsic base that blocks or reduces diffusion of a dopant from the extrinsic base to the intrinsic base. The barrier layer has at least one opening that permits direct contact between the intrinsic base and a portion of the extrinsic base disposed in the opening.

Abstract: This invention disclosed a novel manufacturing approach of collector and buried layer of a bipolar transistor. One aspect of the invention is that an oxide-nitride-oxide (ONO) sandwich structure is employed instead of oxide-nitride dual layer structure before trench etching. Another aspect is, through the formation of silicon oxide spacer in trench sidewall and silicon oxide remaining in trench bottom in the deposition and etch back process, the new structure hard mask can effectively protect active region from impurity implanted in ion implantation process.

Abstract: A semiconductor device includes: a gate electrode formed above a semiconductor region; a drain region and a source region formed in portions of the semiconductor region located below sides of the gate electrode in a gate length direction, respectively; a plurality of drain contacts formed on the drain region to be spaced apart in a gate width direction of the gate electrode; and a plurality of source contacts formed on the source region to be spaced apart in the gate width direction of the gate electrode. The intervals between the drain contacts are greater than the intervals between the source contacts.

Abstract: Embodiments of methods, apparatus, devices and/or systems associated with bipolar junction transistor are disclosed.

Abstract: A semiconductor device is disclosed. The semiconductor device includes: a first electrode, disposed over a first region of a substrate; and a conductive layer, disposed over the substrate, including a second electrode disposed above the first electrode, wherein the second electrode comprises a mesh main part having a plurality of openings, and a plurality of extending parts, wherein the extending parts are connected to the mesh main part at periphery of the openings and extend toward a surface of the first electrode.

Abstract: Disclosed is a semiconductor device in which emitter pad electrodes connected to an active region, collector and base pad electrodes are formed on a surface of a semiconductor substrate. Furthermore, on a back surface of the semiconductor substrate, a backside electrode is formed. Moreover, the emitter pad electrodes connected to a grounding potential are connected to the backside electrode through feedthrough electrodes penetrating the semiconductor substrate in a thickness direction.

Abstract: The invention relates to a metallization for an IGBT or a diode. In the case of this metallization, a copper layer (10, 12) having a layer thickness of approximately 50 ?m is applied to the front side and/or rear side of a semiconductor body (1) directly or if need be via a diffusion barrier layer (13, 14). The layer (8, 12) has a specific heat capacity that is at least a factor of 2 higher than the specific heat capacity of the semiconductor body (1). It simultaneously serves for producing a field stop layer (5) by proton implantation through the layer (12) from the rear side and for masking a proton or helium implantation for the purpose of charge carrier lifetime reduction from the front side of the chip (1).

Abstract: Embodiments of the invention provide a method of fabricating a semiconductor device. The method includes defining a sub-collector region in a layer of doped semiconductor material; forming an active region, a dielectric region, and a reach-through region on top of the layer of doped semiconductor material with the dielectric region separating the active region from the reach-through region; and siliciding the reach-through region and a portion of the sub-collector region to form a partially silicided conductive pathway. A semiconductor device made thereby is also provided.

Abstract: According to one exemplary embodiment, a bipolar transistor includes a base having a top surface. The bipolar transistor further includes a base oxide layer situated on the top surface of the base. The bipolar transistor further includes an antireflective coating layer situated on the base oxide layer. The bipolar transistor further includes an emitter situated over the top surface of the base and the antireflective coating layer, where a layer of polysilicon is not situated between the base oxide layer and the emitter.

Abstract: A semiconductor device is provided with a silicon substrate, with a surface for soldering the silicon substrate to a ceramic substrate, and an electrode making contact with the surface of the silicon substrate. The electrode comprises a first conductor layer, a second conductor layer, and a third conductor layer. The first conductor layer makes contact with the surface of the silicon substrate and includes aluminum and silicon. The second conductor layer makes contact with the first conductor layer and includes titanium. The third conductor layer is separated from the first conductor layer by the second conductor layer and includes nickel.

Abstract: A bipolar semiconductor device includes a collector region that is an n-type low-resistance layer formed in one surface of a semiconductor crystal substrate, an n-type first high-resistance region on the collector region, a p-type base region on the first high-resistance region, an n-type low-resistance emitter region that is formed in another surface of the semiconductor crystal substrate, an n-type second high-resistance region between the emitter region and the base region so as to contact the emitter region, an n-type recombination suppressing region around the second high-resistance region so as to adjoin the second high-resistance region, and a p-type low-resistance base contact region which is provided so as to adjoin the recombination suppressing region, and which contacts the base region. Each of doping concentrations of the second high-resistance region and the recombination suppressing region is equal to or lower than 1×1017 cm?3.

Abstract: A process for manufacturing an array of bipolar transistors, wherein deep field insulation regions of dielectric material are formed in a semiconductor body, thereby defining a plurality of active areas, insulated from each other and a plurality of bipolar transistors are formed in each active area. In particular, in each active area, a first conduction region is formed at a distance from the surface of the semiconductor body; a control region is formed on the first conduction region; and, in each control region, at least two second conduction regions and at least one control contact region are formed. The control contact region is interposed between the second conduction regions and at least two surface field insulation regions are thermally grown in each active area between the control contact region and the second conduction regions.

Abstract: A bipolar junction transistor having an emitter, a base, and a collector includes a stack of one or more layer sets adjacent the collector. Each layer set includes a first material having a first band gap, wherein the first material is highly doped, and a second material having a second band gap narrower than the first band gap, wherein the second material is at most lightly doped.

Abstract: According to one embodiment, a collector electrode including metal is used for a sink region for connecting an n+ type buried layer, so that the sink region can be narrowly formed. Further, an interval between a base region and the collector electrode can be reduced, thereby considerably decreasing the size of the transistor. Furthermore, collector resistance is reduced, so that the performance of the transistor can be improved.

Abstract: The invention relates to a method of manufacturing a semiconductor device (10) with a semiconductor body (1) which is provided with at least one semiconductor element, wherein on the surface of the semiconductor body (1) a mesa-shaped semiconductor region (2) is formed, a masking layer (3) is deposited over the mesa-shaped semiconductor region (2), a part (3A) of the masking layer (3) is removed that borders a side surface of the mesa-shaped semiconductor region (2) near its top and an electrically conducting connection region (4) is formed on the resulting structure forming a contact for the mesa-shaped semiconductor region (2). According to the invention after removal of said part (3A) of the masking layer (3) but before formation of the electrically conducting connection region (4) the mesa-shaped semiconductor region (2) is widened by an additional semiconductor region (5) at the side surface of the mesa-shaped semiconductor region (2) freed by removal of said part (3A) of the masking layer (3).

Abstract: A high-power solid-state transistor structure comprised of a plurality of emitter or gate fingers arranged in a uniform or non-uniform manner to provide improved high power performance is disclosed. Each of the fingers is associated with a corresponding one of a plurality of sub-cells. In an exemplary embodiment, the fingers may be arranged in a 1-D or 2-D form having a “hollow-center” layout where one or more elongated emitter fingers or subcells are left out during design or disconnected during manufacture. In another exemplary embodiment, the fingers may be arranged in a 1-D or 2-D form having one or more “arc-shaped” rows that includes one or more elongated emitter fingers or subcells. The structure can be practically implemented and the absolute thermal stability can be maintained for very high power transistors with reduced adverse effects due to random variation in the manufacturing and design process.

Abstract: Embodiments of the invention provide a semiconductor device including a collector in an active region; a first and a second sub-collector, the first sub-collector being a heavily doped semiconductor material adjacent to the collector and the second sub-collector being a silicided sub-collector next to the first sub-collector; and a silicided reach-through in contact with the second sub-collector, wherein the first and second sub-collectors and the silicided reach-through provide a continuous conductive pathway for electrical charges collected by the collector from the active region. Embodiments of the invention also provide methods of fabricating the same.

Abstract: A method of fabricating a bipolar junction transistor is provided herein. An isolation structure is formed on a first conductive type substrate. A second conductive type deep well is formed in the first conductive type substrate to serve as a collector. Thereafter, a second conductive type well is formed in the substrate and then a first conductive type well is formed in the substrate to serve as a base. A buffer region is formed underneath a portion of the isolation structure and between the base and the second conductive well. The buffer region together with the isolation structure isolates the base from the second conductive type well. A second conductive type emitter and a second conductive type collector pick-up region are selectively formed on the surface of the first conductive type substrate. Thereafter, a first conductive type base pick-up region is selectively formed.

Abstract: An excessive etch in the conventional manufacturing process causes a roughened surface of a contact bottom, resulting in an increased variation in characteristics of semiconductor devices. A bipolar transistor having a collector region 4 provided in a bottom of a trench formed in a P-type silicon substrate 1 is formed. An interlayer insulating film 23 is formed on the P-type silicon substrate 1. The interlayer insulating film 23 above the trench is partially etched to form a portion 30 of an opening for a collector contact. The interlayer insulating film 23 above the trench is partially etched until reaching the bottom thereof to form a residual section 32 of the opening for the collector contact. The residual section 32 of the opening for the collector contact is formed simultaneously with forming an opening 25 for an emitter contact and an opening 27 for a base contact.

Abstract: A structure comprises a single wafer with a first subcollector formed in a first region having a first thickness and a second subcollector formed in a second region having a second thickness, different from the first thickness. A method is also contemplated which includes providing a substrate including a first layer and forming a first doped region in the first layer. The method further includes forming a second layer on the first layer and forming a second doped region in the second layer. The second doped region is formed at a different depth than the first doped region. The method also includes forming a first reachthrough in the first layer and forming a second reachthrough in second layer to link the first reachthrough to the surface.

Abstract: A semiconductor device having an improved voltage control oscillator circuit is provided. The voltage control oscillator circuit includes, in combination, a variable-capacitance element and at least one bipolar transistor on a single semiconductor substrate. The variable-capacitance element includes reversely serially connected PN junctions, and junctions are formed by a single common collector layer and separated base layers on the common collector layer. The capacitance of the variable-capacitance element is generated between respective base layers of the PN junctions with the common collector layer, and varies in correspondence with the voltage applied to the common collector layer.

Abstract: A method for producing a compound semiconductor wafer used for production of HBT by vapor growth of a sub-collector layer, a collector layer, a base layer and an emitter layer in this turn on a compound semiconductor substrate using MOCVD method wherein the base layer is grown as a p-type compound semiconductor thin film layer containing at least one of Ga, Al and In as a Group III element and As as a Group V element under such growth conditions that the growth rate gives a growth determined by a Group V gas flow rate-feed.

Abstract: In the semiconductor device of the present invention, an active region is formed in an upper surface of a semiconductor substrate, and is surrounded by a trench filled with an oxide. A through-hole electrode electrically connected to the active region extends from the upper surface of the semiconductor substrate to a lower surface thereof. A bottom end of the through-hole electrode juts out of an insulating film covering the lower surface of the semiconductor substrate. Accordingly, a jutting portion of the through-hole electrode is embedded in the bonding material when the semiconductor device is mounted on a mounting board, and thus the connection reliability therebetween is improved.

Abstract: A bipolar transistor with a specific area resistance less than about 500 mOhms·mm2 comprises a first semiconductor region of a first conductivity type defining a collector region (2). A second semiconductor region of a second conductivity type defines a base region (3). A third semiconductor region of the first conductivity type defines an emitter region (4). A metal layer provides contacts (6, 7) to said base (3) and emitter regions (4). The metal layer has thickness greater than about 3 ?m.