Characterized By Their Shape, Relative Sizes Or Dispositions (epo) Patents (Class 257/E29.112)

  • Patent number: 9029866
    Abstract: A semiconductor device in provided having a substrate and a semiconductor layer formed on a main surface of the substrate. A plurality of first island electrodes and a plurality of second island electrodes are placed over the semiconductor layer. The plurality of first island electrodes and second island electrodes are spaced apart from each other so as to be alternatively arranged to produce two-dimensional active regions in all feasible areas of the semiconductor layer. Each side of the first island electrodes is opposite a side of the second island electrodes. The semiconductor device can also include a plurality of strip electrodes that are formed in the regions between the first island electrodes and the second island electrodes. The strip electrodes serve as the gate electrodes of a multi-island transistor. The first island electrodes serve as the source electrodes of the multi-island transistor. The second island electrodes serve as the drain electrodes of the multi-island transistor.
    Type: Grant
    Filed: February 3, 2011
    Date of Patent: May 12, 2015
    Assignee: Gan Systems Inc.
    Inventors: John Roberts, Ahmad Mizan, Girvan Patterson, Greg Klowak
  • Patent number: 9000538
    Abstract: A downsized semiconductor device having an excellent reverse characteristic, and a method of manufacturing the semiconductor device is sought to improve. The semiconductor device comprises a semiconductor body having a polygonal contour. An active area is formed in the semiconductor body. An EQR electrode is formed so as to surround the active area and to have curved portions of the EQR electrode along the corners of the semiconductor body. An interlayer insulating film is formed to cover the active area and the EQR electrode. The EQR electrode is embedded in the interlayer insulating film around the active area. EQR contacts are in contact with the curved portions of the EQR electrode and the semiconductor body outside the curved portions, and have at least side walls covered with the interlayer insulating film.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: April 7, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Kouichi Murakawa
  • Patent number: 8994180
    Abstract: A nonvolatile semiconductor memory includes a cell unit having a select gate transistor and a memory cell connected in series, a select gate line connected to the select gate transistor, and a word line connected to the memory cell. One end of the word line is bent to the select gate line side, and a fringe is connected between a bent point and a distal end of the word line.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: March 31, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Kamigaichi, Takeshi Murata, Itaru Kawabata
  • Patent number: 8987869
    Abstract: An integrated circuit device including an interlayer insulating layer on a substrate, a wire layer on the interlayer insulating layer, and a through-silicon-via (TSV) contact pattern having an end contacting the wire layer and integrally extending from inside of a via hole formed through the interlayer insulating layer and the substrate to outside of the via hole.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: March 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeong-gi Jin, Jeong-woo Park, Ju-il Choi
  • Patent number: 8941166
    Abstract: An integrated circuit memory comprises a set of lines each line having parallel X direction line portions in a first region and Y direction line portions in a second region. The second region is offset from the first region. The lengths of the X direction line portions are substantially longer than the lengths of the Y direction line portions. The X direction and Y direction line portions have respective first and second pitches with the second pitch being at least 3 times larger than the first pitch. Contact pickup areas are at the Y direction line portions. In some examples, the lines comprise word lines or bit lines. The memory can be created using multiple patterning methods to create lines of material and then the parallel X direction line portions and parallel Y direction line portions.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: January 27, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Shih-Hung Chen, Hang-Ting Lue
  • Patent number: 8922020
    Abstract: An integrated circuit pattern comprises a set of lines of material having X and Y direction portions. The X and Y direction portions have first and second pitches, the second pitch being larger, such as at least 3 times larger, than the first pitch. The X direction portions are parallel and the Y direction portions are parallel. The end regions of the Y direction portions comprise main line portions and offset portions. The offset portions comprise offset elements spaced apart from and electrically connected to the main line portions. The offset portions define contact areas for subsequent pattern transferring procedures. A multiple patterning method, for use during integrated circuit processing procedures, provides contact areas for subsequent pattern transferring procedures.
    Type: Grant
    Filed: January 3, 2011
    Date of Patent: December 30, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Shih-Hung Chen, Hang-Ting Lue
  • Patent number: 8907345
    Abstract: A photomask includes; a source electrode pattern including; a first electrode portion which extends in a first direction, a second electrode portion which extends in the first direction and is substantially parallel to the first electrode portion, and a third electrode portion which extends from a first end of the first electrode portion to a first end of the second electrode portion and is rounded with a first curvature, a drain electrode pattern which extends in the first direction and is disposed between the first electrode portion and the second electrode portion, wherein an end of the drain electrode pattern is rounded to correspond to the third electrode portion; and a channel region pattern which is disposed between the source electrode pattern and the drain electrode pattern, wherein a center location of the first curvature and a center location of the rounded portion of the end of the drain electrode pattern are the same.
    Type: Grant
    Filed: February 1, 2014
    Date of Patent: December 9, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yeon-Ju Kim, Sung-Jae Moon, Yun-Jung Cho, Bum-Ki Baek, Kwang-Hoon Lee, Byoung-Sun Na, Sung-Hoon Yang, Yoon-Jang Kim, Eun Cho
  • Patent number: 8890218
    Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a gate structure disposed on the substrate; a first spacer disposed on a sidewall of the gate structure; a second spacer disposed around the first spacer, wherein the second spacer comprises a L-shaped cap layer and a cap layer on the L-shaped cap layer; a source/drain disposed in the substrate adjacent to two sides of the second spacer; and a CESL disposed on the substrate to cover the gate structure, wherein at least part of the second spacer and the CESL comprise same chemical composition and/or physical property.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: November 18, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chu-Chun Chang, Chun-Mao Chiou, Chiu-Te Lee
  • Patent number: 8879013
    Abstract: A thin-film transistor liquid crystal display device includes: a substrate and a signal line, a scan line, a pixel electrode, and a thin-film transistor that are formed on the substrate. The signal line and the scan line are arranged to intersect each other. The pixel electrode is located in a pixel display zone enclosed by the intersected signal line and scan line. The thin-film transistor includes a gate terminal, a source terminal, and a drain terminal. The gate terminal is electrically connected to the scan line. The drain terminal is electrically connected to the signal line. The source terminal is arranged at a position corresponding to the intersection of the signal line and the scan line and is electrically connected to the pixel electrode.
    Type: Grant
    Filed: January 16, 2012
    Date of Patent: November 4, 2014
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventor: Cheng-Hung Chen
  • Patent number: 8866268
    Abstract: A semiconductor package structure and a manufacturing method thereof are provided. The semiconductor package structure includes a semiconductor die, a thermally conductive film, a substrate, a plurality of electrically conductive film patterns, and at least one insulator. The thermally conductive film is disposed on the bottom of the semiconductor die. The substrate is substantially comprised of the electrically conductive material or semiconductor material. Furthermore, a first hole is disposed on and passed all the way through the substrate, and the semiconductor die is disposed in the first hole. The electrically conductive film patterns are disposed on the substrate, and not contacting with each other. In addition, the insulator is connected between the semiconductor die and the substrate.
    Type: Grant
    Filed: July 15, 2011
    Date of Patent: October 21, 2014
    Assignee: Unistars Corporation
    Inventors: Shang-Yi Wu, Wen-Cheng Chien, Chia-Lun Tsai, Tien-Hao Huang
  • Patent number: 8822990
    Abstract: An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: September 2, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiroki Ohara, Toshinari Sasaki, Kosei Noda, Hideaki Kuwabara
  • Patent number: 8791528
    Abstract: A method of manufacturing a microelectronic device including forming a dielectric layer surrounding a dummy feature located over a substrate, removing the dummy feature to form an opening in the dielectric layer, and forming a metal-silicide layer conforming to the opening. The metal-silicide layer may then be annealed.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: July 29, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Tung Lin, Chih-Wei Chang, Chii-Ming Wu, Mei-Yun Wang, Chaing-Ming Chuang, Shau-Lin Shue
  • Patent number: 8786096
    Abstract: A nonvolatile semiconductor memory includes a cell unit having a select gate transistor and a memory cell connected in series, a select gate line connected to the select gate transistor, and a word line connected to the memory cell. One end of the word line is bent to the select gate line side, and a fringe is connected between a bent point and a distal end of the word line.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: July 22, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Kamigaichi, Takeshi Murata, Itaru Kawabata
  • Patent number: 8785902
    Abstract: A resistive memory device includes a lower electrode formed on a substrate, a resistive layer formed on the lower electrode, and an upper electrode on the resistive layer, wherein a lower portion of the upper electrode is narrower than an upper portion of the upper electrode.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: July 22, 2014
    Assignee: SK Hynix Inc.
    Inventors: Seok-Pyo Song, Yu-Jin Lee
  • Patent number: 8766367
    Abstract: A textured thin film transistor is comprised of an insulator sandwiched between a textured gate electrode and a semi-conductor. A source electrode and drain electrode are fabricated on a surface of the semi-conductor. The textured gate electrode is fabricated such that a surface is modified in its texture and/or geometry, such modifications affecting the transistor current.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: July 1, 2014
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Sanjiv Sambandan, Robert A. Street
  • Patent number: 8754471
    Abstract: There are provided a semiconductor device which can be miniaturized without being deteriorated in characteristics, and a manufacturing method thereof. The semiconductor device includes a semiconductor substrate having a main surface, a source region and a drain region formed apart from each other in the main surface, a gate electrode layer formed over the main surface sandwiched between the source region and the drain region, a first conductive layer formed so as to be in contact with the surface of the source region, and a second conductive layer formed so as to be in contact with the surface of the drain region. A recess is formed in the main surface so as to extend from the contact region between the first conductive layer and the source region through a part underlying the gate electrode layer to the contact region between the second conductive layer and the drain region.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: June 17, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiaki Iwamatsu, Kozo Ishikawa, Masashi Kitazawa, Kiyoshi Hayashi, Takahiro Maruyama, Masaaki Shinohara, Kenji Kawai
  • Patent number: 8742577
    Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip, and a connection member to electrically connect the first semiconductor chip and the second semiconductor chip. The connection member may include a connection pad disposed on the first semiconductor chip, a connection pillar disposed on the second semiconductor chip, and a bonding member to connect the connection pad and the connection pillar. An anti-contact layer may be formed on at least one surface of the connection pad.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: June 3, 2014
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Young-kun Jee, Sun-kyoung Seo, Sang-wook Park, Ji-hwan Hwang
  • Patent number: 8722490
    Abstract: A method of making a non-volatile MOS semiconductor memory device includes a formation phase, in a semiconductor material substrate, of isolation regions filled by field oxide and of memory cells separated each other by said isolation regions The memory cells include an electrically active region surmounted by a gate electrode electrically isolated from the semiconductor material substrate by a first dielectric layer; the gate electrode includes a floating gate defined. simultaneously to the active electrically region. A formation phase of said floating gate exhibiting a substantially saddle shape including a concavity is proposed.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: May 13, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Giorgio Servalli, Daniela Brazzelli
  • Patent number: 8710616
    Abstract: An improved die seal ring is described which includes at least one break. In the region of the break in the die seal ring, the doping is modified so that the impedance of the electrical path across the break through the substrate is increased. Offsets in the break may also be used and the offset may be within a break in a track and/or between breaks in different tracks, where the die seal ring includes more than one track.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: April 29, 2014
    Assignee: Cambridge Silicon Radio Ltd.
    Inventors: Rainer Herberholz, Howard Godfrey
  • Patent number: 8692380
    Abstract: A method of manufacture of an integrated circuit system includes: forming reticle data; detecting a sub-geometry, a singularity, or a combination thereof in the reticle data; applying a unit cell, a patch cell, or a combination thereof for removing the sub-geometry, the singularity, or the combination thereof from the reticle data; and fabricating an integrated circuit from the reticle data.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: April 8, 2014
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Soon Yoeng Tan, Huey Ming Chong, Byoung-Il Choi, Soo Muay Goh
  • Publication number: 20140077380
    Abstract: An approach for providing SRAM bit cells with double patterned metal layer structures is disclosed. Embodiments include: providing, via a first patterning process, a word line structure, a ground line structure, a power line structure, or a combination thereof; and providing, via a second patterning process, a bit line structure proximate the word line structure, the ground line structure, the power line structure, or a combination thereof. Embodiments include: providing a first landing pad as the word line structure, and a second landing pad as the ground line structure; and providing the first landing pad to have a first tip edge and a first side edge, and the second landing pad to have a second tip edge and a second side edge, wherein the first side edge faces the second side edge.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 20, 2014
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Juhan Kim, Mahbub Rashed
  • Patent number: 8629448
    Abstract: A flat panel display device including a substrate including first and second regions; an active layer on the first region of the substrate including a semiconductor material; a lower electrode on the second region of the substrate including the semiconductor material; a first insulating layer on the substrate including the active layer and the lower electrode thereon; a gate electrode on the first insulating layer overlying the active layer and including a first conductive layer pattern and a second conductive layer pattern; an upper electrode on the first insulating layer overlying the lower electrode and including the first conductive layer pattern and the second conductive layer pattern; a second insulating layer on the gate electrode and the upper electrode exposing portions of the active layer and portions of the upper electrode; and a source electrode and a drain electrode connected to the exposed portions of the active layer.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: January 14, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jin-Hee Kang, Chun-Gi You, Sun Park, Jong-Hyun Park, Yul-Kyu Lee
  • Patent number: 8598561
    Abstract: A nonvolatile memory device includes first and second conductive layers, a resistance change layer, and a rectifying element. The first conductive layer has first and second major surfaces. The second conductive layer has third and fourth major surfaces, a side face, and a corner part. The third major surface faces the first major surface and includes a plane parallel to the first major surface and is provided between the fourth and first major surfaces. The corner part is provided between the third major surface and the side face and has a curvature higher than that of the third major surface. The resistance change layer is provided between the first and second conductive layers. The rectifying element faces the second major surface of the first conductive layer. An area of the third major surface is smaller than that of the second major surface.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: December 3, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuyuki Sekine, Ryota Fujitsuka, Yoshio Ozawa
  • Patent number: 8592870
    Abstract: The present invention discloses a pseudo buried layer, a deep hole contact and a bipolar transistor, and also discloses a manufacturing method of a pseudo buried layer, including: etching a silicon substrate to form an active region and shallow trenches; sequentially implanting phosphorous ion and arsenic ion into the bottom of the shallow trenches to form phosphorus impurity regions and arsenic impurity regions; conducting thermal annealing to the phosphorus impurity regions and arsenic impurity regions. The implantation of the pseudo buried layer, adopting phosphorous with rapid thermal diffusion and arsenic with slow thermal diffusion, can improve the impurity concentration on the surface of the pseudo buried layers, reduce the sheet resistance of the pseudo buried layer, form a good ohmic contact between the pseudo buried layer and a deep hole and reduce the contact resistance, and improve the frequency characteristic and current output of triode devices.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: November 26, 2013
    Assignee: Shanghai Hua Hong NEC Electronics Co., Ltd.
    Inventors: Donghua Liu, Wensheng Qian
  • Publication number: 20130299996
    Abstract: In one embodiment, a method for forming a semiconductor device having a shield electrode includes forming first and second shield electrode contact portions within a contact trench. The first shield electrode contact portion can be formed recessed within the contact trench and includes a flat portion. The second shield electrode contact portion can be formed within the contact trench and makes contact to the first shield electrode contact portion along the flat portion.
    Type: Application
    Filed: May 14, 2012
    Publication date: November 14, 2013
    Inventor: Gordon M. Grivna
  • Patent number: 8546885
    Abstract: An integrated circuit fabrication is disclosed, and more particularly a field effect transistor with a low resistance metal gate electrode is disclosed. An exemplary structure for a metal gate electrode of a field effect transistor comprises a lower portion formed of a first metal material, wherein the lower portion has a recess, a bottom portion and sidewall portions, wherein each of the sidewall portions has a first width; and an upper portion formed of a second metal material, wherein the upper portion has a protrusion and a bulk portion, wherein the bulk portion has a second width, wherein the protrusion extends into the recess, wherein a ratio of the second width to the first width is from about 5 to 10.
    Type: Grant
    Filed: July 25, 2011
    Date of Patent: October 1, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hao Hou, Peng-Soon Lim, Da-Yuan Lee, Xiong-Fei Yu, Chun-Yuan Chou, Fan-Yi Hsu, Jian-Hao Chen, Kuang-Yuan Hsu
  • Patent number: 8519374
    Abstract: A resistive memory device includes a lower electrode formed on a substrate, a resistive layer formed on the lower electrode, and an upper electrode on the resistive layer, wherein a lower portion of the upper electrode is narrower than an upper portion of the upper electrode.
    Type: Grant
    Filed: December 28, 2010
    Date of Patent: August 27, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Seok-Pyo Song, Yu-Jin Lee
  • Patent number: 8497582
    Abstract: A nonvolatile semiconductor memory includes a cell unit having a select gate transistor and a memory cell connected in series, a select gate line connected to the select gate transistor, and a word line connected to the memory cell. One end of the word line is bent to the select gate line side, and a fringe is connected between a bent point and a distal end of the word line.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: July 30, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Kamigaichi, Takeshi Murata, Itaru Kawabata
  • Patent number: 8486788
    Abstract: A semiconductor device includes: a semiconductor substrate in which a trench is formed; a source region and a drain region each of which is buried in the trench and contains an impurity of the same conductive type; a semiconductor FIN buried in the trench and provided between the source and drain regions; a gate insulating film provided on a side surface of the semiconductor FIN as well as the upper surface of the semiconductor FIN; and a gate electrode formed on the gate insulating film.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: July 16, 2013
    Assignee: Panasonic Corporation
    Inventors: Junko Iwanaga, Takeshi Takagi, Yoshihiko Kanzawa, Haruyuki Sorada, Tohru Saitoh, Takahiro Kawashima
  • Patent number: 8426867
    Abstract: A plurality of thin film capacitor parts are provided in respective regions each surrounded by a plurality of gate metal lines (12) and a plurality of data signal lines (11) intersecting perpendicularly to each other on a glass substrate (1), and each of the thin film capacitor parts has a lower electrode (3), a gate insulating film, and an upper electrode (5), which are provided in this order. Adjacent upper electrodes (5) are electrically connected to each other via a corresponding first wire (8), which is positioned above the adjacent upper electrodes (5) and intersects with one of the data signal lines (11). This makes it possible to provide a thin film capacitor, which includes the lower electrodes (3) each having the same thickness in a center portion and an edge portion, and the upper electrodes (5) that are connected to each other by using a corresponding connecting wire with low possibility of disconnection.
    Type: Grant
    Filed: July 2, 2008
    Date of Patent: April 23, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Hiroyuki Moriwaki
  • Publication number: 20130087892
    Abstract: A system and method for providing a post-passivation opening and undercontact metallization is provided. An embodiment comprises an opening through the post-passivation which has a first dimension longer than a second dimension, wherein the first dimension is aligned perpendicular to a chip's direction of coefficient of thermal expansion mismatch. By shaping and aligning the opening through the post-passivation layer in this fashion, the post-passivation layer helps to shield the underlying layers from stresses generated from mismatches of the materials' coefficient of thermal expansion.
    Type: Application
    Filed: October 7, 2011
    Publication date: April 11, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd
    Inventors: Ming-Chih Yew, Wen-Yi Lin, Fu-Jen Li, Po-Yao Lin
  • Publication number: 20130087932
    Abstract: A method of designing an integrated circuit includes deploying an active area in a first standard cell. At least one gate electrode is routed, overlapping the active area in the first standard cell. At least one metallic line structure is routed, overlapping the active area in the first standard cell. The at least one metallic line structure is substantially parallel to the gate electrode. A first power rail is routed substantially orthogonal to the at least one metallic line structure in the first standard cell. The first power rail overlaps the at least one metallic line structure. The first power rail has a flat edge that is adjacent to the at least one metallic line structure. A first connection plug is deployed at a region where the first power rail overlaps the at least one metallic line structure in the first standard cell.
    Type: Application
    Filed: October 6, 2011
    Publication date: April 11, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURTING COMPANY, LTD.
    Inventors: Lee-Chung LU, Li-Chun TIEN, Hui-Zhong ZHUANG, Mei-Hui HUANG
  • Publication number: 20130056876
    Abstract: The present invention provides a composite electrode and method of manufacturing such a composite electrode, the method comprising the steps of: providing a first substrate layer with an electrically conducting surface; providing a non-conducting curable material; providing a second substrate layer which has a surface relief pattern defining at least one retaining feature corresponding to a desired metal track pattern; forming a line of contact between the conducting carrier layer and at least a part of the surface relief pattern; depositing curable material onto at least part of the surface relief pattern or the electrically conducting surface along the line of contact; advancing the line of contact and curing the curable material through the second substrate layer; releasing the cured material from the surface relief pattern feature so as to leave behind a surface relief pattern on the conducting carrier layer; depositing a first metal layer onto the exposed regions of the electrically conducting surface of
    Type: Application
    Filed: May 9, 2011
    Publication date: March 7, 2013
    Inventors: Thomas Harvey, Timothy George Ryan
  • Patent number: 8390098
    Abstract: A semiconductor device 100 is provided with a multiplex through plug 111 that fills an opening extending through the silicon substrate 101. The multiplex through plugs 111 comprises a column-shaped and solid first through electrode 103, a first insulating film 105 that covers the cylindrical face of the first through electrode 103, a second through electrode 107 that covers the cylindrical face of the first insulating film 105 and a second insulating film 109 that covers the cylindrical face of the second through electrode 107, and these have a common central axis. The upper cross sections of the first insulating film 105, the second through electrode 107 and the second insulating film 109 are annular-shaped.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: March 5, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Satoshi Matsui
  • Patent number: 8378496
    Abstract: The interlayer connection of the substrate is formed by a contact-hole filling (4) of a semiconductor layer (11) and metallization (17) of a recess (16) in a reverse-side semiconductor layer (13), wherein the semiconductor layers are separated from each other by a buried insulation layer (12), at whose layer position the contact-hole filling or the metallization ends.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: February 19, 2013
    Assignee: austriamicrosystems AG
    Inventors: Franz Schrank, Martin Schrems, Jochen Kraft
  • Patent number: 8362576
    Abstract: Atomic layer deposition is enhanced using plasma. Plasma begins prior to flowing a second precursor into a chamber. The second precursor reacts with a first precursor to deposit a layer on a substrate. The layer may include at least one element from each of the first and second precursors. The layer may be TaN, and the precursors may be TaF5 and NH3. The plasma may begin during purge gas flow between a pulse of the first precursor and a pulse of the second precursor. Thermal energy assists the reaction of the precursors to deposit the layer on the substrate. The thermal energy may be greater than generally accepted for ALD (e.g., more than 300 degrees Celsius).
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: January 29, 2013
    Assignee: Round Rock Research, LLC
    Inventors: Shuang Meng, Garo J. Derderian, Gurtej S. Sandhu
  • Publication number: 20120326283
    Abstract: Some embodiments include interconnect regions. The regions may contain, along a cross section, a closed-shape interior region having an electrically conductive material therein, a first dielectric material configured as a liner extending entirely around a lateral periphery of the interior region, and at least two dielectric projections joining to the dielectric material liner and being laterally outward of the interior region. The dielectric projections may have an outer dielectric ring surrounding an inner dielectric region. The outer ring may consist of the first dielectric material and the inner dielectric region may be a composition different from a composition of the first dielectric material, and in some embodiments the composition within the inner dielectric region may be gaseous.
    Type: Application
    Filed: September 7, 2012
    Publication date: December 27, 2012
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Kyle K. Kirby, Philip J. Ireland
  • Patent number: 8329574
    Abstract: Flash memory devices include a pair of elongated, closely spaced-apart main active regions in a substrate. A sub active region is also provided in the substrate, extending between the pair of elongated, closely spaced-apart main active regions. A bit line contact plug is provided on, and electrically contacting, the sub active region and being at least as wide as the sub active region. An elongated bit line is provided on, and electrically contacting, the bit line contact plug remote from the sub active region.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: December 11, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Sun Sel, Jung-Dal Choi
  • Publication number: 20120306057
    Abstract: A method for manufacturing a semiconductor device is disclosed. In the method for manufacturing the semiconductor device, a capacitor structure is modified to ensure capacitance of the capacitor, and the height of the capacitor is reduced to prevent defects such as a leaning capacitor or a poor bridge from being generated, such that the fabrication process of semiconductor devices is simplified and therefore the semiconductor devices can be stably manufactured.
    Type: Application
    Filed: January 10, 2012
    Publication date: December 6, 2012
    Applicant: Hynix Semiconductor Inc.
    Inventor: Sang Heon KIM
  • Patent number: 8324715
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate, a first insulating layer, an electrode pad, a through hole, a second insulating layer, and a conductive material. A through groove passes through the semiconductor substrate from a surface to an opposite surface. The first insulating layer fills the through groove. The electrode pad is connected with an interconnection layer. The second insulating layer is provided between the electrode pad and the first insulating layer. The through hole communicates with the electrode pad and passes through the first insulating layer and the second insulating layer. The conductive material is provided in the through hole so as to be connected with the electrode pad.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: December 4, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Mitsuyoshi Endo
  • Patent number: 8310010
    Abstract: A semiconductor device capable of dissipating heat, which has been produced in an ESD protection element, to the exterior of the device rapidly and efficiently includes an ESD protection element having a drain region, a source region and a gate electrode, and a thermal diffusion portion. The thermal diffusion portion, which has been formed on the drain region, has a metal layer electrically connected to a pad, and contacts connecting the drain region and metal layer. The metal layer has a first wiring trace extending along the gate electrode, and second wiring traces intersecting the first wiring trace perpendicularly. The contacts are connected to intersections between the first wiring trace and the second wiring traces. Heat that has been produced at a pn-junction of the ESD protection element and transferred through a contact is diffused simultaneously in three directions through the first wiring trace and second wiring trace in the metal layer and is released into the pad.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: November 13, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Mototsugu Okushima
  • Publication number: 20120248579
    Abstract: According to one embodiment, a first back surface of a first substrate and a second front surface of a second substrate are jointed together so as to connect a first conductor with a second conductor. The first conductor includes a portion having a diameter equal to that of a first gap formed above a first metal layer in a range between the first metal layer and a first front surface, and a portion having a diameter greater than that of the first gap and smaller than an outer diameter of the first metal layer in a range between the first metal layer and the first back surface. A first insulating layer has a gap formed above the first metal layer, the gap being greater than the first gap and smaller than the outer diameter of the first metal layer.
    Type: Application
    Filed: September 21, 2011
    Publication date: October 4, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Mitsuyoshi ENDO
  • Publication number: 20120228745
    Abstract: A semiconductor package structure and a manufacturing method thereof are provided. The semiconductor package structure includes a semiconductor die, a thermally conductive film, a substrate, a plurality of electrically conductive film patterns, and at least one insulator. The thermally conductive film is disposed on the bottom of the semiconductor die. The substrate is substantially comprised of the electrically conductive material or semiconductor material. Furthermore, a first hole is disposed on and passed all the way through the substrate, and the semiconductor die is disposed in the first hole. The electrically conductive film patterns are disposed on the substrate, and not contacting with each other. In addition, the insulator is connected between the semiconductor die and the substrate.
    Type: Application
    Filed: July 15, 2011
    Publication date: September 13, 2012
    Inventors: Shang-Yi WU, Wen-Cheng CHIEN, Chia-Lun TSAI, Tien-Hao HUANG
  • Patent number: 8263462
    Abstract: A semiconductor structure includes a semiconductor substrate having a first portion and a second portion. A first Fin field-effect transistor (FinFET) is formed over the first portion of the semiconductor substrate, wherein the first FinFET includes a first fin having a first fin height. A second FinFET is formed over the second portion of the semiconductor substrate, wherein the second FinFET includes a second fin having a second fin height different from the first fin height. A top surface of the first fin is substantially level with a top surface of the second fin. A punch-through stopper is underlying and adjoining the first FinFET, wherein the punch-through stopper isolates the first fin from the first portion of the semiconductor substrate.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: September 11, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Ting Hung, Cheng-Hung Chang, Chen-Yi Lee, Chen-Nan Yeh, Chen-Hua Yu
  • Patent number: 8247324
    Abstract: A method for fabricating a semiconductor device includes forming landing plugs over a substrate, forming a trench by etching the substrate between the landing plugs, forming a buried gate to partially fill the trench, forming a gap-fill layer to gap-fill an upper side of the buried gate, forming protruding portions of the landing plugs, and trimming the protruding portions of the landing plugs.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: August 21, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jong-Han Shin, Jum-Yong Park
  • Publication number: 20120175668
    Abstract: An electronic component (100), which comprises a substrate (1), at least one first electrode (3) arranged on the substrate (3) and a growth layer (7) on the side of the electrode (3) remote from the substrate (7), wherein the electrode (7) arranged on the growth layer (3) comprises a metal layer (9) with a thickness of less than or equal to 30 nm and the growth layer (7) has a thickness which is less than or equal to 10 nm. An electrical contact is also disclosed.
    Type: Application
    Filed: July 15, 2010
    Publication date: July 12, 2012
    Applicant: OSRAM Opto Semiconductors GmbH
    Inventors: Dirk Becker, Thomas Dobbertin, Thilo Reusch, Erwin Lang
  • Patent number: 8217449
    Abstract: A semiconductor device includes a semiconductor substrate including an active area defined by an device isolation region, a buried gate formed on both side walls of a trench formed in the semiconductor substrate, and a storage node contact which is buried between the buried gates, and is connected to the active region of a middle portion of the trench and the device isolation region.
    Type: Grant
    Filed: July 20, 2010
    Date of Patent: July 10, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Young Man Cho
  • Publication number: 20120161130
    Abstract: A minute electrode, a photoelectric conversion device including the minute electrode, and manufacturing methods thereof are provided. A plurality of parallel groove portions and a region sandwiched between the groove portions are formed in a substrate, and a conductive resin is supplied to the groove portions and the region and is fixed, whereby the groove portions are filled with the conductive resin and the region is covered with the conductive resin. The supplied conductive resin is not expanded outward, and the electrode with a designed width can be formed. Part of the electrode is formed over the region sandwiched between the groove portions, thus, the area of a cross section in the short axis direction can be large, and a low resistance in the long axis direction can be obtained.
    Type: Application
    Filed: December 14, 2011
    Publication date: June 28, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Yuji ODA, Takashi Hirose, Koichiro Tanaka, Sho Kato, Emi Koezuka
  • Patent number: 8198680
    Abstract: The present invention provides a method of manufacturing a semiconductor element having a miniaturized structure and a semiconductor device in which the semiconductor element having a miniaturized structure is integrated highly, by overcoming reduction of the yield caused by alignment accuracy, accuracy of a processing technique by reduced projection exposure, a finished dimension of a resist mask, an etching technique and the like. An insulating film covering a gate electrode is formed, and a source region and a drain region are exposed, a conductive film is formed thereover, a resist having a different film thickness is formed by applying the resist over the conductive film, the entire surface of the resist is exposed to light and developed, or the entire surface of the resist is etched to form a resist mask, and the conductive film is etched by using the resist mask to form a source and drain electrode.
    Type: Grant
    Filed: July 10, 2007
    Date of Patent: June 12, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Akira Ishikawa
  • Publication number: 20120139094
    Abstract: A microelectronic assembly can include first and second microelectronic elements each embodying active semiconductor devices adjacent a front surface thereof, and having an electrically conductive pad exposed at the respective front surface. An interposer of material having a CTE less than 10 ppm/° C. has first and second surfaces attached to the front surfaces of the respective first and second microelectronic elements, the interposer having a second conductive element extending within an opening in the interposer. First and second conductive elements extend within openings extending from the rear surface of a respective microelectronic element of the first and second microelectronic elements towards the front surface of the respective microelectronic element.
    Type: Application
    Filed: December 2, 2010
    Publication date: June 7, 2012
    Applicant: TESSERA RESEARCH LLC
    Inventors: Belgacem Haba, Vage Oganesian, Ilyas Mohammed, Piyush Savalia, Craig Mitchell