Abstract: The present invention discloses a method for preparing switch transistor comprising: sequentially forming a control electrode, an insulation layer, an active layer, and a source/drain metal layer of the switch transistor on a glass substrate; patterning the source/drain metal layer to expose the active layer; and proceeding an etching process to the exposed active layer in a way of gradually reducing etching rate to form a channel of the switch transistor. The present invention further discloses an equipment for etching the switch transistor. In the way mentioned above, the present invention can minimize the damages to the switch transistor and improve the reliability of the switch transistor.

Abstract: A structure and method of producing a semiconductor structure including a semi-insulating semiconductor layer, a plurality of isolated devices formed over the semi-insulating semiconductor layer, and a metal-semiconductor alloy region formed in the semi-insulating semiconductor layer, where the metal-semiconductor alloy region electrically connects two or more of the isolated devices.

Abstract: A textured thin film transistor is comprised of an insulator sandwiched between a textured gate electrode and a semi-conductor. A source electrode and drain electrode are fabricated on a surface of the semi-conductor. The textured gate electrode is fabricated such that a surface is modified in its texture and/or geometry, such modifications affecting the transistor current.

Abstract: A semiconductor device includes TFTs designed in accordance with characteristics of circuits. In a first structure of the invention, the TFT is formed by using a crystalline silicon film made of a unique crystal structure body. The crystal structure body has a structure in which rod-like or flattened rod-like crystals grow in a direction parallel to each other. In a second structure of the invention, growth distances of lateral growth regions are made different from each other in accordance with channel lengths, of the TFTs. By this, characteristics of TFTs formed in one lateral growth region can be made as uniform as possible.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed. In one embodiment, the semiconductor device may comprise a semiconductor layer, a fin formed by patterning the semiconductor layer, and a gate stack crossing over the fin. The fin may comprise a doped block region at the bottom portion thereof. According to the embodiment, it is possible to effectively suppress current leakage at the bottom portion of the fin by the block region.

Abstract: A semiconductor device may include a substrate, an active semiconductor region of the substrate, and a gate electrode. The active semiconductor region may include a channel region between first and second junction regions. The channel region may include a first semiconductor material, the first and second junction regions may include a second semiconductor material, and the first and second semiconductor materials may be different. The gate electrode may be on the channel region with portions of the first and second junction regions being free of the gate electrode.

Abstract: Provided is a semiconductor device including a substrate, and a first wiring layer, a second wiring layer, and a switch via formed on the substrate. The first wiring layer has first wiring formed therein and the second wiring layer has second wiring formed therein. The switch via connects the first wiring and the second wiring. The switch via includes at least at its bottom a switch element including a resistance change layer. A resistance value of the resistance change layer changes according to a history of an electric field applied thereto.

Abstract: A semiconductor device having a through electrode excellent in performance as for an electrode and manufacturing stability is provided. There is provided a through electrode composed of a conductive small diameter plug and a conductive large diameter plug on a semiconductor device. A cross sectional area of the small diameter plug is made larger than a cross sectional area and a diameter of a connection plug, and is made smaller than a cross sectional area and a diameter of the large diameter plug. In addition, a protruding portion formed in such a way that the small diameter plug is projected from the silicon substrate is put into an upper face of the large diameter plug. Further, an upper face of the small diameter plug is connected to a first interconnect.

Abstract: This disclosure discloses a light-emitting device comprising a substrate; and a plurality of rectifying units, comprising a first rectifying unit and a second rectifying unit, formed on the substrate for receiving and regulating an alternating current signal into a direct current signal. Each of the rectifying units comprises a contact layer and a schottky metal layer. The light-emitting device further comprises a plurality of light-emitting diodes receiving the direct current signal; and a first terminal provided on the substrate and covering the contact layer of the first rectifying unit and the schottky metal layer of the second rectifying unit.

Abstract: A semiconductor device having a through electrode excellent in performance as for an electrode and manufacturing stability is provided. There is provided a through electrode composed of a conductive small diameter plug and a conductive large diameter plug on a semiconductor device. A cross sectional area of the small diameter plug is made larger than a cross sectional area and a diameter of a connection plug, and is made smaller than a cross sectional area and a diameter of the large diameter plug. In addition, a protruding portion formed in such a way that the small diameter plug is projected from the silicon substrate is put into an upper face of the large diameter plug. Further, an upper face of the small diameter plug is connected to a first interconnect.

Abstract: A semiconductor device has pluralities of grid array terminals forming a grid array structure, e.g. a BGA structure, in which the output end of a built-in switch circuit is connected to multiple terminals of the grid array structure, thereby reducing the current that flows through each of the multiple terminals below a permissible level and minimizing the heat due to contact resistances of the multiple terminals in contact with the IC socket of the semiconductor device. Each pair of nearest neighbors of the multiple terminals is interposed by at least one further array terminal. The multiple terminals are all located at the outermost peripheral terminal positions of the grid array structure. Thus, the heat generated in the respective multiple terminals connected to the switch circuit is reduced, thereby minimizing the possibility of hazardous melting of the terminals.

Abstract: A semiconductor device may include a substrate, an active semiconductor region of the substrate, and a gate electrode. The active semiconductor region may include a channel region between first and second junction regions. The channel region may include a first semiconductor material, the first and second junction regions may include a second semiconductor material, and the first and second semiconductor materials may be different. The gate electrode may be on the channel region with portions of the first and second junction regions being free of the gate electrode.

Abstract: A semiconductor component in which the active junctions extend perpendicularly to the surface of a semiconductor chip substantially across the entire thickness thereof. The contacts with the regions to be connected are provided by conductive fingers substantially crossing the entire region with which a contact is desired to be established.

Abstract: A semiconductor device includes a base insulating film on which a silicon fuse, silicon wiring patterns, and a silicon guard ring are formed. The silicon guard ring surrounds the silicon fuse and has silicon cutout parts so as not to contact the silicon wiring patterns. A via guard ring, which has via cutout parts located above the silicon cutout parts, is formed in an interlayer insulating film and on the silicon guard ring. A metal wiring guard ring is formed on the via guard ring and the interlayer insulating film. A silicon nitride film is formed on the interlayer insulating film so as to cover the metal wiring guard ring. An interface between the interlayer insulating film and the metal wiring guard ring at the via cutout parts is covered by the silicon nitride film.

Abstract: A semiconductor device may include a substrate, an active semiconductor region of the substrate, and a gate electrode. The active semiconductor region may include a channel region between first and second junction regions. The channel region may include a first semiconductor material, the first and second junction regions may include a second semiconductor material, and the first and second semiconductor materials may be different. The gate electrode may be on the channel region with portions of the first and second junction regions being free of the gate electrode.

Abstract: A thin film transistor includes a gate part which includes a gate electrode and a light blocking electrode extending from the gate electrode. The light blocking electrode prevents a light provided from beneath the gate electrode from being guided to a semiconductor layer. The light blocking electrode is overlapped by two source electrodes and a drain electrode arranged between the two source electrodes, all of which have an I-shape. The width of the light blocking electrode is selected so that a parasitic capacitance between a source part and the gate part may be controlled. Thus, a photocurrent of the thin film transistor may be reduced, and a kickback voltage difference between pixels in the display panel may also be reduced.

Abstract: An electronic device made of group III/N materials and a method of fabricating the device. The method includes growing by epitaxy on a substrate layer the following successive layers: a layer adapted to contain an electron gas, a barrier layer, and a surface layer. The method also includes an etching step performed on at least part of the surface layer. After the etching step, an epitaxial regrowth is performed to grow a covering layer on the etched surface layer. The material of the surface layer and the material of the covering layer include at least one Group III element and nitrogen.

Abstract: Provided is a thin-film transistor (TFT) substrate. The TFT substrate includes: an insulating substrate; a semiconductor pattern which is formed on the insulating substrate, the semiconductor pattern having a top surface and a bottom surface; a source electrode and a drain electrode which are disposed on the top and bottom surfaces of the semiconductor pattern, respectively; a gate electrode which is disposed alongside the semiconductor pattern with a gate insulating film interposed therebetween; a data line which is connected to the source electrode and extends in a first direction; a gate line which is connected to the gate electrode and extends in a second direction; and a pixel electrode which is connected to the drain electrode and is formed in a pixel region.

Abstract: A silicon rectifier semiconductor device with selectable trigger and holding voltages includes a trigger element. A first well region of a first conductivity type formed within a semiconductor body. A first region of the first conductivity type is formed within the first well region. A second region of a second conductivity type is formed with the first well region. A second well region having the second conductivity type is formed within the semiconductor body adjacent the first well region. A third region of the first conductivity type is formed within the second well region. A fourth region of the second conductivity type is formed within the second well region. The trigger element is connected to the first region and alters a base trigger voltage and a base holding voltage into an altered trigger voltage and an altered holding voltage. A first terminal or pad is connected to the second region. A second terminal is connected to the third region, the fourth region, and the trigger element.

Abstract: A method of forming a field effect transistor comprising a gate formed on an insulating layer, the gate having, in a zone in contact with the insulating layer, a semiconducting central zone and lateral zones in the length of the gate, the method comprising forming a gate comprising a portion of insulating layer, a portion of semiconducting layer formed over the insulating layer, and a portion of mask layer formed over the semiconducting layer; performing an etching of the portion of the mask layer such that only a portion in the centre of the gate remains; and reacting the semiconducting gate with a metal deposited over the gate.

Abstract: A silicide layer (first silicide layer, second silicide layer) is laminated on top laminate surfaces of gates of a transmission transistor and a reset transistor, respectively. Each of the first silicide layer and the second silicide layer respectively formed on each of the gates extends in a direction along the main surface of the semiconductor substrate among at least a portion of a plurality of image pixels, connecting gates with one another among the respective image pixels. On the other hand, a signal outputter is not in contact with any silicide layers, has the top laminate surface that is covered with an insulating layer, and is connected with other transistors via a metal wiring layer.

Abstract: A semiconductor component in which the active junctions extend perpendicularly to the surface of a semiconductor chip substantially across the entire thickness thereof. The contacts with the regions to be connected are provided by conductive fingers substantially crossing the entire region with which a contact is desired to be established.

Abstract: Memory devices and methods for manufacturing are described herein. A memory device as described herein includes a first electrode layer, a second electrode layer, and a thermal isolation structure comprising a layer of thermal isolation material between the first and second electrode layers. The first and second electrode layers and the thermal isolation structure define a multi-layer stack having a sidewall. A sidewall conductor layer comprising a sidewall conductor material is on the sidewall of the multi-layer stack. The sidewall conductor material has an electrical conductivity greater than that of the thermal isolation material. A memory element comprising memory material is on the second electrode layer.

Abstract: An embedded memory device solves the problem of the low reliability of the circuit due to the unstable power source. The embedded memory includes a metal-oxide semiconductor (MOS) capacitor and a metal-insulator-metal (MIM) capacitor to increase the stability of the power source ring to stabilize the voltage of the embedded memory and stabilize the voltage for the peripheral circuit of the embedded memory.

Abstract: It is an object of the present invention, in a case of using a conductive material as part of an electrode for an organic transistor, to provide an organic transistor having a structure whose characteristics are not controlled by the work function of the conductive material. Moreover, it is other objects of the present invention to provide an organic transistor having favorable carrier mobility and to provide an organic transistor which is excellent in durability. A composite layer containing an organic compound and an inorganic material is used for an electrode for an organic field effect transistor, that is, at least part of one of a source electrode and a drain electrode in the organic field effect transistor.

Abstract: A structure and method of forming landing pads for through substrate vias in forming stacked semiconductor components are described. In various embodiments, the current invention describes landing pad structures that includes multiple levels of conductive plates connected by vias such that the electrical connection between a through substrate etch and landing pad is independent of the location of the bottom of the through substrate trench.

Abstract: A semiconductor device includes a transistor, a first diode, and a second diode. A collector of the transistor and a cathode of the first diode are electrically connected. The collector of the transistor and a cathode of the second diode are electrically connected, and an emitter of the transistor and an anode of the second diode are electrically connected. The first diode and the second diode are formed in an identical substrate. Thereby, the semiconductor device can be produced in a smaller size and in less steps.

Abstract: Leakage current generated in a PN junction diode is reduced, and charge-up current caused by plasma treatment in formation of wiring connected to the PN junction diode is controlled. An N+ region as a first conductive type impurity region provided in a Si substrate with an upper surface being exposed on one main surface of the Si substrate, a P+ polysilicon plug provided with a bottom being contacted with an upper surface of the N+ region, and wiring connected to a top of the P+ polysilicon plug are included.

Abstract: A semiconductor device may include a substrate and a fin shaped semiconductor region on the substrate. The fin shaped semiconductor region may include a channel region and first and second junction regions on opposite sides of the channel region. A gate electrode may be provided on the channel region of the fin shaped semiconductor region, and a stress inducing layer on the fin shaped semiconductor region.