Abstract: An HEMT includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer is different from the composition of the second III-V compound layer. A third III-V compound layer is disposed on the second III-V compound layer. The first III-V compound layer and the third III-V compound layer are composed of the same group III-V elements. The third III-V compound layer includes a body and numerous finger parts. Each of the finger parts is connected to the body. All finger parts are parallel to each other and do not contact each other. A source electrode, a drain electrode and a gate electrode are disposed on the first III-V compound layer.

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a first active region and a second fin active region extruded from a semiconductor substrate; an isolation featured formed in the semiconductor substrate and being interposed between the first and second fin active regions; a dielectric gate disposed on the isolation feature; a first gate stack disposed on the first fin active region and a second gate stack disposed on the second fin active region; a first source/drain feature formed in the first fin active region and interposed between the first gate stack and the dielectric gate; a second source/drain feature formed in the second fin active region and interposed between the second gate stack and the dielectric gate; a contact feature formed in a first inter-level dielectric material layer and landing on the first and second source/drain features and extending over the dielectric gate.

Abstract: The present invention relates to a semiconductor device with an asymmetric gate structure. The device comprises a substrate; a channel layer, positioned above the substrate; a barrier layer, positioned above the channel layer, the barrier layer and the channel layer being configured to form two-dimensional electron gas (2DEG), and the 2DEG being formed in the channel layer along an interface between the channel layer and the barrier layer; a source contact and a drain contact, positioned above the barrier layer; a doped group III-V layer, positioned above the barrier layer and between the drain contact and the source contact; and a gate electrode, positioned above the doped group III-V layer and configured to form a Schottky junction with the doped group III-V layer, wherein the doped group III-V layer and/or gate electrode has a non-central symmetrical geometry so as to achieve the effect of improving gate leakage current characteristics.

Abstract: Disclosed is an amplifier circuit with cross wiring of direct-current signals and microwave signals. The circuit includes a circuit network unit formed of a direct-current feeding circuit and a microwave power signal circuit. The direct-current feeding circuit comprises a high-electron-mobility transistor (HEMT) drain power-up bonding point, a corresponding line, a feeding end of a tail-level HEMT transistor core, a first Metal-Insulator-Metal (MIM) capacitor, a first micro-strip inductor, symmetrical branch micro-strips, a second MIM capacitors. The microwave power signal circuit comprises a signal end of the tail-level HEMT transistor core, two third MIM capacitors, other electrode of the second MIM capacitors, a ground micro-strip inductors, a second micro-strip inductors, a third micro-strip inductor, a fourth MIM capacitor.

Abstract: An organic light-emitting display apparatus with improved electric properties comprises: a substrate; an insulation layer which is formed on the substrate, and which includes a penetration hole; a first electrode which is formed on the insulation layer; an intermediate layer which is formed on the first electrode, and which includes an organic light-emitting layer; a second electrode which is formed on the intermediate layer; and a fixing member which is formed in the penetration hole, and which contacts the first electrode.

Abstract: The present invention features a field effect transistor forming on a semiconductor substrate having formed thereon gate, source and drain regions, with said gate region having a lateral gate channel. A plurality of spaced-apart trenches each having an electrically conductive plug formed therein in electrical communication with said gate, source and drain regions, with said trenches extend from a back surface of said semiconductor substrate to a controlled depth. A trench contact shorts the source region and a body region. A source contact is in electrical communication with said source region and a drain contact in electrical communication with said drain region, with said source and drain contacts being disposed on opposite sides of said gate channel.

Abstract: In a multiple gate transistor, the plurality of Fins of the drain or source of the transistor are electrically connected to each other by means of a common contact element, wherein enhanced uniformity of the corresponding contact regions may be accomplished by an enhanced silicidation process sequence. For this purpose, the Fins may be embedded into a dielectric material in which an appropriate contact opening may be formed to expose end faces of the Fins, which may then act as silicidation surface areas.

Abstract: A power semiconductor module comprises: a heat dissipation plate; an insulating wiring board having an upper electrode and a lower electrode, the lower electrode joined to the heat dissipation plate via a first solder; a semiconductor chip joined to the upper electrode via a second solder; a first low-k dielectric film coating sides of the lower electrode and the first solder; a second low-k dielectric film coating sides of the semiconductor chip and the second solder; a case on the heat dissipation plate and surrounding the insulating wiring board and the semiconductor chip; and an insulator filled in the case and coating the insulating wiring board, the semiconductor chip, and the first and second low-k dielectric films.

Abstract: Contact via holes are etched in a dielectric material layer overlying a semiconductor layer to expose the topmost surface of the semiconductor layer. The contact via holes are extended into the semiconductor material layer by continuing to etch the semiconductor layer so that a trench having semiconductor sidewalls is formed in the semiconductor material layer. A metal layer is deposited over the dielectric material layer and the sidewalls and bottom surface of the trench. Upon an anneal at an elevated temperature, a metal semiconductor alloy region is formed, which includes a top metal semiconductor alloy portion that includes a cavity therein and a bottom metal semiconductor alloy portion that underlies the cavity and including a horizontal portion. A metal contact via is formed within the cavity so that the top metal semiconductor alloy portion laterally surrounds a bottom portion of a bottom portion of the metal contact via.

Abstract: A first insulating film is provided between a lower interconnect and an upper interconnect. The lower interconnect and the upper interconnect are connected to each other by way of a via formed in the first insulating film. A dummy via or an insulating slit is formed on/in the upper interconnect near the via.

Abstract: An integrated circuit device includes a semiconductor substrate having a first region and second region, a conductive via positioned in the first region of the semiconductor substrate, at least one active element positioned in the second region of the semiconductor substrate, a conductive layer extending from the first region to the second region and electrically connecting the conductive via to the active element, and an auxiliary structure positioned in the first region of the semiconductor substrate and proximate to the conductive via. The auxiliary structure can be a stress-absorbing structure, and the volume of the stress-absorbing structure decreases as the volume of the conductive via increases. The auxiliary structure can be a heat-evacuating structure, and the heat-evacuating structure is configured to transfer the operating heat generated by the active element from the first region of the semiconductor substrate to the conductive via through the conductive layer.

Abstract: A semiconductor device 100 includes a semiconductor substrate 14, a connection electrode 12 disposed on an upper surface of the semiconductor substrate 14 and connected to an integrated circuit thereon, a through electrode 20 which penetrates the semiconductor substrate 14 and the connection electrode 20, and an insulation portion 30 interposed between the semiconductor substrate 14 and the through electrode 20. The through electrode 20 is integrally formed to protrude outward from upper surfaces of the semiconductor substrate 14 and the connection electrode 12, and connected to the connection electrode 12 in a region where the through electrode 20 penetrates the connection electrode 12.

Abstract: The present invention is a production method for a semiconductor device equipped with a conductive film with predetermined film thickness on a sidewall of a concave portion formed in an insulating film, and comprises a step of forming the concave portion in the insulation film formed on a semiconductor substrate. Herein, the concave portion is a generic name of a via-hole and a trench. This production method comprises a step of forming a conductive film with film thickness, which is film thickness of a conductive film to be formed in the concave portion, and which is film thickness, calculated based upon the depth of the concave portion and a projected area of the sidewall of said concave portion when viewing the concave portion from the upper surface, and to be formed over the upper surface of the insulating film where the concave portion is formed. In other words, a film is formed taking the variation of configuration of these based upon a projected area of a via-hole or a trench into consideration.

Abstract: A method of manufacturing an integrated circuit package includes: forming a substrate that includes: forming a core layer, forming vias in the core layer, and forming a conductive layer having a predetermined thickness on the core layer and having substantially twice the predetermined thickness in the vias; and forming connections between an integrated circuit die and the conductive layer.

Abstract: A semiconductor apparatus according to the present invention includes a first well-region and a second well-region in a semiconductor substrate, and a plurality of transistors formed to the second well-region. Further, the semiconductor apparatus includes a through-hole region that is formed so as to pierce through the first well-region and enables the second well-region to be electrically conductive to the semiconductor substrate on the bottom of the second well. Furthermore, in the semiconductor apparatus, the border of the through-hole region is arranged between the transistors, and is also arranged to be planarity apart from the transistor.

Abstract: A transistor includes a source, a drain and a gate. The source includes a p-doped p-body, a p+ region overlapping the p-body, an n+ region overlapping the p-body in proximity to the p+ region, and an n-doped source, heavily double-diffused (SHDD) region, only into the source region of the transistor, the SHDD region having a depth about equal to that of the first n+ region and overlapping the first n+ region. The drain includes a second n+ region and an n-doped shallow drain overlapping the second n+ region. The gate includes a gate oxide and a conductive material over the gate oxide. The SHDD region extends further laterally than the first n+ region beneath the gate oxide. The SHDD region is implanted using a dopant concentration greater than that of the n-doped shallow drain but less than that of the first n+ region.

Abstract: A semiconductor device includes: a semiconductor substrate in which a trench is formed; a source region and a drain region each of which is buried in the trench and contains an impurity of the same conductive type; a semiconductor FIN buried in the trench and provided between the source and drain regions; a gate insulating film provided on a side surface of the semiconductor FIN as well as the upper surface of the semiconductor FIN; and a gate electrode formed on the gate insulating film.

Abstract: A semiconductor memory device includes a first block having first memory cells and first select transistors, a second block having second memory cells and second select transistors, and arranged adjacent to the first block in a first direction, the second select transistor being arranged to face the first select transistor and commonly having a diffusion region with the first select transistor, a first interconnection layer provided on the diffusion region between the first and second blocks and extending in a second direction, and a second interconnection layer having a first portion provided in contact with an upper portion of the first interconnection layer and extending to a portion outside the first interconnection layer, and a second portion extending in the second direction and connected to the first portion in a portion outside a portion on the first interconnection layer.

Abstract: A first insulating film is provided between a lower interconnect and an upper interconnect. The lower interconnect and the upper interconnect are connected to each other by way of a via formed in the first insulating film. A dummy via or an insulating slit is formed on/in the upper interconnect near the via.

Abstract: A method of forming an isolated electrically conductive contact through a metal substrate by creating at least one via through the substrate. The at least one sidewall of the via is cleaned and coated with a non-conductive layer. In one example, the non-conductive layer is formed by anodizing the sidewall(s) of the via. In another example, the non-conductive layer may be formed by thin film deposition of a dielectric on the sidewall(s). An electrically conductive filler is then placed into the via. In the examples disclosed, the filler may be a conductive ink or a conductive epoxy.

Abstract: A semiconductor device includes a substrate including a compound semiconductor, a semiconductor layer formed on a surface of the substrate and a constituent of the semiconductor layer including a nitride semiconductor different from a constituent of the substrate, a via hole provided in the substrate and configured to extend from a rear surface side of the substrate to the semiconductor layer, a ground electrode formed on an inner wall of the via hole, a contact layer provided in the semiconductor layer and configured to extend from a surface of the semiconductor layer to the ground electrode, a gate electrode and a drain electrode, each of which being formed on the semiconductor layer, and a source electrode formed on the semiconductor layer and connected to the ground electrode through the contact layer.

Abstract: The trench MOS transistor according to the present invention includes a drain region in a form of a trench filled with a semiconductor material. The trench has a bottom surface and side surfaces and extends vertically downward from the top surface of the covering layer into the buried layer, the bottom surface of the trench lies in the buried layer, an insulating layer lines the side surfaces of the trenches, and the semiconductor material within the trench overlies the insulating layer and contacts the buried layer at the bottom surface of the trench.

Abstract: A DC-DC boost converter in multi-die package is proposed having an output Schottky diode and a low-side vertical MOSFET controlled by a power regulating controller (PRC). The multi-die package includes a single die pad with the Schottky diode placed there on side by side with the vertical MOSFET. The PRC die is attached atop the single die pad via an insulating die bond. Alternatively, the single die pad is grounded. The vertical MOSFET is a top drain vertical N-channel FET, the substrate of Schottky diode die is its anode. The Schottky diode and the vertical MOSFET are stacked atop the single die pad. The PRC is attached atop the single die pad via a standard conductive die bond. The Schottky diode die can be supplied in a flip-chip configuration with cathode being its substrate. Alternatively, the Schottky diode is supplied with anode being its substrate without the flip-chip configuration.

Abstract: A semiconductor device includes a transistor having a recessed gate, contact plugs formed in a region of a plurality of trenches, which are formed by recessing a semiconductor substrate. Further, a metal line and a source/drain region can be connected through the contact plug, so that on-current can be increased as much as an increased channel area.

Abstract: The characteristic of the semiconductor device of this invention is that the device has a piercing hole 10 formed in the semiconductor layer to touch a first metal film 18, a insulating film 12 formed on the side wall of the piercing hole 10, a second metal film 13 disposed on the first metal film 18 at the bottom of the piercing hole 10 where the insulating film 12 has not been formed and on the semiconductor layer, a barrier metal film 14 formed on the insulating film 12 in the piercing hole 10 and on the first metal film 18, and a wiring layer 15 formed inside the piercing hole 10 through the barrier metal film 14.

Abstract: A phase change memory device is made by processes including forming a first interlayer dielectric on a semiconductor substrate that has junction regions. Then etching the first interlayer dielectric and thereby defining contact holes that expose the junction regions. A conductive layer is formed on the first interlayer dielectric to fill the contact holes. Forming a hard mask layer on the conductive layer and etching the hard mask layer and the conductive layer to form contact plugs in the contact holes. Finally, forming a conductive layer pattern that is located on the contact plug and portions of the first interlayer dielectric adjacent to the contact plug and having a hard mask thereon.

Abstract: The present invention provides a semiconductor device having a recess-structured ohmic electrode, in which the resistance is small and variation in the resistance value caused by manufacturing irregularities is small. In the semiconductor device of the present invention, a two-dimensional electron gas layer is formed on the interface between a channel-forming layer and a Schottky layer by electrons supplied from the Schottky layer. The ohmic electrode comprises a plurality of side faces in ohmic contact with the two-dimensional electron gas layer. At least a part of side faces of the ohmic electrodes are non-parallel to a channel width direction. In a preferred embodiment of the present invention, the side faces have a saw tooth form or a comb tooth form. Since the contact area between the ohmic electrode and the two-dimensional electron gas layer is increased, ohmic resistance is reduced.

Abstract: A field effect transistor having metallic silicide layers is formed in a semiconductor layer on an insulating layer of an SOI substrate. The metallic silicide layers are composed of refractory metal and silicon. The metallic silicide layers extend to bottom surfaces of source and drain regions. A ratio of the metal to the silicon in the metallic silicide layers is X to Y. A ratio of the metal to the silicon of metallic silicide having the lowest resistance among stoichiometric metallic silicides is X0 to Y0. X, Y, X0 and Y0 satisfy the following inequality: (X/Y)>(X0/Y0).

Abstract: A first insulating film is provided between a lower interconnect and an upper interconnect. The lower interconnect and the upper interconnect are connected to each other by way of a via formed in the first insulating film. A dummy via or an insulating slit is formed on/in the upper interconnect near the via.

Abstract: A semiconductor device that reduces the interval between gate electrodes. The semiconductor device includes a semiconductor substrate, a plurality of gate electrodes buried in the semiconductor substrate, a plurality of first insulation layers arranged respectively on the plurality of gate electrodes, a conductive layer formed on the surface of the semiconductor substrate near the plurality of gate electrodes and the plurality of first insulation layers, and a conductor layer arranged on at least the conductive layer.

Abstract: In a technique to improve the high-frequency power gain of an LDMOS, the distance from the surface of a passivation film covering electrode pads to the rear surface of a silicon substrate is set into 200 ?m or less, or a trench of 2 ?m or more in thickness, in which an insulating film or a conductor is embedded, is formed between a region where a p type impurity is diffused, when a p+ type source penetrating layer is formed, and the channel region of a third LDMOS, so as to extend from the front surface of a semiconductor layer toward a silicon substrate. This trench restrains the p+ type source penetrating layer from spreading to the channel region, thereby lowering the inductance or the resistance of the source and improving the high-frequency power gain.

Abstract: Top via pattern for a bond pad structure has at least one first via group and at least one second via group adjacent to each other. The first via group has at least two line vias extending in a first direction. The second via group has at least two line vias extending in a second direction different from said first direction. The line via of the first via group does not cross the line via of the second via group.

Abstract: Methods of fabricating semiconductor devices are provided. An interlayer insulating layer is provided on a single crystalline semiconductor substrate. A single crystalline semiconductor plug is provided that extends through the interlayer insulating layer and a molding layer pattern is provided on the semiconductor substrate and the single crystalline semiconductor plug. The molding layer pattern defines an opening therein that at least partially exposes a portion of the single crystalline semiconductor plug. A single crystalline semiconductor epitaxial pattern is provided on the exposed portion of single crystalline semiconductor plug using a selective epitaxial growth technique that uses the exposed portion of the single crystalline semiconductor plug as a seed layer. A single crystalline semiconductor region is provided in the opening. The single crystalline semiconductor region includes at least a portion of the single crystalline semiconductor epitaxial pattern.