Abstract: A high-voltage MOS transistor includes a semiconductor substrate, a plurality of active regions, a gate insulation layer, and a gate electrode. The active regions are defined by an isolation structure, wherein the active regions include a channel portion and two side portions, the channel portion has first opposite sides and second opposite sides, and the two side portions are at the first opposite sides of the channel portion. The gate insulation layer is disposed on a surface of the channel portion. The gate electrode is disposed on the gate insulation layer and extending on a portion of the isolation structure, wherein the gate electrode includes a pair of channel edge openings and a plurality of slits. The pair of channel edge openings are at the second opposite sides of the channel portion to expose a portion of the gate insulation layer, and the slits are disposed over the channel portion.

Abstract: A semiconductor device includes a gate interconnect, extending in a first direction, and configured to transmit an input signal, and a transistor including gate electrodes extending in a second direction perpendicular to the first direction, and spaced apart from one another, and connected to the gate interconnect, and source and drain regions alternately arranged along the first direction, so that each gate electrode is sandwiched between the source and drain region which are adjacent to each other. The semiconductor device also includes drain interconnects, arranged above the drain regions, and connected to the drain regions, respectively, an output interconnect, connected to the drain interconnects, and configured to transmit an output signal output from the drain regions, and stubs connected to the drain interconnects, respectively. At least one of the stubs is connected to one of the drain interconnects at an end opposite from the gate interconnect.

Abstract: The disclosure relates to a display substrate, including: a base substrate including a display area and a peripheral area surrounding the display area; a first crack detection line located in the peripheral area and surrounding the display area; a second crack detection line located in the peripheral area and surrounding the display area; at least one first electrostatic discharge circuit located in the peripheral area, each including at least one first thin film transistor, the at least one first thin film transistor including a first gate; and at least one second electrostatic discharge circuit located in the peripheral area and electrically connected to the second crack detection line, each including at least one second thin film transistor, the at least one second thin film transistor including a second gate, wherein the second gate is electrically connected to the first gate.

Abstract: An apparatus includes a first drain/source region and a second drain/source region over a substrate, a first gate adjacent to the first drain/source region, the first gate comprising a plurality of first fingers forming a first comb structure, and a second gate adjacent to the second drain/source region, the second gate comprising a plurality of second fingers forming a second comb structure, wherein the plurality of first fingers and the plurality of second fingers are placed in an alternating manner, and wherein the first drain/source region, the second drain/source region, the first gate and the second gate form two back-to-back connected transistors.

Abstract: The present disclosure relates an integrated chip. The integrated chip includes an isolation region disposed within a substrate and surrounding an active area. A gate structure is disposed over the substrate and has a base region and a gate extension finger protruding outward from a sidewall of the base region along a first direction to past opposing sides of the active area. A source contact is disposed within the active area and a drain contact is disposed within the active area and is separated from the source contact by the gate extension finger. A first plurality of conductive contacts are arranged on the gate structure and separated along the first direction. The first plurality of conductive contacts are separated by distances overlying the gate extension finger.

Abstract: A layout method includes generating a design data comprising an electronic circuit, and generating a design layout by placing a first cell corresponding to the electronic circuit. The first cell includes a first source/drain region and a second source/drain region extending in a first direction in a first layer, a gate electrode extending in a second direction perpendicular to the first direction in a second layer, and a first conductive line arranged in a third layer over the second layer and electrically connected to one of the first source/drain region, the second source/drain region and the gate electrode. The first cell is defined by a left cell side and a right cell side. At least one of the left cell side, the right cell side, the gate electrode and the first conductive line extends in a third direction not parallel to the first and second directions.

Abstract: A packaged semiconductor chip includes a semiconductor sub strate having formed thereon: radio-frequency (RF) input and output contact pads, DC contact pads, and first and second amplifier stages. An input of the first amplifier stage is coupled with the RF input contact pad. An input and an output of the second amplifier stage are respectively coupled to an output of the first amplifier stage and the RF output contact pad. The DC contact pads and the input of the first amplifier stages are connected via an input bias coupling path. The outputs of the amplifier stages are connected via an output bias coupling path. The chip further includes a lead frame having RF input and output pins electrically coupled to the RF input and output contact pads, and input bias pins electrically coupled to the DC contact pad.

Abstract: A shift register circuit includes stages each including a unit circuit. The unit circuit includes: an output transistor; an internal node; and a set transistor. Two of the scan signal lines that are adjacent to each other are turned into a selected state for respective, but partially overlapping select periods. The internal node is precharged over a first precharge period by a first transistor that is the set transistor in the unit circuit in at least one of the stages. The internal node is precharged over a second precharge period by a second transistor that is the set transistor in the unit circuit in at least another one of the stages. The first precharge period is shorter than the second precharge period. The first transistor in some or all of the at least one of the stages has a higher current-drive capability than the second transistor.

Abstract: An image sensing device includes a substrate structured to include a first surface on a first side of the substrate and a second surface on a second side of the substrate opposite to the first side and to further include a first active region and a second active region in a portion of the substrate near the second surface, at least one photoelectric conversion element formed in the substrate, and structured to generate photocharges by performing photoelectric conversion of incident light received through the first surface of the substrate, a floating diffusion region formed near the second surface of the substrate, and structured to receive the photocharges from the photoelectric conversion element and temporarily store the received photocharges, a transistor formed in the first active region, and structured to include a first source/drain region coupled to the floating diffusion region, and a well pickup region formed in the second active region, and structured to apply a bias voltage to the substrate.

Abstract: In a power amplifier module for performing slope control of a transmitting signal, a gain variation due to a variation in battery voltage is suppressed while suppressing an increase in circuit size. The power amplifier module includes: a first regulator for outputting a first voltage corresponding to a control voltage for controlling a signal level; a second regulator for outputting a second voltage that rises as a battery voltage drops; a first amplifier supplied with the first voltage as a power-supply voltage to amplify an input signal and output an amplified signal; and a second amplifier for amplifying the amplified signal, wherein the second amplifier includes a first amplification unit supplied with the second voltage as the power-supply voltage to amplify the amplified signal, and a second amplification unit supplied with the battery voltage as the power-supply voltage to amplify the amplified signal.

Abstract: In a power amplifier module for performing slope control of a transmitting signal, a gain variation due to a variation in battery voltage is suppressed while suppressing an increase in circuit size. The power amplifier module includes: a first regulator for outputting a first voltage corresponding to a control voltage for controlling a signal level; a second regulator for outputting a second voltage that rises as a battery voltage drops; a first amplifier supplied with the first voltage as a power-supply voltage to amplify an input signal and output an amplified signal; and a second amplifier for amplifying the amplified signal, wherein the second amplifier includes a first amplification unit supplied with the second voltage as the power-supply voltage to amplify the amplified signal, and a second amplification unit supplied with the battery voltage as the power-supply voltage to amplify the amplified signal.

Abstract: Thin film transistors having a high current drive capability and a suitable threshold voltage are provided. The thin film transistor includes a gate electrode, an insulating layer formed on the gate electrode, a semiconductor layer formed on the insulating layer, and source/drain electrodes formed on the semiconductor layer. The semiconductor layer includes a plurality of regions separated from each other in a longitudinal direction of the source/drain electrodes.

Abstract: Performance of a FinFET is enhanced through a structure that exerts physical stress on the channel. The stress is achieved by a combination of tungsten contacts for the source and drain, epitaxially grown raised source and raised drain, and manipulation of aspects of the tungsten contact deposition resulting in enhancement of the inherent stress of tungsten. The stress can further be enhanced by epitaxially re-growing the portion of the raised source and drain removed by etching trenches for the contacts and/or etching deeper trenches (and corresponding longer contacts) below a surface of the fin.

Abstract: A semiconductor device includes a cell region including memory cells that have a selection element and a data storage element, and a driving circuit region including a driving transistor configured to operate the selection element. The driving transistor includes active portions defined by a device isolation pattern in a substrate and a gate electrode running across the active portion along a first direction, the gate electrode including channel portions of a ring-shaped structure. The driving transistor further includes first impurity doped regions disposed in the active portions that are surrounded by channel portions, and second impurity doped regions disposed in the active portion that are separated from the first impurity doped regions by the channel portions.

Abstract: A power array with a staggered arrangement for improving on-resistance and safe operating area of a device is provided. Each power array includes two or more rows with a plurality of parallel device units arranged along the row. Each device unit includes a source region, a drain region, and a gate disposed between the source region and the drain region, wherein each drain region is offset from the adjacent drain region of adjacent rows in a row direction.

Abstract: A thin film transistor includes a semiconductor pattern disposed on a substrate and a semiconductor pattern portion with a conductive or nonconductive characteristic, and a anti-diffusion portion on a side of the semiconductor pattern portion to prevent metal ions from being diffused along the semiconductor pattern portion. A first insulating layer covers the semiconductor pattern and has a first contact hole exposing a first region of the semiconductor pattern portion and a second contact hole exposing a second region of the semiconductor pattern portion. A gate electrode is disposed on the first insulating layer. A second insulating layer covers the gate electrode and has a third contact hole exposing the first region and a fourth contact hole exposing the second region. A source electrode is formed on the second insulating layer and connected to the first region, and a drain electrode is formed on the second insulating layer and connected to the second region.

Abstract: The semiconductor device includes a gate electrode over a substrate, a gate insulating layer over the gate electrode, an oxide semiconductor layer over the gate insulating layer, and a source electrode and a drain electrode over the oxide semiconductor layer. A length of part of an outer edge of the oxide semiconductor layer from an outer edge of the source electrode to an outer edge of the drain electrode is more than three times, preferably more than five times as long as a channel length of the semiconductor device. Further, oxygen is supplied from the gate insulating layer to the oxide semiconductor layer by heat treatment. In addition, an insulating layer is formed after the oxide semiconductor layer is selectively etched.

Abstract: The invention relates to semiconductor components, in particular to a scalable construction for lateral semiconductor components having high current-carrying capacity. A transistor cell according to the invention comprises a control electrode (203), a plurality of source fields (201) and a plurality of drain fields (202). The control electrode completely encloses at least one of the source fields or drain fields. A transistor according to the invention comprises a plurality of transistor cells on a substrate, each of which comprises a source contact field (206) and/or a drain contact field (207). The source contact fields are conductively connected to each other on the other side of the substrate and the drain contact fields are likewise conductively connected to each other on the other side of the substrate.

Abstract: A semiconductor device includes: a substrate; a transistor that has a ring-shaped gate electrode formed on the substrate; a plurality of external dummy electrodes that are arranged outside the gate electrode and are formed in the same layer as the gate electrode; and at least one internal dummy electrode that is arranged inside the gate electrode and is formed in the same layer as the gate electrode.

Abstract: Semiconductor devices with guard rings are described. The semiconductor devices may be, e.g., transistors and diodes designed for high-voltage applications. A guard ring is a floating electrode formed of electrically conducting material above a semiconductor material layer. A portion of an insulating layer is between at least a portion of the guard ring and the semiconductor material layer. A guard ring may be located, for example, on a transistor between a gate and a drain electrode. A semiconductor device may have one or more guard rings.

Abstract: A thin-film transistor liquid crystal display device includes: a substrate and a signal line, a scan line, a pixel electrode, and a thin-film transistor that are formed on the substrate. The signal line and the scan line are arranged to intersect each other. The pixel electrode is located in a pixel display zone enclosed by the intersected signal line and scan line. The thin-film transistor includes a gate terminal, a source terminal, and a drain terminal. The gate terminal is electrically connected to the scan line. The drain terminal is electrically connected to the signal line. The source terminal is arranged at a position corresponding to the intersection of the signal line and the scan line and is electrically connected to the pixel electrode.

Abstract: The component incorporates, in topological terms, a scalable number of triac structures in a concentric annular arrangement. The component can be used with an electronic device to protect against electrostatic discharges. For example, the components can be used to protect the input/output pad, the first power supply terminal, and the second power supply terminal of an integrated circuit against electrostatic discharges.

Abstract: A semiconductor layout structure includes multiple active blocks which are disposed on a substrate, parallel with one another and extending along a first direction, multiple first shallow trench isolations which are disposed on a substrate, parallel with one another and respectively disposed on the multiple active blocks, and multiple second shallow trench isolations which are disposed on a substrate, cutting through multiple active blocks and extending along a second direction. The first direction has an angle about 1 degree to about 53 degrees to the second direction.

Abstract: A semiconductor fabrication technique cuts loops formed in a spacer pattern. The spacer pattern is a split loop pattern which generally includes a symmetric arrangement of one or more loops in each of four quadrants which are defines with respect to a reference point. The loops can be peaks or trenches. Each quadrant can include one loop, or multiple nested loops. Further, the space pattern includes a single cross, or multiple nested crosses, which extend between the loops. A cut out area is defined which extends outward from the reference point to closed ends of the loops, also encompassing a central portion of the cross. When a metal wiring layer pattern is formed using the spacer pattern with the cut out area, metal wiring is excluded from the cut out area. The loop ends in the metal wiring layer are broken and can be used as independent active lines.

Abstract: An LDMOS device includes a gate which is formed on and/over over a substrate; a source and a drain which are arranged to be separated from each other on both sides of the substrate with the gate interposed therebetween; and a field oxide film formed to have a step between the gate and the drain. The LDMOS device further includes a drift region formed of first conduction type impurity ions between the gate and the drain in the substrate; and at least one internal field ring formed in the drift region by selectively implanting a second conduction type impurity in accordance with the step of the field oxide film.

Abstract: A semiconductor device of the present invention includes: a lower electrode (110); a contact layer (130) including a first contact layer (132), a second contact layer (134) and a third contact layer (136) overlapping with a semiconductor layer (120); and an upper electrode (140) including a first upper electrode (142), a second upper electrode (144) and a third upper electrode (146). The second contact layer (134) includes a first region (134a), and a second region (134b) separate from the first region (134a), and the second upper electrode (144) is directly in contact with the semiconductor layer (120) in a region between the first region (134a) and the second region (134b) of the second contact layer (134).

Abstract: A photomask includes; a source electrode pattern including; a first electrode portion which extends in a first direction, a second electrode portion which extends in the first direction and is substantially parallel to the first electrode portion, and a third electrode portion which extends from a first end of the first electrode portion to a first end of the second electrode portion and is rounded with a first curvature, a drain electrode pattern which extends in the first direction and is disposed between the first electrode portion and the second electrode portion, wherein an end of the drain electrode pattern is rounded to correspond to the third electrode portion; and a channel region pattern which is disposed between the source electrode pattern and the drain electrode pattern, wherein a center location of the first curvature and a center location of the rounded portion of the end of the drain electrode pattern are the same.

Abstract: A semiconductor fabrication technique cuts loops formed in a spacer pattern. The spacer pattern is a split loop pattern which generally includes a symmetric arrangement of one or more loops in each of four quadrants which are defines with respect to a reference point. The loops can be peaks or trenches. Each quadrant can include one loop, or multiple nested loops. Further, the space pattern includes a single cross, or multiple nested crosses, which extend between the loops. A cut out area is defined which extends outward from the reference point to closed ends of the loops, also encompassing a central portion of the cross. When a metal wiring layer pattern is formed using the spacer pattern with the cut out area, metal wiring is excluded from the cut out area. The loop ends in the metal wiring layer are broken and can be used as independent active lines.

Abstract: By locally adapting the size and/or density of a contact structure, for instance, within individual transistors or in a more global manner, the overall performance of advanced semiconductor devices may be increased. Hence, the mutual interaction between the contact structure and local device characteristics may be taken into consideration. On the other hand, a high degree of compatibility with conventional process strategies may be maintained.

Abstract: According to one embodiment, a semiconductor device, including a semiconductor layer including a first region and a second region isolated from the first region, a source in a surface of the first region, a drain in a surface of the second region, a back-gate in the surface of the first region, an end of a drain side of the back-gate being located closer to the drain side than an end of the drain side of the source, a gate insulator on a surface of the semiconductor layer between the first region and the second region, a gate electrode on the gate insulator, a source electrode being contacted to both the source and the back-gate, and a drain electrode being contacted to the drain area.

Abstract: A semiconductor device comprises a source region, a drain region, and a drift region between the source and drain regions. A split gate is disposed over a portion of the drift region, and between the source and drain regions. The split gate includes first and second gate electrodes separated by a gate oxide layer. A super-junction structure is disposed within the drift region between the gate and the drain region.

Abstract: Disclosed is a semiconductor device wherein device characteristics are improved by applying a strong stress to a channel region. The semiconductor device includes a semiconductor substrate, a gate insulating film formed over a first plane of the semiconductor substrate, a gate electrode formed over the gate insulating film, a gate sidewall insulating film formed over the sidewall of the gate electrode, source/drain diffusion layer regions into which impurities are implanted, the source/drain diffusion layer regions being adjacent to a channel region formed in the semiconductor substrate below the gate electrode, and a stress applying film formed over the source/drain diffusion layer regions except over the upper part of the gate electrode; and recesses or protrusions are formed in the region where the source/drain diffusion layer regions are formed over the first plane of the semiconductor substrate.

Abstract: An integrated circuit structure includes a fin field-effect transistor (FinFET) including a semiconductor fin over and adjacent to insulation regions; and a source/drain region over the insulation regions. The source/drain region includes a first and a second semiconductor region. The first semiconductor region includes silicon and an element selected from the group consisting of germanium and carbon, wherein the element has a first atomic percentage in the first semiconductor region. The first semiconductor region has an up-slant facet and a down-slant facet. The second semiconductor region includes silicon and the element. The element has a second atomic percentage lower than the first atomic percentage. The second semiconductor region has a first portion on the up-slant facet and has a first thickness. A second portion of the second semiconductor region, if any, on the down-slant facet has a second thickness smaller than the first thickness.

Abstract: A seal ring structure for an integrated circuit includes a seal ring being disposed along a periphery of the integrated circuit and being divided into at least a first portion and a second portion, wherein the second portion is positioned facing an analog and/or RF circuit block and is different from the first portion in structure. A P+ region is provided in a P substrate and positioned under the second portion. A shallow trench isolation (STI) structure surrounds the P+ region and laterally extends underneath a conductive rampart of the second portion.

Abstract: Semiconductor devices including a plurality of unit cells connected in parallel are provided. Each of the unit cells have a first electrode, a second electrode and a gate finger. One of the first electrodes at a center of the semiconductor device has a first width and one of the first electrodes at a periphery of the semiconductor device has a second width, smaller than the first width. The second electrodes have a substantially constant width such that a pitch between the gate fingers is non-uniform. Related methods are also provided.

Abstract: A seal ring structure disposed along a periphery of an integrated circuit. The seal ring is divided into at least a first portion and a second portion. The second portion is positioned facing and shielding an analog and/or RF circuit block from a noise. A deep N well is disposed in a P substrate and is positioned under the second portion. The deep N well reduces the substrate noise coupling.

Abstract: A layout structure of a MOSFET is provided. The layout structure of the MOSFET includes a plurality of MOSFET cells, a first source/drain metal bus structure and a second source/drain metal bus structure. The first source/drain metal bus structure is electrically connected to first sources/drains of the MOSFET cells, and a width thereof is gradually decreased in a predetermined direction. The second source/drain metal bus structure is electrically connected to second sources/drains of the MOSFET cells, and a width thereof is gradually increased in the predetermined direction.

Abstract: A semiconductor device includes a body region having a source region, a drain region, a channel region interposed between the source region and the drain region, and a body region extension extending from an end of the channel region. A gate pattern is formed on the channel region and the body region, and a body contact connects the gate pattern to the body region. A sidewall of the body region extension is self-aligned to a sidewall of the gate pattern. Methods of forming semiconductor devices having a self-aligned body and a body contact are also disclosed.

Abstract: A semiconductor device, which is connected to a protected device and protects a protected device, includes a semiconductor layer provided on an insulating film; a plurality of source layers which is formed in the semiconductor layer and extends in a first direction; a plurality of drain layers which is formed in the semiconductor layer and extends along with the source layers; a plurality of body regions which is provided between the source layers and the drain layers in the semiconductor layer and extends in the first direction; and at least one body connecting part connecting the plurality of body regions, wherein a first width between the source layer and the drain layer at a first position is larger than a second width between the source layer and the drain layer at a second position, the second position is closer to the body connecting part than the first position.

Abstract: A nanostructure pattern which includes pairs of metal lines separated by identical gaps whose dimensions are in the nanometer range, can be prepared by providing a separating sacrificial layer, whose dimensions can be controlled precisely, in the separation gap between the first metal line and the second metal line. The sacrificial layer is removed at the end of the fabrication, leaving a precisely dimensioned gap between the lines.

Abstract: In a semiconductor memory device which includes a shared sense amplifier portion, a pair of memory cell portions disposed on opposite sides of the shared sense amplifier portion, a pair of transfer gates between the pair of memory cell portions and the shared sense amplifier portion, and bit lines constituting a plurality of bit line pairs and connecting the pair of memory cell portions to each other through the pair of transfer gates and the shared sense amplifier portion, the bit lines in a bit line pair of the plurality of bit line pairs are twisted at a substantial center between the pair of transfer gates on the opposite sides.

Abstract: The present invention is directed to manufacturing an organic transistor with an organic semiconductor film formed by a coating method, without involving a process of forming a rib for forming the organic semiconductor film. To be more specific, the organic transistor of the present invention includes: (1) a source electrode part and a drain electrode part which are formed on a substrate; (2) rib selectively formed on part of the source electrode part and the drain electrode part; (3) an organic semiconductor film placed in the region defined by the ribs and connecting the source electrode part and the drain electrode part; and (4) a gate electrode formed on the organic semiconductor film through a gate insulating film. The organic transistor of the present invention is characterized in that there is a gap between the rib formed on the source electrode part and the rib formed on the drain electrode part.

Abstract: Provided are a semiconductor device which can be manufactured at low cost and has a low on-resistance and a high withstand voltage, and its manufacturing method. The semiconductor device comprises an N-type well area formed on a P-type semiconductor substrate, a P-type body area formed within the well area, an N-type source area formed within the body area, an N-type drain area formed at a distance from the body area within the well area, a gate insulating film formed so as to overlay a part of the body area, a gate electrode formed on the gate insulating film and a P-type buried diffusion area which makes contact with the bottom of the body area and extends to an area beneath the drain area in a direction parallel to the surface of the semiconductor substrate within the well area.

Abstract: A lateral DMOS-transistor is provided that includes a MOS-diode made of a semi-conductor material of a first type of conductivity, a source-area of a second type of conductivity and a drain-area of a second type of conductivity which is separated from the MOS-diode by a drift region made of a semi-conductor material of a second type of conductivity which is at least partially covered by a dielectric gate layer which also covers the semi-conductor material of the MOS-diode. The dielectric gate-layer comprises a first region of a first thickness and a second region of a second thickness. The first region covers the semi-conductor material of the MOS-diode and the second region is arranged on the drift region. A transition takes place from the first thickness to the second thickness such that an edge area of the drift region which is oriented towards the MOS-diode is arranged below the second area of the gate layer. The invention also relates to a method for the production of these types of DMOS-transistors.

Abstract: By locally adapting the size and/or density of a contact structure, for instance, within individual transistors or in a more global manner, the overall performance of advanced semiconductor devices may be increased. Hence, the mutual interaction between the contact structure and local device characteristics may be taken into consideration. On the other hand, a high degree of compatibility with conventional process strategies may be maintained.

Abstract: An RF field effect transistor has a gate electrode, and comb shaped drain and source electrodes, fingers of the comb shaped drain being arranged to be interleaved with fingers of the source electrode, the source and drain electrodes having multiple layers (110,120,130,140). An amount of the interleaving is different in each layer, to enable optimization, particularly for low parasitic capacitance without losing all the advantage of low current density provided by the multiple layers. The interleaving is reduced for layers further from the gate electrode by having shorter fingers. The reduction in interleaving can be optimized for minimum capacitance, by a steeper reduction in interleaving, or for minimum lateral current densities in source and drain fingers, by a more gradual reduction in interleaving. This can enable operation at higher temperatures or at higher input bias currents, while still meeting the requirements of electro-migration rules.

Abstract: A phase change memory device is provided in which the area of contact between phase change material and heater electrode is reduced to suppress current required for heating and a phase change region is formed directly on a contact to raise the degree of integration. The device comprises a heater electrode in which the lower part thereof is surrounded by a side wall of a first insulating material and the upper part thereof protruding from the side wall has a sharp configuration covered by a second insulating material except for a part of the tip end thereof, and the exposed tip end is coupled to the phase change material layer.

Abstract: Semiconductor devices are provided. A semiconductor device can include a substrate and a plurality of dummy line patterns on the substrate that extend in a first direction parallel with one another. Each of the dummy line patterns can include a plurality of sub-line patterns aligned along the first direction and which are separated from each other by at least one cutting region therebetween. The dummy line patterns can include first and second dummy line patterns which are adjacent to each other in a second direction that is perpendicular to the first direction. At least one of the cutting regions between a pair of sub-line patterns of the first dummy line pattern is aligned with and bounded by one of the sub-line patterns of the second dummy line pattern in the second direction.

Abstract: A power transistor includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region overlying a first major surface, a control electrode coupled to a control electrode interconnection region overlying the first major surface, and a second electrode coupled to a second electrode interconnection region overlying a second major surface. Each transistor cell has an approximately constant doping concentration in the channel region. A dielectric platform is used as an edge termination of an epitaxial layer to maintain substantially planar equipotential lines therein. The power transistor finds particular utility in radio frequency applications operating at a frequency greater than 500 megahertz and dissipating more than 5 watts of power. The semiconductor die and package are designed so that the power transistor can efficiently operate under such severe conditions.

Abstract: The trench MOS transistor according to the present invention includes a drain region in a form of a trench filled with a semiconductor material. The trench has a bottom surface and side surfaces and extends vertically downward from the top surface of the covering layer into the buried layer, the bottom surface of the trench lies in the buried layer, an insulating layer lines the side surfaces of the trenches, and the semiconductor material within the trench overlies the insulating layer and contacts the buried layer at the bottom surface of the trench.