Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes a source feature and a drain feature, a channel structure disposed between the source feature and the drain feature, a semiconductor layer disposed over the channel structure and the drain feature, a dielectric layer disposed over the semiconductor layer, a backside source contact over the source feature and extending through the semiconductor layer and the dielectric layer, and a backside power rail disposed over the dielectric layer and in contact with the backside source contact.

Abstract: A semiconductor device having a field-effect transistor, including a trench in a semiconductor substrate, a first insulating film in the trench, an intrinsic polycrystalline silicon film over the first insulating film, and first conductivity type impurities in the intrinsic polycrystalline silicon film to form a first conductive film. The first conductive film is etched to form a first gate electrode in the trench. A second insulating film is also formed in the trench above the first insulating film and the first gate electrode, and a first conductivity type doped polycrystalline silicon film, having higher impurity concentration than the first gate electrode is formed over the second insulating film. The doped polycrystalline silicon film is provided in an upper part of the trench to form a second gate electrode.

Abstract: In a general aspect, an apparatus can include a semiconductor layer of a first conductivity type, the semiconductor layer having a top-side surface. The apparatus can also include a well region of a second conductivity type opposite the first conductivity type, the well region being disposed in an upper portion of the semiconductor layer. The apparatus can further include a gate trench disposed in the semiconductor layer, the gate trench extending through the well region, and a drain contact disposed, at least in part, on the top-side surface of the semiconductor layer, the drain contact being adjacent to the well region. The apparatus can still further include an isolation trench disposed between the drain contact and the gate trench in the semiconductor layer, the isolation trench extending through the well region.

Abstract: A vertical conduction power device includes respective gate, source and drain areas formed in an epitaxial layer on a semiconductor substrate. The respective gate, source and drain metallizations are formed by a first metallization level. The gate, source and drain terminals are formed by a second metallization level. The device is configured as a set of modular areas extending parallel to each other. Each modular area has a rectangular elongate source area perimetrically surrounded by a gate area, and a drain area defined by first and second regions. The first regions of the drain extend parallel to one another and separate adjacent modular areas. The second regions of the drain area extend parallel to one another and contact ends of the first regions of the drain area.

Abstract: The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a semiconductor layer on the sidewalls and bottom of the opening; a dielectric layer on the semiconductor layer; and a metal layer filling an opening of the dielectric layer.

Abstract: Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET). One embodiment of this invention includes creating this differential stress by varying the deposition conditions for forming PFET and NFET contacts, for example, the temperature at which the fill materials are deposited, and the rate at which the fill materials are deposited. In another embodiment, the differential stress is created by filling the contacts with differing materials that will impart differential stress due to differing coefficient of thermal expansions. In another embodiment, the differential stress is created by including a silicide layer within the NFET contacts and/or the PFET contacts.

Abstract: The present invention features a field effect transistor forming on a semiconductor substrate having formed thereon gate, source and drain regions, with said gate region having a lateral gate channel. A plurality of spaced-apart trenches each having an electrically conductive plug formed therein in electrical communication with said gate, source and drain regions, with said trenches extend from a back surface of said semiconductor substrate to a controlled depth. A trench contact shorts the source region and a body region. A source contact is in electrical communication with said source region and a drain contact in electrical communication with said drain region, with said source and drain contacts being disposed on opposite sides of said gate channel.

Abstract: Provided are a semiconductor device, which can facilitate a salicide process and can prevent a gate from being damaged due to misalign, and a method of manufacturing of the semiconductor device. The method includes forming a first insulation layer pattern on a substrate having a gate pattern and a source/drain region formed at both sides of the gate pattern, the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source/drain region, forming a second insulation layer on the entire surface of the substrate to cover the first insulation layer pattern and the silicide layer, and forming a contact hole in the second insulation layer to expose the silicide layer.

Abstract: An active matrix substrate includes a plurality of scanning lines (11a) extending parallel to each other; a plurality of signal lines (16a) extending parallel to each other in a direction crossing the scanning lines (11a); a plurality of TFTs (5) each provided at each of intersections of the scanning lines (11a) and the signal lines (16a), and each including a semiconductor layer (4a); and a coating type insulating layer formed between each of the scanning lines (11a) and each of the signal lines (16a). A plurality of openings (15a) are formed in the insulating layer such that each of the semiconductor layers (4a) is exposed, and at least part of a peripheral end of the opening (15a) of the insulating layer is positioned on an inner side relative to each of peripheral ends of the semiconductor layers (4a).

Abstract: A high-voltage integrated circuit device has formed therein a high-voltage junction terminating region that is configured by a breakdown voltage region formed of an n-well region, a ground potential region formed of a p-region, a first contact region and a second contact region. An opposition section of the high-voltage junction terminating region, whose distance to an intermediate-potential region formed of a p-drain region is shorter than those of other sections, is provided with a resistance higher than those of the other sections. Accordingly, a cathode resistance of a parasitic diode formed of the p-region and the n-well region increases, locally reducing the amount of electron holes injected at the time of the input of a negative-voltage surge. As a result, an erroneous operation or destruction of a logic part of a high-side circuit can be prevented when the negative-voltage surge is applied to an H-VDD terminal or a Vs terminal.

Abstract: A semiconductor device including a connecting structure includes an edge region, a first trench and a second trench running toward the edge region, a first electrode within the first trench, and a second electrode within the second trench, the first and second electrodes being arranged in a same electrode plane with regard to a main surface of a substrate of the electronic device within the trenches, and the first electrode extending, at an edge region side end of the first trench, farther toward the edge region than the second electrode extends, at an edge region side end of the second trench, toward the edge region.

Abstract: A laterally diffused metal-oxide-semiconductor transistor device includes a substrate having a first conductivity type with a semiconductor layer formed over the substrate. A source region and a drain extension region of the first conductivity type are formed in the semiconductor layer. A body region of a second conductivity type is formed in the semiconductor layer. A conductive gate is formed over a gate dielectric layer that is formed over a channel region. A drain contact electrically connects the drain extension region to the substrate and is laterally spaced from the channel region. The drain contact includes a highly-doped drain contact region formed between the substrate and the drain extension region in the semiconductor layer, wherein a topmost portion of the highly-doped drain contact region is spaced from the upper surface of the semiconductor layer. A source contact electrically connects the source region to the body region.

Abstract: A vertical conduction electronic power device includes respective gate, source and drain areas in an epitaxial layer arranged on a semiconductor substrate. The respective gate, source and drain metallizations may be formed by a first metallization level. Corresponding gate, source and drain terminals or pads may be formed by a second metallization level. The power device is configured as a set of modular areas extending parallel to each other, each having a rectangular elongate source area perimetrically surrounded by a narrow gate area. The modular areas are separated from each other by regions with the drain area extending parallel and connected at the opposite ends thereof to a second closed region with the drain area forming a device outer peripheral edge.

Abstract: A lower raised source/drain region is formed on a planar source/drain region of a planar field effect transistor or a surface of a portion of semiconductor fin adjoining a channel region of a fin field effect transistor. At least one contact-level dielectric material layer is formed and planarized, and a contact via hole extending to the lower raised source/drain region is formed in the at least one contact-level dielectric material layer. An upper raised source/drain region is formed on a top surface of the lower raised source/drain region. A metal semiconductor alloy portion and a contact via structure are formed within the contact via hole. Formation of the upper raised source/drain region is limited to a bottom portion of the contact via hole, thereby preventing formation of, and increase of parasitic capacitance by, any additional raised structure in source/drain regions that are not contacted.

Abstract: A laterally diffused metal oxide semiconductor transistor. The laterally diffused metal oxide semiconductor transistor includes a substrate, a drain formed thereon, a source formed on the substrate, comprising a plurality of individual sub-sources respectively corresponding to various sides of the drain, a plurality of channels formed in the substrate between the sub-sources and the drain, a gate overlying a portion of the sub-sources and the channels, and a drift layer formed in the substrate underneath the drain.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises: a semiconductor substrate; a source region and a drain region defined in the semiconductor substrate respectively, and a trench formed in the source region and/or the drain region, in which a rare earth oxide layer is formed in the trench; a source and/or a drain formed on the rare earth oxide layer; and a channel region formed between the source and the drain. A relationship between a lattice constant a of the rare earth oxide layer and a lattice constant b of a semiconductor material of the source and/or the drain and/or the channel region is a=(n±c)b, where n is an integer, c is a mismatch ratio of lattice constants, and 0<c?15%.

Abstract: Disclosed is a semiconductor component arrangement and a method for producing a semiconductor component arrangement. The method comprises producing a trench transistor structure with at least one trench disposed in the semiconductor body and with at least an gate electrode disposed in the at least one trench. An electrode structure is disposed in at least one further trench and comprises at least one electrode. The at least one trench of the transistor structure and the at least one further trench are produced by common process steps. Furthermore, the at least one electrode of the electrode structure and the gate electrode are produced by common process steps.

Abstract: A gate stack is formed on a silicon substrate, and source/drain extension regions are formed around the gate stack. A dielectric spacer is formed around the gate stack. A pair of trenches is formed around the gate stack and the dielectric spacer by an etch so that sidewalls of the source/drain extension regions are exposed. Within each trench, an n-doped silicon liner is deposited on the sidewalls of the trenches by a first selective epitaxy process so that the interface between the dielectric spacer and the source/drain extension region is covered. Within each trench, an n-doped single crystalline silicon-carbon alloy is subsequently deposited to fill the trench by a second selective epitaxy process. A combination of an n-doped single crystalline silicon liner and an n-doped single crystalline silicon-carbon alloy functions as embedded source/drain regions of an n-type field effect transistor (NFET), which applies a tensile stress to the channel of the transistor.

Abstract: An integrated circuit structure includes a fin field-effect transistor (FinFET) including a semiconductor fin over and adjacent to insulation regions; and a source/drain region over the insulation regions. The source/drain region includes a first and a second semiconductor region. The first semiconductor region includes silicon and an element selected from the group consisting of germanium and carbon, wherein the element has a first atomic percentage in the first semiconductor region. The first semiconductor region has an up-slant facet and a down-slant facet. The second semiconductor region includes silicon and the element. The element has a second atomic percentage lower than the first atomic percentage. The second semiconductor region has a first portion on the up-slant facet and has a first thickness. A second portion of the second semiconductor region, if any, on the down-slant facet has a second thickness smaller than the first thickness.

Abstract: A wiring board with an electronic device comprising a plurality of trenches arranged in parallel on a substrate, a common trench communicating the plurality of trenches with each other at one of their ends on the substrate, a metal layer formed at the bottom of the plurality of trenches, and an electrode layer connected with the metal layer and formed on a bottom of the common trench, wherein the electrode layer on the bottom of the common trench constitutes a source electrode or a drain electrode of a field effect transistor, whereby the wiring board and an electronic circuit having a good fine wire pattern and a good narrow gap between the patterns using a coating material can be formed, and a reduction for a cost of an organic thin film electronic device and the electronic circuit can be attained since they can be realized through a development of a printing technique.

Abstract: A connecting structure for an electronic device includes an edge region of the device, a first trench and a second trench running toward the edge region, a first electrode within the first trench, and a second electrode within the second trench, the first and second electrodes being arranged in a same electrode plane with regard to a main surface of a substrate of the electronic device within the trenches, and the first electrode extending, at an edge region side end of the first trench, farther toward the edge region than the second electrode extends, at an edge region side end of the second trench, toward the edge region.

Abstract: A semiconductor device has: a silicon (semiconductor) substrate; a gate insulating film and a gate electrode, which are formed on the silicon substrate in this order; and source/drain material layers formed in recesses (holes) in the silicon substrate, the recesses being located beside the gate electrode. Here, each of side surfaces of the recesses, which are closer to the gate electrode, is constituted of at least one crystal plane of the silicon substrate.

Abstract: A method of manufacturing a bottom gate thin film transistor (“TFT”) in which a polycrystalline channel region having a large grain size is formed relatively simply and easily. The method of manufacturing a bottom gate thin film transistor includes forming a bottom gate electrode on a substrate, forming a gate insulating layer on the substrate to cover the bottom gate electrode, forming an amorphous semiconductor layer, an N-type semiconductor layer and an electrode layer on the gate insulating layer sequentially, etching an electrode region and an N-type semiconductor layer region formed on the bottom gate electrode sequentially to expose an amorphous semiconductor layer region, melting the amorphous semiconductor layer region using a laser annealing method, and crystallizing the melted amorphous semiconductor layer region to form a laterally grown polycrystalline channel region.

Abstract: A phase change memory device is provided in which the area of contact between phase change material and heater electrode is reduced to suppress current required for heating and a phase change region is formed directly on a contact to raise the degree of integration. The device comprises a heater electrode in which the lower part thereof is surrounded by a side wall of a first insulating material and the upper part thereof protruding from the side wall has a sharp configuration covered by a second insulating material except for a part of the tip end thereof, and the exposed tip end is coupled to the phase change material layer.

Abstract: A semiconductor device is disclosed having a conductive gate structure overlying a semiconductor layer having a major surface. An isolation material is recessed within a trench region below the major surface of the semiconductor layer. An epitaxial layer is formed overlying a portion of the major surface and on an active region forming a sidewall of the trench.

Abstract: Disclosed is a semiconductor component arrangement and a method for producing a semiconductor component arrangement. The method comprises producing a trench transistor structure with at least one trench disposed in the semiconductor body and with at least a gate electrode disposed in the at least one trench. An electrode structure is disposed in at least one further trench and comprises an at least one electrode. The at least one trench of the transistor structure and the at least one further trench are produced by common process steps. Furthermore, the at least one electrode of the electrode structure and the gate electrode are produced by common process steps.

Abstract: The trench MOS transistor according to the present invention includes a drain region in a form of a trench filled with a semiconductor material. The trench has a bottom surface and side surfaces and extends vertically downward from the top surface of the covering layer into the buried layer, the bottom surface of the trench lies in the buried layer, an insulating layer lines the side surfaces of the trenches, and the semiconductor material within the trench overlies the insulating layer and contacts the buried layer at the bottom surface of the trench.

Abstract: In one embodiment a transistor is formed with a gate structure having an opening in the gate structure. An insulator is formed on at least sidewalls of the opening and a conductor is formed on the insulator.

Abstract: A method for fabricating a field-effect transistor with local source/drain insulation. The method includes forming and patterning a gate stack with a gate layer and a gate dielectric on a semiconductor substrate; forming source and drain depressions at the gate stack in the semiconductor substrate; forming a depression insulation layer at least in a bottom region of the source and drain depressions; and filling the at least partially insulated source and drain depressions with a filling layer for realizing source and drain regions. Further, the step of forming source and drain depressions at the gate stack in the semiconductor substrate includes that first depressions are formed for realizing channel connection regions in the semiconductor substrate, spacers are formed at the gate stack, and second depressions are formed using the spacers as a mask in the first depressions and in the semiconductor substrate.

Abstract: A DC-DC boost converter in multi-die package is proposed having an output Schottky diode and a low-side vertical MOSFET controlled by a power regulating controller (PRC). The multi-die package includes a single die pad with the Schottky diode placed there on side by side with the vertical MOSFET. The PRC die is attached atop the single die pad via an insulating die bond. Alternatively, the single die pad is grounded. The vertical MOSFET is a top drain vertical N-channel FET, the substrate of Schottky diode die is its anode. The Schottky diode and the vertical MOSFET are stacked atop the single die pad. The PRC is attached atop the single die pad via a standard conductive die bond. The Schottky diode die can be supplied in a flip-chip configuration with cathode being its substrate. Alternatively, the Schottky diode is supplied with anode being its substrate without the flip-chip configuration.

Abstract: A semiconductor device includes a transistor having a recessed gate, contact plugs formed in a region of a plurality of trenches, which are formed by recessing a semiconductor substrate. Further, a metal line and a source/drain region can be connected through the contact plug, so that on-current can be increased as much as an increased channel area.

Abstract: In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes an offset body region.

Abstract: A method of forming a vertical MOSFET device includes forming a first trench within a semiconductor layer of a first polarity, the first trench generally defining a well region of a second polarity opposite the first polarity; growing a first epitaxial well layer of the second polarity over the original semiconductor layer; growing a second epitaxial source contact layer of the first polarity over the well layer; forming a second trench through the source contact layer and at least a portion of the well layer; growing a third epitaxial layer of the second polarity over the source contact layer; and planarizing at least the first and second epitaxial layers so as to expose an upper surface of the original semiconductor layer, wherein a top surface of the third epitaxial layer is substantially coplanar with a top surface of the source contact layer prior to ohmic contact formation.

Abstract: In one embodiment a transistor is formed with a gate structure having an opening in the gate structure. An insulator is formed on at least sidewalls of the opening and a conductor is formed on the insulator.

Abstract: In a first aspect, a first apparatus is provided. The first apparatus is a semiconductor device on a substrate that includes (1) a first metal-oxide-semiconductor field-effect transistor (MOSFET); (2) a second MOSFET coupled to the first MOSFET, wherein portions of the first and second MOSFETs form first and second bipolar junction transistors (BJTs) which are coupled into a loop; and (3) a conductive region that electrically couples a source diffusion region of the first or second MOSFET with a doped well region below the source diffusion region. The conductive region is adapted to prevent an induced current from forming in the loop. Numerous other aspects are provided.

Abstract: A diffusion layer for semiconductor devices is provided. In accordance with embodiments of the present invention, a semiconductor device, such as a transistor, comprises doped regions surrounded by a diffusion barrier. The diffusion barrier may be formed by recessing regions of the substrate and implanting fluorine or carbon ions. A silicon layer may be epitaxially grown over the diffusion barrier in the recessed regions. Thereafter, the recessed regions may be filled and doped with a semiconductor or semiconductor alloy material. In an embodiment, a semiconductor alloy material, such as silicon carbon, is selected to induce a tensile stress in the channel region for an NMOS device, and a semiconductor alloy material, such as silicon germanium, is selected to induce a compressive stress in the channel region for a PMOS device.

Abstract: A vertical trench transistor has a first electrode, a second electrode and also a semiconductor body arranged between the first and second electrodes, there being formed in the semiconductor body a plurality of transistor cells comprising source region, body region, drift region and gate electrode and also contact holes for making contact with the source and body regions, contact being made with the source and body regions by means of the first electrode, and at least the bottom of each contact hole adjoining at least one drift region, so that Schottky contacts between the first electrode and corresponding drift regions are formed at the bottoms of the contact holes. The dimensions and configurations of the body regions or of the body contact regions optionally arranged between body regions and contact holes are chosen in such a way as to avoid excessive increases in electric fields at the edges of the contact hole bottoms.

Abstract: A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.

Abstract: An accumulation mode FET (ACCUFET) which includes an insulated gate, an adjacently disposed insulated source field electrode, and a source contact that makes Schottky contact with the base region of the ACCUFET.

Abstract: A semiconductor device that reduces the interval between gate electrodes. The semiconductor device includes a semiconductor substrate, a plurality of gate electrodes buried in the semiconductor substrate, a plurality of first insulation layers arranged respectively on the plurality of gate electrodes, a conductive layer formed on the surface of the semiconductor substrate near the plurality of gate electrodes and the plurality of first insulation layers, and a conductor layer arranged on at least the conductive layer.

Abstract: A semiconductor device which includes a laterally extending stack of laterally adjacent conductive semiconductor regions formed over a support surface of a substrate, and a method for fabricating the device.

Abstract: An MOS device is formed including a semiconductor layer of a first conductivity type, a first source/drain region of a second conductivity type formed in the semiconductor layer, and a second source/drain region of the second conductivity type formed in the semiconductor layer and spaced apart from the first source/drain region. A gate is formed proximate an upper surface of the semiconductor layer and at least partially between the first and second source/drain regions. The MOS device further includes at least one contact, the at least one contact including a silicide layer formed on and in electrical connection with at least a portion of the first source/drain region, the silicide layer extending laterally away from the gate. The contact further includes at least one insulating layer formed directly on the silicide layer.