Abstract: A bidirectional power transistor formed horizontally in a semiconductor layer disposed on a heavily-doped semiconductor wafer with an interposed insulating layer, the wafer being capable of being biased to a reference voltage, the product of the average dopant concentration and of the thickness of the semiconductor layer ranging between 5·1011 cm?2 and 5·1012 cm?2.

Abstract: Vertical heterojunction bipolar transistors with reduced base-collector junction capacitance, as well as fabrication methods for vertical heterojunction bipolar transistors and design structures for BiCMOS integrated circuits. The vertical heterojunction bipolar transistor includes a barrier layer between the intrinsic base and the extrinsic base that blocks or reduces diffusion of a dopant from the extrinsic base to the intrinsic base. The barrier layer has at least one opening that permits direct contact between the intrinsic base and a portion of the extrinsic base disposed in the opening.

Abstract: A vertical organic transistor and a method for fabricating the same are provided, wherein an emitter, a grid with openings and a collector are sequentially arranged above a substrate. Two organic semiconductor layers are interposed respectively between the emitter and the grid with openings and between the grid with openings and the collector. The channel length is simply decided by the thickness of the organic semiconductor layers. The collector current depends on the space-charge-limited current contributed by the potential difference between the emitter and the openings of the grid. And the grid voltage can thus effectively control the collector current. Further, the fabrication process of the vertical organic transistor of the present invention is simple and exempt from using the photolithographic process.

Abstract: A method for producing an electrical contact of an optoelectronic semiconductor chip (1), comprising providing a mirror layer (2), comprised of a metal or metal alloy, over the semiconductor chip; providing a protective layer (3) over said mirror layer; providing a layer sequence of a barrier layer and a coupling layer (5) over said protective layer; and providing a solder layer (8) over said layer sequence.

Abstract: A vertical organic transistor and a method for fabricating the same are provided, wherein an emitter, a grid with openings and a collector are sequentially arranged above a substrate. Two organic semiconductor layers are interposed respectively between the emitter and the grid with openings and between the grid with openings and the collector. The channel length is simply decided by the thickness of the organic semiconductor layers. The collector current depends on the space-charge-limited current contributed by the potential difference between the emitter and the openings of the grid. And the grid voltage can thus effectively control the collector current. Further, the fabrication process of the vertical organic transistor of the present invention is simple and exempt from using the photolithographic process.

Abstract: A method for producing a semiconductor component is proposed. The method includes providing a semiconductor body having a first surface; forming a mask on the first surface, wherein the mask has openings for defining respective positions of trenches; producing the trenches in the semiconductor body using the mask, wherein mesa structures remain between adjacent trenches; introducing a first dopant of a first conduction type using the mask into the bottoms of the trenches; carrying out a first thermal step; introducing a second dopant of a second conduction type, which is complementary to the first conduction type, at least into the bottoms of the trenches; and carrying out a second thermal step.

Abstract: A bipolar transistor (100) is manufactured using the following processes: (a) forming a base electrode layer (129) as a portion of a base electrode over a semiconductor substrate (110); (b) forming a first portion of an emitter electrode (154) over the base electrode layer; (c) forming a mask layer (280) over a first portion of the base electrode layer, a portion of the first portion of the emitter electrode and a portion of the semiconductor substrate; and (d) implanting a dopant into a second portion of the base electrode layer after forming the emitter electrode after forming the mask layer.

Abstract: A Low Noise semiconductor amplifier structure formed from layers of differently doped semiconductor material. This structure when properly biased will amplify voltage signals applied to the input terminal (Base1 or signal-base), and provide the same signal, amplified at the terminal designated as the output or collector. The semiconductor material can be any of a number of semiconductor materials, Germanium, Silicon, Gallium-Arsenide or any material with suitable semi-conducting properties. The structure can be any BJT (Bipolar Junction Transistor) form. The presence of an additional, distinct highly doped layer indicated as Base2 in the BJT form, provides an electrical noise suppression function. This inhibits intrinsic electrical noise, and improves the high frequency performance of the device in conjunction with an external capacitor connected to this new Base2 (or anti-base) region.

Abstract: In the inventive method of producing a base terminal structure for a bipolar transistor, an etch stop layer is applied on a single-crystal semiconductor substrate, a poly-crystal base terminal layer is produced on the etch stop layer and an emitter window is etched in the base terminal layer using the etch stop layer as an etch stop.