Abstract: A semiconductor device having a transistor channel with an enhanced stress is provided. To achieve the enhanced stress transistor channel, a nitride film is preferentially formed on the device substrate with little to no nitride on a portion of the gate stack. The nitride film may be preferentially deposited only on the silicon substrate in a non-conformal layer, where little to no nitride is deposited on the upper portions of the gate stack. The nitride film may also be uniformly deposited on the silicon substrate and gate stack in a conformal layer, with the nitride film proximate the upper regions of the gate stack preferentially removed in a later step. In some embodiments, nitride near the top of the gate stack is removed by removing the upper portion of the gate stack. In any of the methods, stress in the transistor channel is enhanced by minimizing nitride deposited on the gate stack, while having nitride deposited on the substrate.

Abstract: A trench gate FET is formed as follows. A well region is formed in a silicon region. A plurality of active gate trenches and a termination trench are simultaneously formed in an active region and a termination region of the FET, respectively, such that the well region is divided into a plurality of active body regions and a termination body region. Using a mask, openings are formed over the termination body region and the active body region. Dopants are implanted into the active body regions and the termination body region through the openings thereby forming a first region in each active and termination body region. Exposed surfaces of all first regions are recessed so as to form a bowl-shaped recess having slanted walls and a bottom protruding through the first region such that remaining portions of the first region in each active body region form source regions that are self-aligned to the active gate trenches.

Abstract: The invention included to methods of forming CoSi2, methods of forming field effect transistors, and methods of forming conductive contacts. In one implementation, a method of forming CoSi2 includes forming a substantially amorphous layer comprising MSix over a silicon-containing substrate, where “M” comprises at least some metal other than cobalt. A layer comprising cobalt is deposited over the substantially amorphous MSix-comprising layer. The substrate is annealed effective to diffuse cobalt of the cobalt-comprising layer through the substantially amorphous MSix-comprising layer and combine with silicon of the silicon-containing substrate to form CoSi2 beneath the substantially amorphous MSix-comprising layer. Other aspects and implementations are contemplated.

Abstract: A transistor device includes a recess in a surface of semiconductor substrate, a gate insulation layer formed over an inner side of the recess, a gate conductor filling the recess in which the gate insulation layer is formed, and source and drain regions located over the substrate adjacent the recess. Among the advantages: the gate structure lowers overall gate resistance and reduces the short channel effect.

Abstract: The invention includes methods of forming conductive metal silicides by reaction of metal with silicon. In one implementation, such a method includes providing a semiconductor substrate comprising an exposed elemental silicon containing surface. At least one of a crystalline form TiN, WN, elemental form W, or SiC comprising layer is deposited onto the exposed elemental silicon containing surface to a thickness no greater than 50 Angstroms. Such layer is exposed to plasma and a conductive reaction layer including at least one of an elemental metal or metal rich silicide is deposited onto the plasma exposed layer.

Abstract: A method for manufacturing a semiconductor device having a P-type MOSFET and an N-type MOSFET, the method comprising the steps of: forming a gate insulating film, a non-doped polysilicon film, a metal silicide film, a metal nitride film and a metal film on a semiconductor substrate; processing at least the metal film, the metal nitride film and the metal silicide film to pattern them into the shape of a gate such that the portion of the meal silicide film that forms part of a gate electrode of a P-type MOSFET and the portion of the meal silicide film that forms part of a gate electrode of an N-type MOSFET are separated from each other; introducing P-type and N-type impurities into the respective regions of the non-doped polysilicon film where the P-type and N-type MOSFETs are formed; performing thermal treatment to diffuse the impurities; and patterning the polysilicon film with the impurities introduced into the shape of the gate.

Abstract: Integrated circuit devices are provided including an integrated circuit substrate and a gate on the integrated circuit substrate. The gate has sidewalls. A barrier layer spacer is provided on the sidewalls of the gate. A portion of the barrier layer spacer protrudes from the sidewalls of the gate exposing a lower surface of the barrier layer spacer that faces the integrated circuit substrate. A silicide layer is provided on the portion of the barrier layer spacer protruding from the sidewalls of the gate.

Abstract: A salicide layer is deposited on the source/drain regions of a PMOS transistor. A dielectric capping layer having residual compressive stress is formed on the salicide layer by depositing a plurality of PECVD dielectric sublayers and plasma-treating each sublayer. Compressive stress from the dielectric capping layer is uniaxially transferred to the PMOS channel through the source-drain regions to create compressive strain in the PMOS channel. To form a compressive dielectric layer, a deposition reactant mixture containing A1 atoms and A2 atoms is provided in a vacuum chamber. Element A2 is more electronegative than element A1, and A1 atoms have a positive oxidation state and A2 atoms have a negative oxidation state when A1 atoms are bonded with A2 atoms. A deposition plasma is generated by applying HF and LF radio-frequency power to the deposition reactant mixture, and a sublayer of compressive dielectric material is deposited.

Abstract: A semiconductor device and method of manufacturing the same. The semiconductor device includes a semiconductor substrate having a first conductive layer, a second conductive layer on the first conductive layer, a first high density impurity area on the second conductive layer, and a second high density impurity area on the first impurity area; a trench exposing the first conductive layer; a gate insulating layer on an inner wall of the trench; a polysilicon layer on the gate insulating layer; and a metal layer on the polysilicon layer in the trench, in which the metal layer fills the trench.

Abstract: A high resistor SRAM memory cell to reduce soft error rate includes a first inverter having an output as a first memory node, and a second inverter having an output as a second memory node. The second memory node is coupled to an input of the first inverter through a first resistor. The first memory node is coupled to an input of the second inverter through a second resistor. A pair of access transistors are respectively coupled to a pair of bit lines, a split word line and one of the memory nodes. The resistors are prepared by coating a layer of silicide material on a selective portion of the gate structure of the transistors included in the first inverter, and connecting a portion of the gate structure that is substantially void of the silicide material to the drain of the transistors included in the second inverter.

Abstract: A method for use in the fabrication of a gate electrode includes providing a gate oxide layer and forming a titanium boride layer on the oxide layer. An insulator cap layer is formed on the titanium boride layer and thereafter, the gate electrode is formed from the titanium boride layer. A barrier layer may be formed on the oxide layer prior to forming the titanium boride layer with the gate electrode being formed from the barrier layer and the titanium boride layer. Further, a polysilicon layer may be formed on the gate oxide layer prior to forming the titanium boride layer with the gate electrode being formed from the titanium boride layer and the polysilicon layer. Yet further, a polysilicon layer may be formed on the gate oxide layer and a barrier layer formed on the polysilicon layer prior to forming the titanium boride layer. The gate electrode is then formed from the polysilicon layer, the barrier layer, and the titanium boride layer.

Abstract: A semiconductor device includes a gate electrode, and a source region and a drain region proximate the gate electrode. A silicide region is disposed over a top surface of the gate electrode, the source region, or the drain region. A non-silicide region is disposed proximate the silicide region over an edge region of the top surface of the gate electrode, the source region, or the drain region.

Abstract: In a semiconductor device using a polysilicon contact, such as a poly plug between a transistor and a capacitor in a container cell, an interface is provided where the poly plug would otherwise contact the bottom plate of the capacitor. The interface bars silicon from the plug from diffusing into the capacitor's dielectric. The interface can also include an oxygen barrier to prevent the poly plug from oxidizing during processing. Below the interface is a silicide layer to help enhance electrical contact with the poly plug. In a preferred method, the interface is created by selectively depositing a layer of titanium over a recessed poly plug to the exclusion of the surrounding oxide. The deposition process allows for silicidation of the titanium. The top half of the titanium silicide is then nitridized. A conformal ruthenium or ruthenium oxide layer is subsequently deposited, covering the titanium nitride and lining the sides and bottom of the container cell.

Abstract: Methods and apparatus are provided for semiconductor devices. The apparatus comprises a substrate having therein a source region and a drain region separated by a channel region extending to a first surface of the substrate, and a multilayered gate structure located above the channel region. The gate structure comprises, a gate dielectric, preferably of an oxide of Hf, Zr or HfZr substantially in contact with the channel region, a first conductor layer of, for example an oxide of MoSi overlying the gate dielectric, a second conductor layer of, e.g., poly-Si, overlying the first conductor layer and adapted to apply an electrical field to the channel region, and an impurity migration inhibiting layer (e.g., MoSi) located above or below the first conductor layer and adapted to inhibit migration of a mobile impurity, such as oxygen for example, toward the substrate.

Abstract: A silicide method for integrated circuit and semiconductor device fabrication wherein a layer of nickel is formed over at least one silicon region of a substrate and a layer of cobalt is formed over the nickel layer. The cobalt/nickel bi-layer is then annealed to transform the bi-layer to a bi-silicide film having a cobalt-rich silicide portion and a nickel-rich silicide portion.

Abstract: A semiconductor device includes: a gate electrode formed on a silicon substrate; source/drain regions formed at both sides of the gate electrode in the silicon substrate; and a silicide layer formed on the source/drain regions. The silicide layer includes a first silicide layer mainly made of a metal silicide having a formation enthalpy lower than that of NiSi and a second silicide layer formed on the first silicide and made of Ni silicide.

Abstract: A manufacturing method of a semiconductor device capable of efficiently inspecting whether a metal silicide layer is sufficiently formed is provided. The manufacturing method is provided with the steps of forming a metal layer over a semiconductor layer containing silicon; forming a metal silicide layer over a surface of the semiconductor layer by heating the semiconductor layer and the metal layer; generating image data by performing color imaging of the metal silicide layer from above the metal silicide layer; calculating saturation of the metal silicide layer by processing the image data; and judging the formation amount of the metal silicide layer on the basis of the calculated saturation.

Abstract: A transistor device includes a recess in a surface of semiconductor substrate, a gate insulation layer formed over an inner side of the recess, a gate conductor filling the recess in which the gate insulation layer is formed, and source and drain regions located over the substrate adjacent the recess. Among the advantages: the gate structure lowers overall gate resistance and reduces the short channel effect.

Abstract: A semiconductor device according to the present invention comprises a silicon substrate, a gate electrode formed on a main surface of the silicon substrate with a gate insulation film therethrough, a sidewall spacer formed so as to cover a side surface of the gate electrode and including at least two layers of a silicon oxide film as a lowermost layer and a silicon nitride film formed thereon, a source region and a drain region formed in the main surface of the silicon substrate so as to sandwich the gate electrode, a protection film formed so as to cover an end surface of the silicon oxide film without extending below said silicon nitride film, the end surface being on a side of said source region and said drain region, and a metal silicide layer formed in the source region and the drain region on a side of said protection film away from said gate electrode.

Abstract: A method for improving a microelectronic device interface with an ultra-fast anneal process at an intermediate temperature that may be lower than those used in a dopant activation process. In one embodiment, a partial recrystalization of an amorphous silicon layer in the source drain region that is the precursor to the metal salicide reaction is disclosed. Source/drain regions are first amorphized using an implant process, then a metal layer is deposited in the source/drain region which reacts with the silicon in a salicide formation anneal. Amorphization reduces problems with metal diffusion that can occur during salicide formation anneal process, which typically occurs at a temperature significantly lower than the dopant activation temperature.

Abstract: A metal-oxide-semiconductor (MOS) transistor device is provided. The MOS transistor device includes a substrate, a gate structure, a spacer, a source/drain region and a barrier layer. The gate structure is disposed on the substrate. The gate structure includes a gate and a gate dielectric layer disposed between the gate and the substrate. The spacer is disposed on the sidewall of the gate structure. The source/drain region is disposed in the substrate on two sides of the spacer. The barrier layer is disposed around the source/drain region. The source/drain region and the barrier layer are fabricated using an identical material. However, the doping concentration of the source/drain region is larger than the doping concentration of the barrier layer.

Abstract: A method of manufacturing a metal-oxide-semiconductor transistor device is disclosed. In the method, a silicon nitride spacer is formed and will be removed after an ion implantation process to form a source/drain region and a salicide process to form a metal silicide layer on the surface of the source/drain region and the gate electrode. The metal silicide layer is formed to comprise silicon (Si), nickel (Ni) and at least one metal selected from a group consisting of iridium (Ir), iron (Fe), cobalt (Co), platinum (Pt), palladium (Pd), molybdenum (Mo), and tantalum (Ta); therefore, when the silicon nitride spacer is removed by etching, the metal silicide layer is not damaged.

Abstract: A semiconductor device includes a substrate having first and second device regions separated from each other by a device isolation region, a first field effect transistor having a first polysilicon gate electrode and formed in the first device region, a second field effect transistor having a second polysilicon gate electrode and formed in the second device region, a polysilicon pattern extending over the device isolation region from the first polysilicon gate electrode to the second polysilicon gate electrode, and a silicide layer formed on a surface of the first polysilicon gate electrode, a surface of said the polysilicon gate electrode and a surface of the polysilicon pattern so as to extend on the polysilicon pattern from the first polysilicon gate electrode to the second polysilicon gate electrode, the silicide layer having a region of increased film thickness on the polysilicon pattern, wherein the silicide layer has a surface protruding upward in the region of increased film thickness.

Abstract: A method for forming a semiconductor device structure, comprising the steps of independently forming source/drain surface metal silicide layers and a fully silicided metal gate in a polysilicon gate stack. Specifically, one or more sets of spacer structures are provided along sidewalls of the polysilicon gate stack after formation of the source/drain surface metal silicide layers and before formation of the silicided metal gate, in order to prevent formation of additional metal silicide structures in the source/drain regions during the gate salicidation process. The resulting semiconductor device structure includes a fully silicide metal gate that either comprises a different metal silicide material from that in the source/drain surface metal silicide layers, or has a thickness that is larger than that of the source/drain surface metal silicide layers. The source/drain regions of the semiconductor device structure are devoid of other metal silicide structures besides the surface metal silicide layers.

Abstract: A method of forming a semiconductor device comprising providing a substrate comprising a first device region, implanting a source/drain region in the first device region, forming a strained capping layer on the source/drain region, super annealing and crystallizing the source/drain region, and removing substantially all of the strained capping layer is provided. The method further includes pre-amorphizing the source/drain region before the super annealing. The strained capping layer may further be formed on a pre-amorphized gate electrode, and the gate electrode is super annealed. The strain is generated and preserved after the removal of the strained capping layer.

Abstract: A method of forming MOS devices is provided. The method includes providing a semiconductor substrate, forming a gate dielectric over the semiconductor substrate, forming a gate electrode over the gate dielectric, forming a source/drain region in the semiconductor substrate, forming an additional layer, preferably by epitaxial growth, on the source/drain region, and siliciding at least a top portion of the additional layer. The additional layer compensates for at least a portion of the semiconductor material lost during manufacturing processes and increases the distance between the source/drain silicide and the substrate. As a result, the leakage current is reduced. A transistor formed using the preferred embodiment preferably includes a silicide over the gate electrode wherein the silicide extends beyond a sidewall boundary of the gate electrode.

Abstract: A metal oxide semiconductor field effect transistor (MOSFET) structure that includes multiple and distinct self-aligned silicide contacts and methods of fabricating the same are provided. The MOSFET structure includes at least one metal oxide semiconductor field effect transistor having a gate conductor including a gate edge located on a surface of a Si-containing substrate; a first inner silicide having an edge that is substantially aligned to the gate edge of the at least one metal oxide semiconductor field effect transistor; and a second outer silicide located adjacent to the first inner silicide. In accordance with the present invention, the second outer silicide has second thickness is greater than the first thickness of the first inner silicide. Moreover, the second outer silicide has a resistivity that is lower than the resistivity of the first inner silicide.

Abstract: An integrated circuit is provided with a semiconductor substrate that is doped with a set concentration of an oxidizable dopant of a type that segregates to the top surface of a suicide when the semiconductor substrate is reacted to form such a silicide. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. Source/drain junctions are in the semiconductor substrate. A silicide is on the source/drain junctions and dopant is segregated to the top surface of the silicide. The dopant on the top surface of the segregated dopant is oxidized to form an insulating layer of oxidized dopant above the silicide. An interlayer dielectric is above the semiconductor substrate. Contacts and connection points are in the interlayer dielectric to the insulating layer of oxidized dopant above the silicide.

Abstract: An integrated circuit arrangement and fabrication method is presented. The integrated circuit arrangement contains a semiconductor and a metal electrode. The contact area between a semiconductor and the electrode is increased without increasing the lateral dimensions using partial regions of the semiconductor and/or of the electrode that extend through a transition layer between the semiconductor and electrode.