With At Least One Ferroelectric Layer (epo) Patents (Class 257/E29.164)
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Patent number: 7545013Abstract: A nonvolatilely reconfigurable logical circuit is built. It is a reconfigurable logical circuit based on the CMOS configuration using the spin MOSFET. By changing the transmission characteristic of each transistor in accordance with the magnetization states of Tr1, Tr2, Tr5, and Tr8 which are spin MOSFETs, it is possible to reconfigure all the two-input symmetric functions AND/OR/XOR/NAND/NOR/XNOR/“1”/“0”. Since it is possible to constitute the logical function by a small number of non-volatile elements, it is possible to reduce the chip area, thereby increasing the speed and reducing the power consumption.Type: GrantFiled: March 26, 2004Date of Patent: June 9, 2009Assignee: Japan Science and Technology AgencyInventors: Satoshi Sugahara, Tomohiro Matsuno, Masaaki Tanaka
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Publication number: 20090134440Abstract: A semiconductor device comprising a substrate and a ferroelectric capacitor formed on the substrate. The ferroelectric capacitor includes a lower electrode, an upper electrode and a ferroelectric film interposed between the lower and upper electrodes. The ferroelectric capacitor having sidewalls receded from sidewalls of the upper electrode.Type: ApplicationFiled: January 29, 2009Publication date: May 28, 2009Inventor: Hiroyuki KANAYA
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Publication number: 20090127602Abstract: This disclosure concerns a memory including transistors provided on a substrate; ferroelectric capacitors provided on the transistors, the ferroelectric capacitors respectively including a ferroelectric film provided between a lower electrode and an upper electrode; and a barrier film covering a first side surface of the ferroelectric capacitor, and blocking passing of hydrogen, wherein adjacent two of the ferroelectric capacitors connected in the lower electrode form one capacitor unit, a plurality of the capacitor units connected in the upper electrode form one capacitor chain, the capacitor units are arranged with a deviation of a half pitch of the capacitor unit in adjacent plurality of capacitor chains, and when D1 is a distance between the adjacent ferroelectric capacitors within the capacitor unit, D2 is a distance between the adjacent capacitor chains, and D3 is a distance between the adjacent capacitor units within the capacitor chain, D3 is larger than D1 and D2.Type: ApplicationFiled: October 16, 2008Publication date: May 21, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Tohru Ozaki
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Patent number: 7535745Abstract: A ferroelectric memory device, which includes a vertical ferroelectric capacitor having an electrode distance smaller than a minimum feature size of lithography technology being used and suitable for the miniaturization, and a method of manufacturing the same are disclosed. According to one aspect of the present invention, it is provided a ferroelectric memory device comprising an MIS transistor formed on a substrate, and a ferroelectric capacitor formed on an interlevel insulator above the MIS transistor, wherein a pair of electrodes of the ferroelectric capacitor are disposed in a channel length direction of the MIS transistor to face each other putting a ferroelectric film in-between, and wherein a distance between the electrodes of the ferroelectric capacitor is smaller than a gate length of the MIS transistor.Type: GrantFiled: June 19, 2006Date of Patent: May 19, 2009Assignee: Kabushiki Kaisha ToshibaInventor: Susumu Shuto
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Publication number: 20090059659Abstract: A spin transistor includes a first ferromagnetic layer provided on a substrate and having an invariable magnetization direction, a second ferromagnetic layer provided on the substrate apart from the first ferromagnetic layer in a first direction, and having a variable magnetization direction, a plurality of projecting semiconductor layers provided on the substrate to extend in the first direction, and sandwiched between the first ferromagnetic layer and the second ferromagnetic layer, a plurality of channel regions respectively provided in the projecting semiconductor layers, and a gate electrode provided on the channel regions.Type: ApplicationFiled: August 28, 2008Publication date: March 5, 2009Inventors: Tomoaki INOKUCHI, Mizue Ishikawa, Hideyuki Sugiyama, Yoshiaki Saito
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Patent number: 7479696Abstract: A tunable microwave device includes a SOI structure. A buffer layer is formed on the SOI structure. A microwave film layer is formed on the buffer layer. The microwave film layer comprises BST related materials.Type: GrantFiled: August 26, 2005Date of Patent: January 20, 2009Assignee: Massachusetts Institute of TechnologyInventors: Il-Doo Kim, Ytshak Avrahami, Harry L. Tuller
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Publication number: 20080290384Abstract: An improved microelectronic device, and method for making such a microelectronic device. The device includes one or plural transistors and piezoelectric mechanisms, with an arrangement capable of applying a variable mechanical strain on transistor channels.Type: ApplicationFiled: July 21, 2006Publication date: November 27, 2008Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUEInventors: Jerome Lolivier, Maud Vinet, Thierry Poiroux
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Patent number: 7436013Abstract: A ferroelectric memory device has a high performance, includes no Pb, and can be directly mounted onto an Si substrate. The ferroelectric memory device includes a (001)-oriented BiFeO3 ferroelectric layer 5 with a tetragonal structure, which is formed on an electrode 4 made of a perovskite material formed on an Si oxide film. The electrode 4 with a perovskite structure is formed by an ion beam assist method.Type: GrantFiled: January 10, 2007Date of Patent: October 14, 2008Assignee: Seiko Epson CorporationInventors: Hiromu Miyazawa, Takamitsu Higuchi, Setsuya Iwashita
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Patent number: 7382013Abstract: To provide a dielectric thin with a high dielectric constant, a low leakage current, and stable physical properties and electrical properties and to provide a thin film capacitor or other thin film dielectric device with a high capacitance and high reliability and a method of production of the same, a dielectric thin film containing oxides such as barium strontium titanate expressed by the formula (BaxSr(1-x))aTiO3 (0.5<x?1.0, 0.96<a?1.00) and having a thickness of not more than 500 nm and a method of production of a thin film dielectric device including a step of annealing the dielectric thin film in an atmosphere of an oxidizing gas after forming a dielectric thin film on a conductive electrode.Type: GrantFiled: September 28, 2005Date of Patent: June 3, 2008Assignee: TDK CorporationInventors: Kiyoshi Uchida, Kenji Horino, Hitoshi Saita
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Publication number: 20070287199Abstract: A method of forming a semiconductor structure includes providing a semiconductor substrate, performing a hydrogen annealing to the semiconductor substrate, forming a base oxide layer after the step of hydrogen annealing, and forming a high-k dielectric layer on the base oxide layer.Type: ApplicationFiled: June 9, 2006Publication date: December 13, 2007Inventors: Peng-Fu Hsu, Jin Ying, Hun-Jan Tao
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Patent number: 7285810Abstract: A ferroelectric memory device includes a microelectronic substrate and a plurality of ferroelectric capacitors on the substrate, arranged as a plurality of rows and columns in respective row and column directions. A plurality of parallel plate lines overlie the ferroelectric capacitors and extend along the row direction, wherein a plate line contacts ferroelectric capacitors in at least two adjacent rows. The plurality of plate lines may include a plurality of local plate lines, and the ferroelectric memory device may further include an insulating layer disposed on the local plate lines and a plurality of main plate lines disposed on the insulating layer and contacting the local plate lines through openings in the insulating layer. In some embodiments, ferroelectric capacitors in adjacent rows share a common upper electrode, and respective ones of the local plate lines are disposed on respective ones of the common upper electrodes.Type: GrantFiled: September 23, 2004Date of Patent: October 23, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Ho Kim, Dong-Jin Jung, Ki-Nam Kim, Sang-Don Nam, Kyu-Mann Lee
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Publication number: 20070238239Abstract: A method is provided for forming a rare earth element-doped silicon oxide (SiO2) precursor with nanocrystalline (nc) Si particles. In one aspect the method comprises: mixing Si particles into a first organic solvent, forming a first solution with a first boiling point; filtering the first solution to remove large Si particles; mixing a second organic solvent having a second boiling point, higher than the first boiling point, to the filtered first solution; and, fractionally distilling, forming a second solution of nc Si particles. The Si particles are formed by immersing a Si wafer into a third solution including hydrofluoric (HF) acid and alcohol, applying an electric bias, and forming a porous Si layer overlying the Si wafer. Then, the Si particles are mixed into the organic solvent by depositing the Si wafer into the first organic solvent, and ultrasonically removing the porous Si layer from the Si wafer.Type: ApplicationFiled: September 12, 2005Publication date: October 11, 2007Inventors: Wei-Wei Zhuang, Yoshi Ono, Sheng Teng-Hsu, Tingkai Li
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Patent number: 7276758Abstract: Disclosed is a non-volatile memory having three data states and a method for manufacturing the same. The non-volatile memory includes a silicon substrate having a device separation film; a floating gate formed on the silicon substrate; a tunnel oxide film interposed between the silicon substrate and the floating gate below both ends of the floating gate; a ferroelectric substance interposed between the silicon substrate and the floating gate inside the tunnel oxide film; a diffusion barrier film enclosing the ferroelectric substance; a control gate formed on the substrate including the floating gate; a gate oxide film formed below the control gate; spacers formed on both lateral walls of the laminated floating gate and control gate including the tunnel oxide film and gate oxide film, respectively; and source/drain regions formed within the substrate surfaces on both sides of the control gate including the spacers, respectively.Type: GrantFiled: May 4, 2005Date of Patent: October 2, 2007Assignee: Hynix Semiconductor Inc.Inventor: Kyung Do Kim
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Patent number: 7220601Abstract: Provided is a method of manufacturing a nano-sized MTJ cell in which a contact in the MTJ cell is formed without forming a contact hole. The method of forming the MTJ cell includes forming an MTJ layer on a substrate, forming an MTJ cell region by patterning the MTJ layer, sequentially depositing an insulating layer and a mask layer on the MTJ layer, exposing an upper surface of the MTJ cell region by etching the mask layer and the insulating layer at the same etching rate, and depositing a metal layer on the insulating layer and the MTJ layer.Type: GrantFiled: January 13, 2005Date of Patent: May 22, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Soon-won Hwang, I-hun Song, Geun-young Yeom, Seok-jae Chung
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Patent number: 7214977Abstract: A ferroelectric thin film formed of a highly oriented polycrystal in which 180° domains and 90° domains arrange at a constant angle to an applied electric field direction in a thin film plane and reversely rotate in a predetermined electric field.Type: GrantFiled: October 4, 2005Date of Patent: May 8, 2007Assignee: Seiko Epson CorporationInventors: Takeshi Kijima, Yasuaki Hamada, Eiji Natori
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Patent number: 7211852Abstract: High quality epitaxial layers of GaN can be grown overlying large silicon wafers (200) by forming an amorphous layer (210) on the substrate. The amorphous layer dissipates strain and permits the growth of a high quality GaN layer (208). Any lattice mismatch between the GaN layer and the underlying substrate is taken care of by the amorphous layer.Type: GrantFiled: April 29, 2005Date of Patent: May 1, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Jamal Ramdani, Lyndee L. Hilt
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Patent number: 7211851Abstract: A ferroelectric memory comprises a first transistor connected between N1 and N2 nodes, a second transistor connected between the N2 node and an N3 node, a first transistor connected between P1 and P2 nodes, a second transistor connected between the P2 node and a P3 node, a first wiring formed in a first wiring layer to interconnect the N1 node and the P1 node, a second wiring formed in the first wiring layer to interconnect the N3 node and the P3 node, a third wiring formed in a second wiring layer different from the first wiring layer to interconnect the N2 node and the P2 node, a first capacitor whose first electrode is connected to the first wiring, and a second capacitor whose first electrode is connected to the second wiring. Second electrodes of the first and second capacitors are both connected to the N2 node or the P2 node.Type: GrantFiled: March 21, 2005Date of Patent: May 1, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Tadashi Miyakawa, Daisaburo Takashima
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Patent number: 7196367Abstract: An embodiment of the invention is a transistor formed in part by a ferromagnetic semiconductor with a sufficiently high ferromagnetic transition temperature to coherently amplify spin polarization of a current. For example, an injected non-polarized control current creates ferromagnetic conditions within the transistor base, enabling a small spin-polarized signal current to generate spontaneous magnetization of a larger output current.Type: GrantFiled: September 30, 2004Date of Patent: March 27, 2007Assignee: Intel CorporationInventors: Dmitri E. Nikonov, George I. Bourianoff
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Publication number: 20070031981Abstract: In a method for forming a ferroelectric film of insulating metal oxide on a surface of an electrode with a concave or a convex or in convex shape which is formed above a substrate, multiple types of source gases constituting a material gas and each containing an organometallic compound are introduced into a chamber and main components of the multiple types of source gases are allowed to chemically react with one another with the chemical reaction proceeding depending on the reaction rate. Then, the ferroelectric film is deposited on the surface of the electrode.Type: ApplicationFiled: October 5, 2006Publication date: February 8, 2007Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Toshitaka Tatsunari, Shinichiro Hayashi
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Patent number: 7148531Abstract: A ferromagnetic thin-film based digital memory having a substrate formed of a base supporting an electrically insulating material primary substrate layer in turn supporting a plurality of current control devices each having an interconnection arrangement with each of said plurality of current control devices being separated from one another by spacer material therebetween and being electrically interconnected with information storage and retrieval circuitry. A plurality of bit structures are each supported on and electrically connected to a said interconnection arrangement of a corresponding one of said plurality of current control devices and have magnetic material films in which a characteristic magnetic property is substantially maintained below an associated critical temperature above which such magnetic property is not maintained of which two are separated by at least one intermediate layer of a nonmagnetic material having two major surfaces on opposite sides thereof.Type: GrantFiled: April 28, 2005Date of Patent: December 12, 2006Assignee: NVE CorporationInventors: James M. Daughton, James G. Deak, Arthur V. Pohm
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Patent number: 7141842Abstract: A magnetic memory device includes a memory cell which has a first wiring line composed of a first wiring layer, a second wiring line composed of a second wiring layer and provided above or below the first wiring line so as to cross the first wiring line, and a magnetoresistive effect element device provided in a position where the first wiring line and the second wiring line cross each other. The device further includes a peripheral circuit which includes a third wiring line provided around the memory cell and composed of the first wiring layer, a fourth wiring line provided above or below the third wiring line and composed of the second wiring layer, and at least one magnetic layer forming the magnetoresistive effect element device and provided between the third wiring line and the fourth wiring line.Type: GrantFiled: December 17, 2003Date of Patent: November 28, 2006Assignee: Kabushiki Kaisha ToshibaInventor: Takeshi Kajiyama
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Patent number: 7026677Abstract: The present invention provides a magnetic memory device capable of performing stable operation efficiently using a magnetic field generated by write current and formed with high precision while realizing a compact configuration. Since a plating film is used for at least a part of a magnetic yoke, as compared with the case of formation by a dry film forming method, sufficient thickness and higher dimensional precision can be obtained. Consequently, a more stabilized return magnetic field can be generated and high reliability can be assured. Neighboring memory cells can be disposed at narrower intervals, so that the invention is suitable for realizing higher integration and higher packing density.Type: GrantFiled: July 20, 2004Date of Patent: April 11, 2006Assignee: TDK CorporationInventors: Akifumi Kamijima, Hitoshi Hatate