Abstract: A sensor configured to sense when a force is applied to a surface includes a capacitive structure having a first conductive layer, a dielectric layer, and a second conductive layer. The dielectric layer is overlain on the first conductive layer and the second conductive layer is overlain on the dielectric layer. A glass superstrate has a first side and a second side, with the first side overlain on the second conductive layer. The force is applied to the second side of the glass superstrate. The force results from an object attached to the second side of the glass superstrate. The force causes capacitance changes between the first and second conductive layers. The force can be compressive or tensile, depending on whether the object is attached by magnet or adhesive.

Abstract: An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-MRAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) with an upper MTJ layer, lower MTJ layer, and tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. In an embodiment the first and second ILDs directly contact one another. Other embodiments are described herein.

Abstract: A MTJ for a spintronic device that is a domain wall motion device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/X)n or (CoX)n composition where n is from 2 to 30, X is one of V, Rh, Ir, Os, Ru, Au, Cr, Mo, Cu, Ti, Re, Mg, or Si, and CoX is a disordered alloy. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.

Abstract: A MTJ for a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/X)n or (CoX)n composition where n is from 2 to 30, X is one of V, Rh, Ir, Os, Ru, Au, Cr, Mo, Cu, Ti, Re, Mg, or Si, and CoX is a disordered alloy. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.

Abstract: Provided is a magnetic tunneling junction device including a first structure including a magnetic layer; a second structure including at least two extrinsic perpendicular magnetization structures, each including a magnetic layer and; a perpendicular magnetization inducing layer on the magnetic layer; and a tunnel barrier between the first and second structures.

Abstract: The present invention is directed to a method for forming a magnetic tunnel junction (MTJ) memory element comprising the steps of providing a substrate having a bottom electrode layer thereon; depositing an MTJ layer stack on top of the bottom electrode layer; forming a composite hard mask comprising a bottom conducting mask disposed on top of the MTJ layer stack and a top conducting mask with a dielectric mask interposed therebetween; etching the MTJ layer stack with the composite hard mask thereon to form a patterned MTJ while consuming the top conducting mask, thereby exposing the dielectric mask on top; and trimming the patterned MTJ with the bottom conducting mask and the dielectric mask thereon by ion beam etching to remove redeposited material and damaged material from surface of the patterned MTJ while consuming most of the dielectric mask.

Abstract: To provide a semiconductor device in which wireless communication is performed between devices formed over different substrates and connection defects of wirings are reduced. A first device having a first antenna is provided over a first substrate, a second device having a second antenna which can communicate with the first antenna is provided over a second substrate, and the first substrate and the second substrate are bonded to each other to manufacture a semiconductor device. The first substrate and the second substrate are bonded to each other by bonding with a bonding layer interposed therebetween, anodic bonding, or surface activated bonding.

Abstract: A magnetoresistive element according to an embodiment includes: a first to third ferromagnetic layers, and a first nonmagnetic layer, the first and second ferromagnetic layers each having an axis of easy magnetization in a direction perpendicular to a film plane, the third ferromagnetic layer including a plurality of ferromagnetic oscillators generating rotating magnetic fields of different oscillation frequencies from one another. Spin-polarized electrons are injected into the first ferromagnetic layer and induce precession movements in the plurality of ferromagnetic oscillators of the third ferromagnetic layer by flowing a current between the first and third ferromagnetic layers, the rotating magnetic fields are generated by the precession movements and are applied to the first ferromagnetic layer, and at least one of the rotating magnetic fields assists a magnetization switching in the first ferromagnetic layer.

Abstract: A method that includes forming a first layer having a first dopant concentration, the first layer having an integrated circuit region and a micro-electromechanical region and doping the micro-electromechanical region of the first layer to have a second dopant concentration is presented. The method includes forming a second layer having a third dopant concentration overlying the first layer, doping the second layer that overlies the micro-electromechanical region to have a fourth dopant concentration, forming a micro-electromechanical structure in the micro-electromechanical region using the first and second layers, and forming active components in the integrated circuit region using the second layer.

Abstract: A semiconductor pressure sensor includes n-type semiconductor regions, which are formed in a diaphragm of a semiconductor substrate, piezoresistive elements, which are respectively formed in the n-type semiconductor regions, and conductive shielding thin film layers, which are respectively formed on the piezoresistive elements through an insulating thin film layer, and the piezoresistive elements form a Wheatstone bridge circuit. Further, the n-type semiconductor regions and the conductive shielding thin film layers are electrically connected to each other through contacts formed in the diaphragm.

Abstract: An object of the invention is to ensure the thermal stability of magnetization even when a magnetic memory element is miniaturized. A magnetic memory element includes a first magnetic layer (22), an insulating layer (21) that is formed on the first magnetic layer (22), and a second magnetic layer (20) that is formed on the insulating layer (21). At least one of the first magnetic layer (22) and the second magnetic layer (20) is strained and deformed so as to be elongated in an easy magnetization axis direction of the magnetic layer (22) or (20) or compressive strain (101) remains in any direction in the plane of at least one of the first magnetic layer and the second magnetic layer.

Abstract: Provided is a magnetic tunneling junction device including a first structure including a magnetic layer; a second structure including at least two extrinsic perpendicular magnetization structures, each including a magnetic layer and; a perpendicular magnetization inducing layer on the magnetic layer; and a tunnel barrier between the first and second structures.

Abstract: A free ferromagnetic data storage layer of an MRAM cell is coupled to a free ferromagnetic stabilization layer, which stabilization layer is directly electrically coupled to a contact electrode, on one side, and is separated from the free ferromagnetic data storage layer, on an opposite side, by a spacer layer. The spacer layer provides for the coupling between the two free layers, which coupling is one of: a ferromagnetic coupling and an antiferromagnetic coupling.

Abstract: A MEMS coupler and a method to form a MEMS structure having such a coupler are described. In an embodiment, a MEMS structure comprises a member and a substrate. A coupler extends through a portion of the member and connects the member with the substrate. The member is comprised of a first material and the coupler is comprised of a second material. In one embodiment, the first and second materials are substantially the same. In one embodiment, the second material is conductive and is different than the first material. In another embodiment, a method for fabricating a MEMS structure comprises first forming a member above a substrate. A coupler comprised of a conductive material is then formed to connect the member with the substrate.

Abstract: A MTJ for a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/X)n or (CoX)n composition where n is from 2 to 30, X is one of V, Rh, Ir, Os, Ru, Au, Cr, Mo, Cu, Ti, Re, Mg, or Si, and CoX is a disordered alloy. The seed layer is preferably NiCr, NiFeCr, Hf, or a composite thereof with a thickness from 10 to 100 Angstroms. Furthermore, a magnetic layer such as CoFeB may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.

Abstract: Provided are magnetic memory devices, electronic systems and memory cards including the same, methods of manufacturing the same, and methods of controlling a magnetization direction of a magnetic pattern. In a magnetic memory device, atomic-magnetic moments non-parallel to one surface of a free pattern increase in the free pattern. Therefore, critical current density of the magnetic memory device may be reduced, such that power consumption of the magnetic memory device is reduced or minimized and/or the magnetic memory device is improved or optimized for a higher degree of integration.

Abstract: To provide a semiconductor device in which wireless communication is performed between devices formed over different substrates and connection defects of wirings are reduced. A first device having a first antenna is provided over a first substrate, a second device having a second antenna which can communicate with the first antenna is provided over a second substrate, and the first substrate and the second substrate are bonded to each other to manufacture a semiconductor device. The first substrate and the second substrate are bonded to each other by bonding with a bonding layer interposed therebetween, anodic bonding, or surface activated bonding.

Abstract: A reliable long life RF-MEMS capacitive switch is provided with a dielectric layer comprising a “fast discharge diamond dielectric layer” and enabling rapid switch recovery, dielectric layer charging and discharging that is efficient and effective to enable RF-MEMS switch operation to greater than or equal to 100 billion cycles.

Abstract: A MTJ for a spintronic device is disclosed and includes a thin seed layer that enhances perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (Co/X)n or (CoX)n composition where n is from 2 to 30, X is one of V, Rh, Ir, Os, Ru, Au, Cr, Mo, Cu, Ti, Re, Mg, or Si, and CoX is a disordered alloy. A CoFeB layer may be formed between the laminated layer and a tunnel barrier layer to serve as a transitional layer between a (111) laminate and (100) MgO tunnel barrier. The laminated layer may be used as a reference layer, dipole layer, or free layer in a MTJ. Annealing between 300° C. and 400° C. may be used to further enhance PMA in the laminated layer.

Abstract: A STT-MTJ MRAM cell that utilizes transfer of spin angular momentum as a mechanism for changing the magnetic moment direction of a free layer includes an IrMn pinning layer, a SyAP pinned layer, a naturally oxidized, crystalline MgO tunneling barrier layer that is formed on an Ar-ion plasma smoothed surface of the pinned layer and a free layer that comprises an amorphous layer of Co60Fe20B20 of approximately 20 angstroms thickness or an amorphous ferromagnetic layer of Co40Fe40B20 of approximately 15 angstroms thickness formed between two crystalline layers of Fe of 3 and 6 angstroms thickness respectively. The free layer is characterized by a low Gilbert damping factor and by very strong polarizing action on conduction electrons. The resulting cell has a low critical current, a high dR/R and a plurality of such cells will exhibit a low variation of both resistance and pinned layer magnetization angular dispersion.

Abstract: A manufacturing method for a hollow sealing structure, includes, a process for filling a recessed portion in a principal surface of a substrate with a first sacrificial layer, a process for forming a functional element portion on the principal surface of the substrate, a process for forming a second sacrificial layer on the functional element portion so as to be connected to a part of the first sacrificial layer, a process for forming a covering portion over respective surfaces of the first and second sacrificial layers, a process for circulating a fluid for sacrificial layer removal through an opening in the covering portion in contact with the first sacrificial layer, thereby removing the first and second sacrificial layers, and a process for closing the opening.

Abstract: Electrical energy generation apparatuses, in which a solar battery device and a piezoelectric device are combined in a single body by using a plurality of nano wires formed of a semiconductor material having piezoelectric properties.

Abstract: System and methods offset mechanism elements during fabrication of Micro-Electro-Mechanical Systems (MEMS) devices. An exemplary embodiment applies a voltage across an offset mechanism element and a bonding layer of a MEMS device to generate an electrostatic charge between the offset mechanism element and the bonding layer, wherein the electrostatic charge draws the offset mechanism element to the bonding layer. The offset mechanism element and the bonding layer are then bonded.

Abstract: A method and system for providing a magnetic junction usable in a magnetic device are described. The magnetic junction includes a pinned layer, a nonmagnetic spacer layer, and a free layer. The nonmagnetic spacer layer is between the pinned layer and the free layer. The free layer has an easy cone magnetic anisotropy. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.

Abstract: A method that includes forming a first layer having a first dopant concentration, the first layer having an integrated circuit region and a micro-electromechanical region and doping the micro-electromechanical region of the first layer to have a second dopant concentration is presented. The method includes forming a second layer having a third dopant concentration overlying the first layer, doping the second layer that overlies the micro-electromechanical region to have a fourth dopant concentration, forming a micro-electromechanical structure in the micro-electromechanical region using the first and second layers, and forming active components in the integrated circuit region using the second layer.

Abstract: A method of fabricating a micro-electromechanical system microphone structure is disclosed. First, a substrate defining a MEMS region and a logic region is provided, and a surface of the substrate has a dielectric layer thereon. Next, at least one metal interconnect layer is formed on the dielectric layer in the logic region, and at least one micro-machined metal mesh is simultaneously formed in the dielectric layer of the MEMS region. Therefore, the thickness of the MEMS microphone structure can be effectively reduced.

Abstract: A method of fabricating a micro-electromechanical system microphone structure is disclosed. First, a substrate defining a MEMS region and a logic region is provided, and a surface of the substrate has a dielectric layer thereon. Next, at least one metal interconnect layer is formed on the dielectric layer in the logic region, and at least one micro-machined metal mesh is simultaneously formed in the dielectric layer of the MEMS region. Therefore, the thickness of the MEMS microphone structure can be effectively reduced.

Abstract: A spin transistor conducive to the miniaturization and large scale integration of devices, because a magnetization direction of a source and a drain is determined by a direction of the epitaxial growth of a ferromagnet. The spin transistor includes a semiconductor substrate having a channel layer formed thereinside; ferromagnetic source and drain epitaxially grown on the semiconductor substrate and magnetized in a longitudinal direction of the channel layer due to magnetocrystalline anisotropy—the source and drain being disposed spaced apart from each other in a channel direction and magnetized in the same direction—; and a gate disposed between the source and the drain to be insulated with the semiconductor substrate and formed on the semiconductor substrate to control the spin of electrons that are passed through the channel layer.

Abstract: A nano-resonator including a beam having a composite structure may include a silicon carbide beam and/or a metal conductor. The metal conductor may be vapor-deposited on the silicon carbide beam. The metal conductor may have a density lower than a density of the silicon carbide beam.

Abstract: When a positive voltage of V1 is applied to a drive capacitor with a braking voltage V2 at 0V, a moveable electrode moves toward the drive electrode, and a capacitance C of a tunable capacitor becomes smaller. When the braking voltage V2 is applied a lower portion brake electrode of the brake capacitor moves in a horizontal direction, such that the inter electrode separation distance between an upper portion brake electrode and the lower portion brake electrode becomes 0 ?m. The moveable electrode configured integrally formed with the lower portion brake electrode also moves in the horizontal direction, and the inter electrode separation distance between the moveable electrode and a fixed electrode becomes 0 ?m. Since the two electrodes make contact with each other with a dielectric layer interposed therebetween, the position of the moveable electrode can be stably maintained by frictional force between the electrodes.

Abstract: A high performance TMR sensor is fabricated by employing a composite inner pinned (AP1) layer in an AP2/Ru/AP1 pinned layer configuration. In one embodiment, there is a 10 to 80 Angstrom thick lower CoFeB or CoFeB alloy layer on the Ru coupling layer, a and 5 to 50 Angstrom thick Fe or Fe alloy layer on the CoFeB or CoFeB alloy, and a 5 to 30 Angstrom thick Co or Co rich alloy layer formed on the Fe or Fe alloy. A MR ratio of about 48% with a RA of <2 ohm-um2 is achieved when a CoFe AP2 layer, MgO (NOX) tunnel barrier, and CoFe/NiFe free layer are used in the TMR stack. Improved RA uniformity and less head noise are observed. Optionally, a CoFe layer may be inserted between the coupling layer and CoFeB or CoFeB alloy layer to improve pinning strength and enhance crystallization.

Abstract: An MRAM structure is disclosed in which the bottom electrode has an amorphous TaN capping layer to consistently provide smooth and dense growth for AFM, pinned, tunnel barrier, and free layers in an overlying MTJ. Unlike a conventional Ta capping layer, TaN is oxidation resistant and has high resistivity to avoid shunting of a sense current caused by redeposition of the capping layer on the sidewalls of the tunnel barrier layer. Alternatively, the ?-TaN layer is the seed layer in the MTJ. Furthermore, the seed layer may be a composite layer of NiCr, NiFe, or NiFeCr layer on the oc-TaN layer. An ?-TaN capping layer or seed layer can also be used in a TMR read head. An MTJ formed on an ?-TaN capping layer has a high MR ratio, high Vb, and a RA similar to results obtained from MTJs based on an optimized Ta capping layer.

Abstract: A structure which prevents thinning and disconnection of a wiring is provided, in a micromachine (MEMS structure body) formed with a surface micromachining technology. A wiring (upper auxiliary wiring) over a sacrificial layer is electrically connected to a different wiring (upper connection wiring) over the sacrificial layer, so that thinning, disconnection, and the like of the wiring formed over the sacrificial layer at a step portion generated due to the thickness of the sacrificial layer can be prevented. The wiring over the sacrificial layer is formed of the same conductive film as an upper driving electrode which is a movable electrode and is thus thin. However, the different wiring is formed over a structural layer, which is formed by a CVD method and has a rounded step, and has a thickness of 200 nm to 1 ?m, whereby thinning, disconnection, and the like of the wiring can be further prevented.

Abstract: A spin transistor useful for device miniaturization and high-density integration is provided. The spin transistor includes: a semiconductor substrate including a channel layer; ferromagnetic source and drain disposed on the semiconductor substrate to be separated from each other and to be magnetized in a direction perpendicular to a surface of the channel layer; a gate formed on the semiconductor substrate between the source and the drain to adjust spins of electrons passing through the channel layer, wherein spin-polarized electrons are injected from the source to the channel layer, and the electrons injected into the channel layer pass though the channel layer and are injected into the drain, and wherein the spins of the electrons passing through the channel layer undergo precession due to a spin-orbit coupling induced magnetic field according to a voltage of the gate.

Abstract: A method and apparatus is provided for use in an integrated circuit or printed circuit board for reducing or minimizing interference. An inductance is formed using two or more inductors coupled together and configured such that current flows through the inductors in different directions, thus at least partially canceling magnetic fields. When designing a circuit, the configuration of the inductors, as well as the relative positions of portions of the circuit, can be tweaked to provide optimal interference or noise control.

Abstract: A magnetic memory element having a layer structure containing a fixing layer (pinned layer: PL) having a magnetization direction fixed unidirectionally, a nonmagnetic dielectric layer (TN1) in contact with the fixing layer (PL), and a memory layer (free layer: FL) having a first surface in contact with the nonmagnetic dielectric layer (TN1) and a second surface on the opposite to the first surface, the magnetization direction of the memory layer (FL) having a reversible magnetization direction in response to the current through the layer structure. The entire surface of the first surface of the memory layer (FL) is covered with the nonmagnetic dielectric layer (TN1) and in the joint surface of the nonmagnetic dielectric layer (TN1) and the fixing layer (PL), the first surface of the nonmagnetic dielectric layer (TN1) is exposed in a manner of surrounding the joint surface.

Abstract: A manufacturing method for a hollow sealing structure, includes, a process for filling a recessed portion in a principal surface of a substrate with a first sacrificial layer, a process for forming a functional element portion on the principal surface of the substrate, a process for forming a second sacrificial layer on the functional element portion so as to be connected to a part of the first sacrificial layer, a process for forming a covering portion over respective surfaces of the first and second sacrificial layers, a process for circulating a fluid for sacrificial layer removal through an opening in the covering portion in contact with the first sacrificial layer, thereby removing the first and second sacrificial layers, and a process for closing the opening.

Abstract: An impact sensor comprises a silicon substrate; an insulating layer formed over the silicon substrate; a plurality of beams having flexibility that are formed of conductive silicon material; a fixing portion to fix a fixed end of each of the beams, the fixing portion being formed of conductive silicon material; a fixed end line at whose one end is formed the fixing portion, the fixed end line being formed of conductive silicon material on the insulating layer; and a free end line having a pressing portion that faces a free end of each of the beams via a space, the free end line being formed of conductive silicon material on the insulating layer. Respective beam widths, each measured in a direction orthogonal to a length direction joining the fixed end and the free end, of the plurality of beams are set different from each other, thus reducing the space occupied by the sensor.

Abstract: A free ferromagnetic data storage layer of an MRAM cell is coupled to a free ferromagnetic stabilization layer, which stabilization layer is directly electrically coupled to a contact electrode, on one side, and is separated from the free ferromagnetic data storage layer, on an opposite side, by a spacer layer. The spacer layer provides for the coupling between the two free layers, which coupling is one of: a ferromagnetic coupling and an antiferromagnetic coupling.

Abstract: A resonator includes a CMOS substrate having a first electrode and a second electrode. The CMOS substrate is configured to provide one or more control signals to the first electrode. The resonator also includes a resonator structure including a silicon material layer. The resonator structure is coupled to the CMOS substrate and configured to resonate in response to the one or more control signals.

Abstract: A capped integrated device includes a semiconductor chip, incorporating an integrated device and a protective cap, bonded to the semiconductor chip for protection of the integrated device by means of a bonding layer made of a bonding material. The bonding material forms anchorage elements within recesses, formed in at least one between the semiconductor chip and the protective cap.

Abstract: Devices having magnetic or magnetoresistive tunnel junctions (MTJS) have a multilayer insulator barrier layer to produce balanced write switching currents in the device circuitry, or to produce the magnetic devices with balanced critical spin currents required for spin torque transfer induced switching of the magnetization, or both for the MTJs under both the forward and reversed bias directions.

Abstract: A method of forming a microstructure body and a semiconductor element for controlling the microstructure body over the same substrate to reduce manufacturing cost, for mass-production of micromachines having a microstructure. In manufacturing a micromachine, a sacrifice layer is formed using a mask material for forming a pattern of a film, and removal of the mask in a region for forming a semiconductor element and removal of the sacrifice layer and the mask in a region for forming a microstructure body are performed by the same step. Specifically, a manufacturing method of a micro-electro-mechanical device is provided wherein a sacrifice layer is selectively formed over an insulating substrate, a semiconductor layer is formed to cover the sacrifice layer, a mask is formed over the semiconductor layer, the semiconductor layer is etched using the mask, and the mask and the sacrifice layer are removed by the same step.

Abstract: An STT-MTJ MRAM cell utilizes transfer of spin angular momentum as a mechanism for changing the magnetic moment direction of a free layer. The cell includes an IrMn pinning layer, a SyAP pinned layer, a naturally oxidized, crystalline MgO tunneling barrier layer that is formed on an Ar-ion plasma smoothed surface of the pinned layer and, in one embodiment, a composite tri-layer free layer that comprises an amorphous layer of Co60Fe20B20 of approximately 20 angstroms thickness formed between two crystalline layers of Fe of 3 and 6 angstroms thickness respectively. The free layer is characterized by a low Gilbert damping factor and by very strong polarizing action on conduction electrons. The resulting cell has a low critical current, a high dR/R and a plurality of such cells will exhibit a low variation of both resistance and pinned layer magnetization angular dispersion.

Abstract: An MTJ MRAM cell and its method of formation are described. The cell includes a composite free layer having the general form (Ni88Fe12)1-xCo100x—Ni92Fe8 with x between 0.05 and 0.1 that provides low magnetization and negative magnetostriction. The magnetostriction can be tuned to a low value by a multilayer capping layer that includes a positive magnetostriction layer of NiFeHf(15%). When this cell forms an MRAM array, it contributes to a TMR?26%, a TMR/Rp—cov?15.5 and a high AQF (array quality factor) for write operations.

Abstract: Nanotube device structures and methods of fabrication. A method of making a nanotube switching element includes forming a first structure having at a first output electrode; forming second structure having a second output electrode; forming a conductive article having at least one nanotube, the article having first and second ends; positioning the conductive article between said first and second structures such that the first structure clamps the first and second ends of the article to the second structure, and such that the first and second output electrodes are opposite each other with the article positioned therebetween; providing at least one signal electrode in electrical communication with the conductive article; and providing at least one control electrode in spaced relation to the conductive article such that the control electrode may control the conductive article to form a conductive pathway between the signal electrode and the first output electrode.

Abstract: A magnetic switching element includes a ferromagnetic layer which is substantially pinned in magnetization in one direction; and a magnetic semiconductor layer provided within a range where a magnetic field from the ferromagnetic layer reaches, where the magnetic semiconductor layer changes its state from a paramagnetic state to a ferromagnetic state by applying a voltage thereto, and a magnetization corresponding to the magnetization of the ferromagnetic layer is induced in the magnetic semiconductor layer by applying a voltage to the magnetic semiconductor layer.

Abstract: The magnetic device comprises a least two layers made of a magnetic material that are separated by at least one interlayer made of a non-magnetic material. The layers made of a magnetic material each have magnetization oriented substantially perpendicular to the plane of the layers. The layer of non-magnetic material induces an antiferromagnetic coupling field between the layers made of a magnetic material, the direction and amplitude of this field attenuating the effects of the ferromagnetic coupling field of magnetostatic origin that occurs between the magnetic layers.

Abstract: An RF MEMS tuneable arrangement, e.g. variable capacitor, having two or more tunable devices, e.g. variable capacitances, a coupling circuit arranged to couple the tunable devices together to provide a combined output, e.g. a combined capacitance, that is variable according to a tuning signal. The coupling circuit is reconfigurable to alter a response of the arrangement to changes in the tuning signal, to enable a broader range of applications, manufacturing cost reductions and more flexibility in design. The device can have a pivoted beam (30), actuable by a control signal, the beam having electrodes (40, 60) at either side of the pivot, and corresponding fixed electrodes (50, 70) facing the electrodes on the beam to provide a two or more variable devices such as switches or variable capacitors, arranged such that a given movement of the beam causes electrode separation in the same direction for the two or more switches or capacitors.

Abstract: A STT-MTJ MRAM cell that utilizes transfer of spin angular momentum as a mechanism for changing the magnetic moment direction of a free layer includes an IrMn pinning layer, a SyAP pinned layer, a naturally oxidized, crystalline MgO tunneling barrier layer that is formed on an Ar-ion plasma smoothed surface of the pinned layer and, in one embodiment, a free layer that comprises an amorphous layer of Co60Fe20B20 of approximately 20 angstroms thickness formed between two crystalline layers of Fe of 3 and 6 angstroms thickness respectively or on a single such layer. The free layer is characterized by a low Gilbert damping factor and by very strong polarizing action on conduction electrons. The resulting cell has a low critical current, a high dR/R and a plurality of such cells will exhibit a low variation of both resistance and pinned layer magnetization angular dispersion.