Abstract: A magnetic transistor includes a first magnetic section, a second magnetic section, a conductive section, a first metal terminal, and a second metal terminal. The conductive section is disposed between and is in direct contact with both the first and second magnetic section. The first metal terminal is disposed on one end of an opposite surface to the conductive section of the first magnetic section. The second metal terminal is disposed on one end approximately diagonal to the first metal terminal on an opposite surface to the conductive section of the second magnetic section. While the magnetic transistor structure is turned on, a current flows through the first magnetic section and the second magnetic section via the conductive section.

Abstract: Systems and methods for assembling a structure onto a substrate include an array of programmable magnets disposed beneath a substrate, wherein a magnetic field is applied to the structure to levitate the structure above the substrate while the structure is moved relative to the substrate to align the structure with a corresponding recess formed in the substrate. A magnetic field may be applied to translate and rotate the structure relative to the substrate. Differences between or among the programmable magnets regarding magnetic polarity, energized versus de-energized status, and magnetic field strength may be used to move the structure relative to the substrate in conjunction with a closed-loop control system. A bonded substrate assembly and a method of bonding a first wafer to a second wafer include wherein the first wafer includes a projection and the second wafer includes a matching depression.

Abstract: Embodiments of the present invention generally relate to a device that has an improved usable lifetime due to the presence of a lubricant that reduces the likelihood of stiction occurring between the various moving parts in an electromechanical device. Embodiments of the present invention also generally include a device, and a method of forming a device, that has one or more surfaces or regions that have a volume of lubricant disposed thereon that acts as a ready supply of “fresh” lubricant to prevent stiction occurring between interacting components found within the device. In one aspect, components within the volume of lubricant form a gas or vapor phase that reduces the chances of stiction-related failure in the formed device. In one example, aspects of this invention may be especially useful for fabricating and using micromechanical devices, such as MEMS devices, NEMS devices, or other similar thermal or fluidic devices.

Abstract: A bipolar spin transistor is provided. In one embodiment of the present invention, the bipolar spin transistor includes a first semiconductor region having a first conductivity type, a second semiconductor region having a second conductivity type that is different from the first conductivity type and also having a spin polarization, and a third semiconductor region having a conductivity type that is the same conductivity type of the first semiconductor region. The first semiconductor region and the second semiconductor region are adjacent to each other so as to form a first charge depletion layer therebetween, the first charge depletion layer having a first side facing the first semiconductor region and an opposing second side facing the second semiconductor region.

Abstract: A small structure which uses bonding wires to prevent disturbance and provide support and a method of fabricating the same are provided. The small structure includes a floating body having a plurality of first contact pads, a base having a plurality of second contact pads, and a plurality of bonding wires electrically connecting the first and second contact pads and elastically supporting the floating body. The method of fabricating the small structure includes preparing a base, forming a sacrificial layer on the base, disposing a floating body on the sacrificial layer, connecting the base and the floating body with bonding wires, and removing the sacrificial layer. Thereby, fabrication costs of the small structure are reduced.

Abstract: A magnetic memory element includes a laminated construction of an electrode, a first pinned layer, a first intermediate layer, a first memory layer, a second intermediate layer, a second memory layer, a third intermediate layer, a second pinned layer and electrode. The magnetization direction of the first memory layer takes a first and a second directions and that of the second memory layer takes a third and a fourth directions corresponding to a value and polarity of a current between the electrodes. In response to the current, the second intermediate layer has an electric resistance higher than the first intermediate layer and than the third intermediate layer.

Abstract: A semiconductor device and a method of producing the same is disclosed, in which a through hole is formed in the upper surface of a semiconductor substrate from the lower surface thereof, and an opening of a desired size is formed in a desired position on the upper surface of the substrate. A guide that functions as an etching stopper is formed in the semiconductor substrate. An opening having a width W2 is formed in the guide. The opening faces an opening in a mask used in the formation of a through hole, and the width W2 thereof is narrower than a width W4 of the opening in the mask. The direction in which etching progresses is controlled by the opening formed in the guide as etching is conducted from a lower surface of the substrate to an upper surface of the substrate, and thus deviations in the width W1 and position of an opening in the upper surface of the substrate can be controlled.

Abstract: An electronically scannable multiplexing device is capable of addressing multiple bits within a volatile or non-volatile memory cell. The multiplexing device generates an electronically scannable conducting channel with two oppositely formed depletion regions. The depletion width of each depletion region is controlled by a voltage applied to a respective control gate at each end of the multiplexing device. The present multi-bit addressing technique allows, for example, 10 to 100 bits of data to be accessed or addressed at a single node. The present invention can also be used to build a programmable nanoscale logic array or for randomly accessing a nanoscale sensor array.

Abstract: There is disclosed a switching element including a first input/output electrode, a movable portion which repeats contact/non-contact with respect to the first input/output electrode, a second input/output electrode connected with the movable portion, a floating gate electrode which is coupled with the movable portion through an insulating layer and in which electric charge is stored, and a first gate electrode which generates an electrostatic force between itself and the floating gate electrode to control an operation of the movable portion.

Abstract: An electric field read/write head, a method of manufacturing the same, and a data read/write device including the electric field read/write head are provided. The data read/write device includes an electric field read/write head which reads and writes data to and from a recording medium. The electric field read/write head includes a semiconductor substrate, a resistance region, source and drain regions, and a write electrode. The semiconductor substrate includes a first surface and a second surface with adjoining edges. The resistance region is formed to extend from a central portion at one end of the first surface to the second surface. The source region and the drain region are formed at either side of the resistance region and are separated from the first surface. The write electrode is formed on the resistance region with an insulating layer interposed between the write electrode and the resistance region.

Abstract: A high performance TMR sensor is fabricated by employing a composite inner pinned (AP1) layer in an AP2/Ru/AP1 pinned layer configuration. In one embodiment, there is a 10 to 80 Angstrom thick lower CoFeB or CoFeB alloy layer on the Ru coupling layer, a and 5 to 50 Angstrom thick Fe or Fe alloy layer on the CoFeB or CoFeB alloy, and a 5 to 30 Angstrom thick Co or Co rich alloy layer formed on the Fe or Fe alloy. A MR ratio of about 48% with a RA of <2 ohm-um2 is achieved when a CoFe AP2 layer, MgO (NOX) tunnel barrier, and CoFe/NiFe free layer are used in the TMR stack. Improved RA uniformity and less head noise are observed. Optionally, a CoFe layer may be inserted between the coupling layer and CoFeB or CoFeB alloy layer to improve pinning strength and enhance crystallization.

Abstract: A high performance TMR sensor is fabricated by employing a composite inner pinned (AP1) layer in an AP2/Ru/AP1 pinned layer configuration. In one embodiment, there is a 10 to 80 Angstrom thick lower CoFeB or CoFeB alloy layer on the Ru coupling layer, a and 5 to 50 Angstrom thick Fe or Fe alloy layer on the CoFeB or CoFeB alloy, and a 5 to 30 Angstrom thick Co or Co rich alloy layer formed on the Fe or Fe alloy. A MR ratio of about 48% with a RA of <2 ohm-um2 is achieved when a CoFe AP2 layer, MgO (NOX) tunnel barrier, and CoFe/NiFe free layer are used in the TMR stack. Improved RA uniformity and less head noise are observed. Optionally, a CoFe layer may be inserted between the coupling layer and CoFeB or CoFeB alloy layer to improve pinning strength and enhance crystallization.

Abstract: Methods and apparatus are provided for magnetic tunnel junctions (MTJs) (10, 50) employing synthetic antiferromagnet (SAF) free layers (14, 14?). The MTJ (10, 50) comprises a pinned ferromagnetic (FM) layer (32, 18), the SAF (14) and a tunneling barrier (16) therebetween. The SAF (14) has a first higher spin polarization FM layer (30) proximate the tunneling barrier (16) and a second FM layer (26) desirably separated from the first FM layer (30) by a coupling layer (28), with magnetostriction adapted to compensate the magnetostriction of the first FM layer (30). Such compensation reduces the net magnetostriction of the SAF (14) to near zero even with high spin polarization proximate the tunneling barrier (16). Higher magnetoresistance ratios (MRs) are obtained without adverse affect on other MTJ (10, 50) properties. NiFe combinations are desirable for the first (30) and second (26) free FM layers, with more Fe in the first (30) free layer and less Fe in the second (26) free layer.

Abstract: A magnetic sensor comprises a plurality of layers including a substrate having circuitry, at least one conductive layer to interconnect the circuitry, and an insulator layer to electrically insulate the at least one conductive layer. First and second conductive layers are disposed above the substrate with a dielectric layer disposed between the first and second conductive layers such that the first and second conductive layers and the dielectric layer form a capacitor. A first terminal is electrically connected to the first conductive layer and a second terminal is electrically connected to the second conductive layer.

Abstract: A nonvolatile memory cell includes a gate controlled diode steering element and a resistivity switching element.

Abstract: An electronically scannable multiplexing device is capable of addressing multiple bits within a volatile or non-volatile memory cell. The multiplexing device generates an electronically scannable conducting channel with two oppositely formed depletion regions. The depletion width of each depletion region is controlled by a voltage applied to a respective control gate at each end of the multiplexing device. The present multi-bit addressing technique allows, for example, 10 to 100 bits of data to be accessed or addressed at a single node. The present invention can also be used to build a programmable nanoscale logic array or for randomly accessing a nanoscale sensor array.

Abstract: A micro-generator includes an integrated circuit (IC) wafer. A micro-electro mechanical system (MEMS) wafer, with a movable micromechanical element, is bonded to the IC wafer. A plurality of first metal coils associated with a plurality of trenches is arranged in one of the IC wafer and the MEMS wafer. A plurality of micro-magnets is provided in the other of the IC wafer and the MEMS wafer. Each micro-magnet is associated with a respective trench and is formed from a magnet layer deposited, plated or bonded to the MEMS wafer or IC wafer. Movement of the micro-mechanical element generates a voltage in the first metal coils.

Abstract: A magnetic transistor includes a magnetic section, a thin semiconductor layer, a first metal terminal, a second metal terminal, and a third metal terminal. The thin semiconductor layer is disposed on the magnetic section. The first metal terminal is disposed on one end of the magnetic section, acting as a gate of the magnetic transistor and capable of providing a conductive channel in the thin semiconductor layer. The second metal terminal and the third metal terminal are disposed respectively on one end and the other end of the thin semiconductor layer, capable of creating a conductive region. While the magnetic transistor is turned on, a current path is formed between the second metal terminal and the third metal terminal via the thin semiconductor layer.

Abstract: A spin transistor useful for device miniaturization and high-density integration is provided. The spin transistor includes: a semiconductor substrate including a channel layer; ferromagnetic source and drain disposed on the semiconductor substrate to be separated from each other and to be magnetized in a direction perpendicular to a surface of the channel layer; a gate formed on the semiconductor substrate between the source and the drain to adjust spins of electrons passing through the channel layer, wherein spin-polarized electrons are injected from the source to the channel layer, and the electrons injected into the channel layer pass though the channel layer and are injected into the drain, and wherein the spins of the electrons passing through the channel layer undergo precession due to a spin-orbit coupling induced magnetic field according to a voltage of the gate.

Abstract: A surface-spintronic device operating on a novel principles of operations may be implemented as a spin conducting, a spin switching or a spin memory device. It includes a magnetic atom thin film (13) layered on a surface of a solid crystal (12) and a drain and a source electrodes (14)and (15) disposed at two locations on the magnetic atom thin film, respectively, whereby a spin splitting surface electronic state band formed in a system comprising said solid crystal(12) surface and said magnetic atom thin film (13) is utilized to obtain a spin polarized current flow. With electrons spin-polarized in a particular direction injected from the source electrode (15), controlling the direction of magnetization of the magnetic atom thin film (13) allows switching on and off the conduction of such injected electrons therethrough.

Abstract: A process for manufacturing an integrated membrane made of semiconductor material includes the step of forming, in a monolithic body of semiconductor material having a front face, a buried cavity, extending at a distance from the front face and delimiting with the front face a surface region of the monolithic body, the surface region forming a membrane that is suspended above the buried cavity. The process further envisages the step of forming an insulation structure in a surface portion of the monolithic body to electrically insulate the membrane from the monolithic body; and the further and distinct step of setting the insulation structure at a distance from the membrane so that it will be positioned outside the membrane at a non-zero distance of separation.

Abstract: Disclosed herein is a spin transistor including: a semiconductor substrate having a channel layer formed therein; first and second electrodes which are formed to be spaced apart from each other on the substrate at a predetermined distance along a longitudinal direction of the channel layer; a source and drain which include magnetized ferromagnetic materials and are formed to be spaced apart form each other between the first electrode and the second electrode at a predetermined distance along the longitudinal direction of the channel layer; and a gate which is formed on the substrate between the source and the drain, and adjusts spin orientations of electrons passing through the channel layer, wherein the electrons passing through the channel layer are spin-aligned at a lower side of the source by a stray magnetic field of the source and spin-filtered at a lower side of the drain by a stray field of the drain.

Abstract: An electronic component includes a semiconductor chip with a chip topside, an integrated circuit, and a chip backside. The chip backside includes a magnetic layer. The electronic component further includes a chip carrier with a magnetic layer on its carrier topside. At least one of the two magnetic layers is permanently magnetic such that the semiconductor chip is magnetically fixed on the chip carrier.

Abstract: A seek-scan probe (SSP) memory including a recess cavity to self-align magnets includes a frame, a movable platform movably coupled to the frame, a coil coupled to the movable platform, and a cap wafer having coupled to the frame. The cap wafer includes a recess cavity to receive a magnet that produces a magnetic field. By energizing the coil while in the magnetic field a physical force is produced that is translated into movement of the movable platform.

Abstract: A memory device or a logic device that uses an electronically scannable multiplexing device capable of addressing multiple bits within a volatile or non-volatile memory cell. The multiplexing device generates an electronically scannable conducting channel with two oppositely formed depletion regions. The depletion width of each depletion region is controlled by a voltage applied to a respective control gate at each end of the multiplexing device. The present multi-bit addressing technique allows, for example, 10 to 100 bits of data to be accessed or addressed at a single node. The present invention can also be used to build a programmable nanoscale logic array or for randomly accessing a nanoscale sensor array.

Abstract: A method for forming catalytic sites at the surface of a support, which includes: depositing on the surface a liquid film (3) containing elements (4) of a living matter, capable of moving when subjected to an electric and/or magnetic field and designed to form catalytic traces or alterations at the surface of the substrate; applying an electric and/or magnetic field to the film such that, under the effect of the field, at least some of the living matter elements move and assemble on zones of the substrate surface; and eliminating the liquid film and the living matter at the substrate surface while allowing the traces left by the living element at the substrate surface to subsist so as to constitute the catalytic sites at the locations of the traces.

Abstract: An interconnect module and a method of manufacturing the same. The method of making an interconnect module on a substrate comprises forming an interconnect section on the substrate. The interconnect section comprises at least two metal interconnect layers separated by a dielectric layer. The method further comprises forming a passive device on the substrate at a location laterally adjacent to the interconnect section. The passive device comprises at least one moveable element comprising a metal layer. The method further comprises forming the metal layer and one of the at least two metal interconnect layers from substantially the same material.

Abstract: A digital magnetic memory cell device for read and/or write operations, having a soft-magnetic read and/or write layer system and at least one hard-magnetic reference layer system, which is designed as an AAF system and includes at least one reference layer, wherein the reference layer system has a layer section comprising at least one bias layer system with at least one ferrimagnetic layer, the magnetic moments of the bias layer system and of the reference layer being coupled in opposite directions via a coupling layer.

Abstract: An electronic system is provided with a structure for improved transmission line operation on integrated circuits. The structure for transmission line operation includes a first layer of electrically conductive material on a substrate. A first layer of insulating material is formed on the first layer of the electrically conductive material. A number of high permeability metal lines are formed on the first layer of insulating material. The number of high permeability metal lines includes composite hexaferrite films. A number of transmission lines is formed on the first layer of insulating material and between and parallel with the high permeability metal lines. A second layer of insulating material is formed on the transmission line and the pair of high permeability metal lines. The structure for transmission line operation includes a second layer of electrically conductive material on the second layer of insulating material.

Abstract: One embodiment of the present invention provides a switching device that can vary a spin-polarized current based on an input signal. The switching device comprises a first conducting region, a second conducting region, and a half-metal region interposed between the first conducting region and the second conducting region. The half-metal region comprises a material which, at the intrinsic Fermi level, has substantially zero available electronic states in a minority spin channel. Changing the voltage of the half-metal region with respect to the first conducting region moves its Fermi level with respect to the electron energy bands of the first conducting region, which changes the number of available electronic states in the majority spin channel, and in doing so, changes the majority-spin polarized current passing through the switching device.

Abstract: A first electrode thin film is formed on an upper surface of the oxygen ion conductive thin film so as to have a through hole. A resistor is formed on part of the upper surface of the oxygen conductive thin film located in the through hole. Thus, the oxygen ion conductive thin film can be directly heated by the resistor, so that oxygen ions can be speedily transferred with a low power. Therefore, the oxygen ion conductivity of the oxygen ion conductive thin film can be improved.

Abstract: The present invention relates to a nanotube device (100, 600), comprising a nanotube with a longitudinal and a lateral extension, a structure for supporting at least a first part of the nanotube, and first means for exerting a force upon the nanotube in a first direction defined by its lateral extension. At least a second part of the nanotube protrudes beyond the support of said structure, so that when said force exceeds a certain level, the second part of the nanotube will flex in the direction of its lateral extension, and thereby close a first electrical circuit. Suitably, the first means for exerting said force upon the nanotube is an electrical means, the force being created by applying a voltage to the means.

Abstract: A package substrate is placed in a first predetermined position on a supporting equipment. A chip guide equipment and a magnetic-field-generating equipment in a second predetermined position are placed near the package substrate. A semiconductor chip having a photoelectric element and a solenoid electrically connected to the photoelectric element in a surface region of the semiconductor chip is placed on the package substrate with the surface region facing away from the package substrate. The photoelectric element of the semiconductor chip is exposed to light so as to move the semiconductor chip toward the chip guide equipment by an interaction between a first magnetic field of the solenoid and a second magnetic field of the magnetic-field-generating equipment. A manufacturing step to the semiconductor chip is performed while keeping the position of the semiconductor chip near the chip guide equipment.

Abstract: Methods and apparatus are provided for sensing physical parameters. The apparatus comprises a magnetic tunnel junction (MTJ) and a magnetic field source whose magnetic field overlaps the MTJ and whose proximity to the MTJ varies in response to an input to the sensor. The MTJ comprises first and second magnetic electrodes separated by a dielectric configured to permit significant tunneling conduction therebetween. The first magnetic electrode has its spin axis pinned and the second magnetic electrode has its spin axis free. The magnetic field source is oriented closer to the second magnetic electrode than the first magnetic electrode. The overall sensor dynamic range is extended by providing multiple electrically coupled sensors receiving the same input but with different individual response curves and desirably but not essentially formed on the same substrate.

Abstract: A magnetic data track used in a magnetic shift register memory system may be fabricated by forming a multilayered stack of alternating dielectric and/ or silicon layers. A trench is etched in the multi-layer stack structure. A selective etching process is used to corrugate the walls of trench. A seed layer is applied to the walls and bottom of the trench; the seed layer is covered with a magnetic layer. The trench is filled with an insulating material. A patterned layer is applied and portions of insulating material exposed by the pattern are removed, forming holes. Magnetic material and seed layer exposed in holes is selectively removed. The holes are filled with insulating material and connecting leads are attached to data tracks.

Abstract: A semiconductor apparatus includes lower conductive film strips, an inter-layer insulating layer, implanted conductive members, and upper conductive film strips. The lower conductive film strips are formed in a pattern closely adjacent in a line width orientation, electrically separated from each other. The inter-layer insulating layer is formed the lower conductive film strips. The implanted conductive members are implanted in connection holes formed in the inter-layer insulating layer at positions corresponding to both edge sides of the lower conductive film strips. The upper conductive film strips are formed on the implanted conductive members and the inter-layer insulating layer to connect the lower conductive film strips in series so that the lower conductive film strips, the implanted conductive members, and the upper conductive film strips form an electric coil.

Abstract: A common pinned layer is shared by multiple memory cells in an MRAM device. The common pinned layer includes a plurality of domain wall traps that prevent the formation of domain walls within a region of the common pinned layer corresponding to a given memory cell. Therefore, the memory cells can advantageously be formed such that the domain walls, to the extent they exist, fall between (rather than within) the memory cells, thereby improving the performance of the MRAM device.