Characterized By Amorphous Semiconductor Layer (epo) Patents (Class 257/E31.034)
  • Patent number: 9941431
    Abstract: A photodiode includes a light absorbing layer including a first superlattice structure that includes first semiconductor layers and second semiconductor layers, the first superlattice structure having a band structure sensitive to infrared light; a p-type semiconductor region; and an intermediate layer disposed between the p-type semiconductor region and the light absorbing layer, the intermediate layer having a conduction band having a bottom energy level lower than that of the p-type semiconductor region.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: April 10, 2018
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Kohei Miura, Yasuhiro Iguchi
  • Patent number: 8878259
    Abstract: Segmented semiconductor nanowires are manufactured by removal of material from a layered structure of two or more semiconductor materials in the absence of a template. The removal takes place at some locations on the surface of the layered structure and continues preferentially along the direction of a crystallographic axis, such that nanowires with a segmented structure remain at locations where little or no removal occurs. The interface between different segments can be perpendicular to or at angle with the longitudinal direction of the nanowire.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: November 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Harold J. Hovel, Qiang Huang, Xiaoyan Shao, James Vichiconti, George F. Walker
  • Patent number: 8629445
    Abstract: Provided are a semiconductor device with less leakage current is reduced, a semiconductor device with both of high field effect mobility and low leakage current, an electronic appliance with low power consumption, and a manufacturing method of a semiconductor device in which leakage current can be reduced without an increase in the number of masks. The side surface of a semiconductor layer formed of a semiconductor film having high carrier mobility is not in contact with any of a source electrode and a drain electrode. Further, such a transistor structure is formed without an increase in the number of photomasks and can be applied to an electronic appliance.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: January 14, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuhiro Tanaka, Ryo Tokumaru
  • Patent number: 8492746
    Abstract: A light emitting diode (LED) die includes a wavelength conversion layer having a base material, and a plurality of particles embedded in the base material including wavelength conversion particles, and reflective particles. A method for fabricating light emitting diode (LED) dice includes the steps of mixing the wavelength conversion particles in the base material to a first weight percentage, mixing the reflective particles in the base material to a second weight percentage, curing the base material to form a wavelength conversion layer having a selected thickness, and attaching the wavelength conversion layer to a die.
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: July 23, 2013
    Assignee: SemiLEDS Optoelectronics Co., Ltd.
    Inventor: Jui-Kang Yen
  • Patent number: 8415787
    Abstract: The present invention relates to a heat dissipator that includes a conductive substrate and a plurality of nanostructures supported by the conductive substrate. The nanostructures are at least partly embedded in an insulator. Each of the nanostructures includes a plurality of intermediate layers on the conductive substrate. At least two of the plurality of intermediate layers are interdiffused, and material of the at least two of the plurality of intermediate layers that are interdiffused is present in the nanostructure.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: April 9, 2013
    Assignee: Smoltek AB
    Inventor: Mohammad Shafiqul Kabir
  • Patent number: 8349644
    Abstract: A method for producing a backside contact of a single p-n junction photovoltaic solar cell is provided. The method includes the steps of: providing a p-type substrate having a back surface; providing a plurality of p+ diffusion regions at the back surface of the substrate; providing a plurality of n+ diffusion regions at the back surface of the substrate in an alternate pattern with the p+ diffusion regions; providing an oxide layer over the p+ and n+ regions; providing an insulating layer over the back surface of the substrate; providing at least one first metal contact at the back surface for the p+ diffusion regions; and providing at least one second metal contact at the back surface for the n+ diffusion regions.
    Type: Grant
    Filed: October 20, 2008
    Date of Patent: January 8, 2013
    Assignee: e-Cube Energy Technologies, Ltd.
    Inventors: Wei Shan, Xiao-Dong Xiang
  • Publication number: 20120318336
    Abstract: A photovoltaic device and method include a substrate coupled to an emitter side structure on a first side of the substrate and a back side structure on a side opposite the first side of the substrate. The emitter side structure or the back side structure include layers alternating between wide band gap layers and narrow band gap layers to provide a multilayer contact with an effectively increased band offset with the substrate and/or an effectively higher doping level over a single material contact. An emitter contact is coupled to the emitter side structure on a light collecting end portion of the device. A back contact is coupled to the back side structure opposite the light collecting end portion.
    Type: Application
    Filed: June 17, 2011
    Publication date: December 20, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: BAHMAN HEKMATSHOAR-TABARI, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 8273591
    Abstract: Segmented semiconductor nanowires are manufactured by removal of material from a layered structure of two or more semiconductor materials in the absence of a template. The removal takes place at some locations on the surface of the layered structure and continues preferentially along the direction of a crystallographic axis, such that nanowires with a segmented structure remain at locations where little or no removal occurs. The interface between different segments can be perpendicular to or at angle with the longitudinal direction of the nanowire.
    Type: Grant
    Filed: March 25, 2008
    Date of Patent: September 25, 2012
    Assignee: International Business Machines Corporation
    Inventors: Harold J. Hovel, Qiang Huang, Xiaoyan Shao, James Vichiconti, George F. Walker
  • Patent number: 8258002
    Abstract: A phase change memory device resistant to stack pattern collapse is presented. The phase change memory device includes a silicon substrate, switching elements, heaters, stack patterns, bit lines and word lines. The silicon substrate has a plurality of active areas. The switching elements are connected to the active areas. The heaters are connected to the switching elements. The stack patterns are connected to the heaters. The bit lines are connected to the stack patterns. The word lines are connected to the active areas of the silicon substrate.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: September 4, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Heon Yong Chang
  • Patent number: 8183659
    Abstract: The present invention provides for nanostructures grown on a conducting or insulating substrate, and a method of making the same. The nanostructures grown according to the claimed method are suitable for interconnects and/or as heat dissipators in electronic devices.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: May 22, 2012
    Inventor: Mohammad Shafiqul Kabir
  • Publication number: 20110203650
    Abstract: A photovoltaic converter device includes a first conductivity type substrate (a p-type single crystalline silicon substrate 100), a first intermediate layer (an i-type semiconductor layer 110 or a dielectric layer 160), and a second conductivity type semiconductor layer (an n-type semiconductor layer 120). The first intermediate layer (the i-type semiconductor layer 110 or the dielectric layer 160) includes quantum dots (nanoparticles) having at least cores. The first conductivity type substrate is formed from crystalline semiconductor such as single crystalline silicon.
    Type: Application
    Filed: February 24, 2011
    Publication date: August 25, 2011
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Masahiro FURUSAWA
  • Patent number: 7791106
    Abstract: Gallium nitride material-based semiconductor structures are provided. In some embodiments, the structures include a composite substrate over which a gallium nitride material region is formed. The gallium nitride material structures may include additional features, such as strain-absorbing layers and/or transition layers, which also promote favorable stress conditions. The reduction in stresses may reduce defect formation and cracking in the gallium nitride material region, as well as reducing warpage of the overall structure. The gallium nitride material-based semiconductor structures may be used in a variety of applications such as transistors (e.g. FETs) Schottky diodes, light emitting diodes, laser diodes, SAW devices, and sensors, amongst others devices.
    Type: Grant
    Filed: February 1, 2008
    Date of Patent: September 7, 2010
    Assignee: Nitronex Corporation
    Inventors: Edwin L. Piner, Pradeep Rajagopal, John C. Roberts, Kevin J. Linthicum
  • Patent number: 7777291
    Abstract: The present invention provides for nanostructures grown on a conducting or insulating substrate, and a method of making the same. The nanostructures grown according to the claimed method are suitable for interconnects and/or as heat dissipators in electronic devices.
    Type: Grant
    Filed: August 28, 2006
    Date of Patent: August 17, 2010
    Assignee: Smoltek AB
    Inventor: Mohammad Shafiqul Kabir
  • Patent number: 7682945
    Abstract: The present invention in one embodiment provides a method of forming a memory device that includes providing an interlevel dielectric layer including a conductive stud having a first width; forming an stack comprising a metal layer and a first insulating layer; forming a second insulating layer atop portions of the interlevel dielectric layer adjacent each sidewall of the stack; removing the first insulating layer to provide a cavity; forming a conformal insulating layer atop the second insulating layer and the cavity; applying an anisotropic etch step to the conformal insulating layer to produce a opening having a second width exposing an upper surface of the metal layer, wherein the first width is greater than the second width; and forming a memory material layer in the opening.
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: March 23, 2010
    Assignee: International Business Machines Corporation
    Inventors: Chung H. Lam, Matthew J. Breitwisch, Roger W. Cheek, Alejandro G. Schrott, Matthew D. Moon
  • Patent number: 7671354
    Abstract: An integrated circuit includes a contact, a first spacer, and a first electrode including a first portion and a second portion. The second portion contacts the contact and is defined by the first spacer. The integrated circuit includes a second electrode and resistivity changing material between the second electrode and the first portion of the first electrode.
    Type: Grant
    Filed: June 11, 2007
    Date of Patent: March 2, 2010
    Assignee: Qimonda AG
    Inventors: Thomas Happ, Jan Boris Philipp, Ulrike Gruening-von Schwerin
  • Patent number: 7601984
    Abstract: A novel amorphous oxide applicable, for example, to an active layer of a TFT is provided. The amorphous oxide comprises microcrystals.
    Type: Grant
    Filed: November 9, 2005
    Date of Patent: October 13, 2009
    Assignees: Canon Kabushiki Kaisha, Tokyo Institute of Technology
    Inventors: Masafumi Sano, Katsumi Nakagawa, Hideo Hosono, Toshio Kamiya, Kenji Nomura
  • Publication number: 20080223440
    Abstract: Embodiments of the present invention generally relate to solar cells and methods and apparatuses for forming the same. More particularly, embodiments of the present invention relate to thin film multi-junction solar cells and methods and apparatuses for forming the same.
    Type: Application
    Filed: April 25, 2008
    Publication date: September 18, 2008
    Inventors: SHURAN SHENG, Yong-Kee Chae, Soo Young Choi
  • Patent number: 7352044
    Abstract: A solar battery 10 comprises a metal electrode layer 12, a pin junction 100, and a transparent electrode layer 16 which are successively laminated on a substrate 11 such as a silicon substrate. The pin junction 100 comprises an n-layer 13, an i-layer 14, and a p-layer 15 which are laminated in succession. The i-layer 14 is formed by amorphous iron silicide (FexSiy:H) containing hydrogen atoms. In the i-layer 14, at least a part of the hydrogen atoms contained therein terminate dangling bonds of silicon atoms and/or iron atoms, so that a number of trap levels which may occur in an amorphous iron silicide film can be eliminated, whereby the i-layer 14 exhibits a characteristic as an intrinsic semiconductor layer.
    Type: Grant
    Filed: January 16, 2004
    Date of Patent: April 1, 2008
    Assignees: TDK Corporation, Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroshi Yamada, Hisao Morooka, Kazuo Nishi