Semiconductor Devices Responsive Or Sensitive To Electromagnetic Radiation (e.g., Infrared Radiation, Adapted For Conversion Of Radiation Into Electrical Energy Or For Control Of Electrical Energy By Such Radiation Processes, Or Apparatus Peculiar To Manufacture Or Treatment Of Such Devices, Or Of Parts Thereof) (epo) Patents (Class 257/E31.001)

  • Patent number: 10644055
    Abstract: A photoelectric conversion apparatus includes a semiconductor substrate including a photoelectric conversion portion, a metal containing portion provided on the semiconductor substrate, an interlayer insulation film arranged on the semiconductor substrate to cover the metal containing portion, a first silicon nitride layer arranged on the photoelectric conversion portion to include a portion lying between the interlayer insulation film and the semiconductor substrate, a silicon oxide film including a portion arranged between the first silicon nitride layer and the photoelectric conversion portion, and a portion arranged between the interlayer insulation film and the metal containing portion, a second silicon nitride layer arranged between the silicon oxide film and the metal containing portion.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: May 5, 2020
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shinji Kodaira, Takehito Okabe, Mitsuhiro Yomori, Nobuyuki Endo, Tomoyuki Tezuka, Toshihiro Shoyama, Jun Iwata
  • Patent number: 10020412
    Abstract: Solar cells are packaged by placing the solar cells between sheets of encapsulants. The encapsulants are exposed to ultraviolet (UV) light to cure the encapsulants and bond the encapsulants together to encapsulate the solar cells. The UV curing steps may be performed to bond one of the encapsulants to a transparent top cover and the solar cells, and to bond the other encapsulant to the solar cells and a backsheet. A protective package that includes the transparent top cover, encapsulated solar cells, and the backsheet is then optionally mounted on a frame.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: July 10, 2018
    Assignee: SunPower Corporation
    Inventor: Gabriela Bunea
  • Patent number: 9884369
    Abstract: The described embodiments relate generally to methods for forming structures by solid state deposition processes. More specifically a method for depositing cold spray over a removable body is disclosed. Methods are also disclosed for affixing operational and structural components to a surface of a device housing with cold spray.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: February 6, 2018
    Assignee: Apple Inc.
    Inventors: Simon Regis Louis Lancaster-Larocque, Ari P. Miller, Laura M. DeForest, Michelle R. Goldberg, William F. Leggett, Adam T. Garelli
  • Patent number: 9466752
    Abstract: Solar cells are packaged by placing the solar cells between sheets of encapsulants. The encapsulants are exposed to ultraviolet (UV) light to cure the encapsulants and bond the encapsulants together to encapsulate the solar cells. The UV curing steps may be performed to bond one of the encapsulants to a transparent top cover and the solar cells, and to bond the other encapsulant to the solar cells and a backsheet. A protective package that includes the transparent top cover, encapsulated solar cells, and the backsheet is then optionally mounted on a frame.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: October 11, 2016
    Assignee: SunPower Corporation
    Inventor: Gabriela Bunea
  • Patent number: 9006852
    Abstract: Disclosed herein is a solid-state imaging element including: a transfer section configured to transfer charge generated simultaneously by a photoelectric conversion section in all pixels to a memory section and have a metal gate; and a light-shielding section formed by filling a metal into a groove portion formed by digging an interlayer insulating film around the transfer section.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: April 14, 2015
    Assignee: Sony Corporation
    Inventor: Shinichi Arakawa
  • Patent number: 8993411
    Abstract: A method for forming a pad in a wafer with a three-dimensional stacking structure is disclosed. The method includes bonding a device wafer that includes an Si substrate and a handling wafer, thinning a back side of the Si substrate, depositing an anti-reflective layer on the thinned back side of the Si substrate, depositing a back side dielectric layer on the anti-reflective layer, defining a space for a pad in the back side dielectric layer and forming vias that pass through the back side dielectric layer and the anti-reflective layer and contact back sides of super contacts which are formed on the Si substrate, filling one or more metals in the vias and the defined space for the pad, and removing a remnant amount of the metal filled in the space for the pad through planarization by a CMP (chemical mechanical polishing) process.
    Type: Grant
    Filed: February 23, 2013
    Date of Patent: March 31, 2015
    Assignee: Siliconfile Technologies Inc.
    Inventors: Heui-Gyun Ahn, Se-Jung Oh, In-Gyun Jeon, Jun-Ho Won
  • Patent number: 8993371
    Abstract: The method of manufacturing a light absorbing layer for a solar cell by performing thermal treatment on a specimen configured to include thin films of one or more of copper, indium, and gallium on a substrate and element selenium, includes steps of: (a) heating a wall of a chamber up to a predefined thin film formation temperature in order to maintain a selenium vapor pressure; (b) mounting the specimen and the element selenium on the susceptor at the room temperature and loading the susceptor in the chamber; and (c) heating the specimen in the lower portion of the susceptor and, at the same time, heating the element selenium in the upper portion of the susceptor, wherein, in the step (c), in order for liquefied selenium not to be condensed on the specimen which is loaded at the room temperature and is not yet heated, the temperature of the element selenium and the specimen loaded in the chamber are individually controlled, so that the selenium vapor pressure of an inner space of the chamber does not exceed a
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: March 31, 2015
    Assignee: Semics Inc.
    Inventor: Seong Hoon Song
  • Patent number: 8975715
    Abstract: A photodetector includes a substrate and an insulating arrangement formed in the substrate. The insulating arrangement electrically insulates a confined region of the substrate. The confined region is configured to generate free charge carriers in response to an irradiation. The photodetector further includes a read-out electrode arrangement configured to provide a photocurrent formed by at least a portion of the free charge carriers that are generated in response to the irradiation. The photodetector also includes a biasing electrode arrangement that is electrically insulated against the confined region by means of the insulating arrangement. The biasing electrode arrangement is configured to cause an influence on a spatial charge carrier distribution within the confined region so that fewer of the free charge carriers recombine at boundaries of the confined region compared to an unbiased state.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: March 10, 2015
    Assignee: Infineon Technologies AG
    Inventor: Thoralf Kautzsch
  • Patent number: 8975511
    Abstract: A photovoltaic device includes a substrate, a first electrode, a second electrode, and an active layer between the first electrode and the second electrode. The active layer comprises a polyarylamine biscarbonate ester of Formula (I): wherein Ar1, Ar2, Ar3, Ar4, R, m, y, and n are as described herein. The photovoltaic device can be fabricated in an ambient environment and does not need significant processing.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: March 10, 2015
    Assignee: Xerox Corporation
    Inventors: Liang-Bih Lin, George Cunha Cardoso, Amanda Elizabeth Preske, Krishna Balantrapu
  • Patent number: 8952371
    Abstract: An organic EL element comprises: a substrate; a first electrode formed at one surface side of the substrate; a second electrode opposing the first electrode; and an organic EL layer located between the first and second electrodes. In the organic EL element, the second electrode is a transparent electrode, and the first electrode is a reflecting electrode. The organic EL element is a top-emission type. The first electrode comprises a plurality of nanometer-size (nanometer-order) columnar structures formed on the above-mentioned one surface of the substrate, and each of the plurality of columnar structures has a metallic surface as the outermost surface.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: February 10, 2015
    Assignees: Panasonic Corporation, Kyushu University, National University Corporation, LINTEC Corporation
    Inventors: Manabu Nakata, Chihaya Adachi, Yasukazu Nakata
  • Patent number: 8936970
    Abstract: A light-emitting structure comprises a semiconductor light-emitting element which includes a first connection point and a second connection point. The light-emitting structure further includes a first electrode electrically connected to the first connection point, and a second electrode electrically connected the second connection point. The first electrode and the second electrode can form a concave on which the semiconductor light-emitting element is located.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: January 20, 2015
    Assignee: Epistar Corporation
    Inventor: Chia-Liang Hsu
  • Patent number: 8933458
    Abstract: A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: January 13, 2015
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Jack Kavalieros, Brian S. Doyle, Uday Shah, Suman Datta, Amlan Majumdar, Robert S. Chau
  • Patent number: 8921856
    Abstract: A TFT-PIN array substrate and an assembly structure for a flat-panel x-ray detector are provided to overcome the problem that the conventional scintillator substrate and TFT-PIN array substrate are neither penetrated by UV-light nor assembled by UV curable LOCA. The metal layer of the PIN photodiode of the TFT-PIN array substrate is perforated to have at least one hole, whereby UV-light can pass through the TFT-PIN array substrate to cure UV curable LOCA. Therefore, UV curable LOCA can be used as an adhesive layer in the assembly structure of a scintillator substrate and a TFT-PIN array substrate to promote the detective quantum efficiency and image quality of a flat-panel X-Ray detector.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: December 30, 2014
    Assignee: National Chiao Tung University
    Inventors: Pao-Yun Tang, Shu-Lin Ho, Kei-Hsiung Yang
  • Patent number: 8901696
    Abstract: A solid-state imaging device includes: photoelectric conversion units disposed in the form of matrix in an imaging region and a peripheral region around the imaging region; transfer electrodes provided on a side of the photoelectric conversion units arranged in the vertical direction of the matrix; and first-layer wirings and second-layer wirings in a multi-layer wiring structure disposed to connect the transfer electrodes in the horizontal direction of the matrix, wherein the first-layer wirings and the second-layer wirings are provided as light-shielding patterns for covering the photoelectric conversion units in the peripheral region.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: December 2, 2014
    Assignee: Sony Corporation
    Inventors: Masashi Takami, Ryoma Yoshinaga, Akira Furukawa
  • Patent number: 8894887
    Abstract: Photovoltaic cells comprising an active layer comprising, as p-type material, conjugated polymers such as polythiophene and regioregular polythiophene, and as n-type material at least one fullerene derivative. The fullerene derivative can be C60, C70, or C84. The fullerene also can be functionalized with indene groups. Improved efficiency can be achieved.
    Type: Grant
    Filed: April 10, 2013
    Date of Patent: November 25, 2014
    Assignees: Solvay USA, Inc., Nano-C, Inc.
    Inventors: Darin W. Laird, Reza Stegamat, Henning Richter, Victor Vejins, Lawrence T. Scott, Thomas A. Lada, II
  • Patent number: 8883545
    Abstract: The invention relates to the production of solar panels which comprise solar cells connected to one another. In this case, various layers are stacked onto one another, such as a film layer, bonding agent, insulating film, solar cells and a support layer. Combining all these layers to form the final panel is carried out on a carrier which stabilizes and supports the stack while it is conveyed past the various treatment stations. The turning over of the stack can also be carried out in a reliable manner by means of such a carrier without shifts between the various components with respect to one another occurring.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: November 11, 2014
    Assignee: Eurotron B.V.
    Inventors: Jan Bakker, Abraham Jan Verschoor, Simon Den Hartigh
  • Patent number: 8878337
    Abstract: A method and integrated circuit structure for mitigating metal gate dishing resulting from chemical mechanical polishing. The integrated circuit structure comprises a first area comprising at least one first type device; a second area comprising at least one second type device; a third area comprising at least one capacitor having an uppermost layer of polysilicon, where the capacitor area is greater than a sum of the first and second areas. The method utilizes the polysilicon of the capacitor to mitigate metal gate dishing of a metal gate of at least one device.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: November 4, 2014
    Assignee: Xilinx, Inc.
    Inventors: Hong-Tsz Pan, Yun Wu, Shuxian Wu, Qi Lin, Bang-Thu Nguyen
  • Patent number: 8853519
    Abstract: In order to achieve a thermoelectric transducer exhibiting a higher conversion efficiency and an electronic apparatus including such a thermoelectric transducer, a thermoelectric conversion device is provided, including a semiconductor stacked structure including semiconductor layers stacked with each other, the semiconductor layers being made from different semiconductor materials, in which a material and a composition of each semiconductor layer in the semiconductor stacked structure are selected so as to avoid conduction-band or valence-band discontinuity.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: October 7, 2014
    Assignee: Fujitsu Limited
    Inventor: Taisuke Iwai
  • Patent number: 8847202
    Abstract: A dual-band infrared detector structure based on Type-II superlattices (T2SL) has been developed and experimentally validated. The structure according to the principles of the present invention is designed for a single Indium bump architecture and utilizes a T2SL barrier design that omits the traditional p-n junction region. The barrier design comprises multiple periods where each period comprises multiple monolayers doped P type. By selecting the composition, number of monolayers per period and number of periods, a transition region is created in the conduction band between a first absorber layer and a second absorber layer that allows operation at low biases (<100 mV for both bands) and exhibits a dark current density in the longer wavelength band comparable to that obtained with single-color detectors.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: September 30, 2014
    Assignee: HRL Laboratories, LLC
    Inventors: Brett Z. Nosho, Rajesh D. Rajavel, Hasan Sharifi, Sevag Terterian
  • Patent number: 8835991
    Abstract: There is provided a solid-state image pickup device including a semiconductor substrate, and a plurality of pixel portions that are provided on the semiconductor substrate. Each of the pixel portions includes a photoelectric converting unit that generates a charge on the basis of incident light, a memory unit that accumulates the charge generated by the photoelectric converting unit, a light shielding portion that shields at least the memory unit from light, a digging portion that digs into the semiconductor substrate between the photoelectric converting unit and the memory unit and is formed of a light shielding material, and a transmitting unit that transmits the charge from the photoelectric converting unit to the memory unit, by forming a channel for transmission in the digging portion.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: September 16, 2014
    Assignee: Sony Corporation
    Inventor: Shinichi Arakawa
  • Patent number: 8836070
    Abstract: A photo diode includes an intrinsic region on a substrate, a P+ doping region in a first portion of the intrinsic region, and an oxide semiconductor region. The oxide semiconductor region is spaced apart from the P+ doping region on a second portion of the intrinsic region and the second portion of the intrinsic region is different from the first portion of the intrinsic region.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: September 16, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Won-Kyu Lee, Jae-Beom Choi, Jae-Hwan Oh, Young-Jin Chang, Seong-Hyun Jin
  • Patent number: 8822256
    Abstract: A method for fabricating infrared sensors is disclosed. a chalcogenide layer is initially deposited on a substrate. A group of vias is then formed within the chalcogenide layer. After the vias have been converted to a group of studs, a vanadium oxide layer is deposited on the chalcogenide layer covering the studs. Next, the vanadium oxide layer is separated into multiple vanadium oxide membranes. After the chalcogenide layer has been removed, each of the vanadium oxide membranes is allowed to be freestanding while only supported by a corresponding one of the studs. The vanadium oxide membranes will be used as infrared sensors.
    Type: Grant
    Filed: April 4, 2013
    Date of Patent: September 2, 2014
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Chi-Hua Yang, David Sargent
  • Patent number: 8823012
    Abstract: Enhancement-mode GaN devices having a gate spacer, a gate metal material and a gate compound that are self-aligned, and a methods of forming the same. The materials are patterned and etched using a single photo mask, which reduces manufacturing costs. An interface of the gate spacer and the gate compound has lower leakage than the interface of a dielectric film and the gate compound, thereby reducing gate leakage. In addition, an ohmic contact metal layer is used as a field plate to relieve the electric field at a doped III-V gate compound corner towards the drain contact, which leads to lower gate leakage current and improved gate reliability.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: September 2, 2014
    Assignee: Efficient Power Conversion Corporation
    Inventors: Alexander Lidow, Robert Beach, Alana Nakata, Jianjun Cao, Guang Yuan Zhao, Robert Strittmatter, Fang Chang Liu
  • Patent number: 8815124
    Abstract: Photovoltaic cells comprising an active layer comprising, as p-type material, conjugated polymers such as polythiophene and regioregular polythiophene, and as n-type material at least one fullerene derivative. The fullerene derivative can be C60, C70, or C84. The fullerene also can be functionalized with indene groups. Improved efficiency can be achieved.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: August 26, 2014
    Assignees: Solvay USA, Inc., Nano-C, Inc.
    Inventors: Darin W. Laird, Reza Stegamat, Henning Richter, Viktor Vejins, Larry Scott, Thomas A. Lada, Malika Daadi
  • Patent number: 8816457
    Abstract: The present disclosure provides various embodiments of an image sensor device. An exemplary image sensor device includes an image sensing region disposed in a substrate; a multilayer interconnection structure disposed over the substrate; and a color filter formed in the multilayer interconnection structure and aligned with the image sensing region. The color filter has a length and a width, where the length is greater than the width.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: August 26, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jyh-Ming Hung, Jen-Cheng Liu, Dun-Nian Yaung, Chun-Chieh Chuang
  • Patent number: 8809925
    Abstract: An image sensor pixel includes a photosensitive element, a floating diffusion (“FD”) region, and a transfer device. The photosensitive element is disposed in a substrate layer for accumulating an image charge in response to light. The FD region is disposed in the substrate layer to receive the image charge from the photosensitive element. The transfer device is disposed between the photosensitive element and the FD region to selectively transfer the image charge from the photosensitive element to the FD region. The transfer device includes a gate, a buried channel dopant region and a surface channel region. The gate is disposed between the photosensitive element and the FD region. The buried channel dopant region is disposed adjacent to the FD region and underneath the gate. The surface channel region is disposed between the buried channel dopant region and the photosensitive element and disposed underneath the gate.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: August 19, 2014
    Assignee: OmniVision Technologies, Inc.
    Inventors: Gang Chen, Hsin-Chih Tai, Duli Mao, Zhenhong Fu
  • Patent number: 8809983
    Abstract: A semiconductor device includes: a first semiconductor chip; and a second semiconductor chip that is stacked on the first semiconductor chip. The first semiconductor chip includes a first wiring portion of which a side surface is exposed at a side portion of the first semiconductor chip. The second semiconductor chip includes a second wiring portion of which a side surface is exposed at a side portion of the second semiconductor chip. The respective side surfaces of the first wiring portion and the second wiring portion, which are exposed at the side portions of the first semiconductor chip and the second semiconductor chip, are covered by a conductive layer, and the first wiring portion and the second wiring portion are electrically connected to each other through the conductive layer.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: August 19, 2014
    Assignee: Sony Corporation
    Inventors: Ikuo Yoshihara, Taku Umebayashi, Hiroshi Takahashi, Hironobu Yoshida
  • Patent number: 8809921
    Abstract: A solid-state imaging apparatus includes a plurality of pixels each including a photoelectric conversion unit and pixel transistors, which are formed on a semiconductor substrate; a floating diffusion unit in the pixel; a first-conductivity-type ion implantation area for surface pinning, which is formed over the surface on the side of the photoelectric conversion unit and the surface of the semiconductor substrate; and a second-conductivity-type ion implantation area for forming an overflow path serving as an overflow path for the floating diffusion unit, the second-conductivity-type ion implantation area being formed below the entire area of the first-conductivity-type ion implantation area. An overflow barrier is formed using the second-conductivity-type ion implantation area. A charge storage area is formed using an area in which the second-conductivity-type semiconductor area and the second-conductivity-type ion implantation area superpose each other.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: August 19, 2014
    Assignee: Sony Corporation
    Inventors: Akihiro Yamada, Atsuhiko Yamamoto, Hideo Kido
  • Patent number: 8803211
    Abstract: A solid-state imaging device includes an array of pixels, each pixel includes: a pixel electrode; an organic layer; a counter electrode; a sealing layer; a color filter; a readout circuit; and a light-collecting unit as defined herein, the photoelectric layer contains an organic p type semiconductor and an organic n type semiconductor, the organic layer further includes a charge blocking layer as defined herein, an ionization potential of the charge blocking layer and an electron affinity of the organic n type semiconductor in the photoelectric layer has a difference of at least 1 eV, and the sealing layer includes a first sealing sublayer formed by atomic layer deposition and a second sealing sublayer formed by physical vapor deposition and containing one of a metal oxide, a metal nitride, and a metal oxynitride.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: August 12, 2014
    Assignee: FUJIFILM Corporation
    Inventors: Toshihiro Nakatani, Takashi Goto, Yoshiki Maehara, Hideyuki Suzuki
  • Patent number: 8802478
    Abstract: Manufacturing a semiconductor device includes preparing a structure including a semiconductor substrate having a first region and a second region, a first insulating film arranged on the first region, a second insulating film arranged on the first insulating film, a third insulating film arranged on the second insulating film, a fourth insulating film arranged on the second region, a fifth insulating film arranged on the fourth insulating film, and a sixth insulating film arranged on the fifth insulating film, etching the second insulating film and the first insulating film under different etching conditions after etching the third insulating film, and continuously etching the fifth insulating film and the fourth insulating film under the same etching conditions after etching the sixth insulating film.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: August 12, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Aiko Kato, Takehito Okabe
  • Patent number: 8796061
    Abstract: Solar cells are packaged by placing the solar cells between sheets of encapsulants. The encapsulants are exposed to ultraviolet (UV) light to cure the encapsulants and bond the encapsulants together to encapsulate the solar cells. The UV curing steps may be performed to bond one of the encapsulants to a transparent top cover and the solar cells, and to bond the other encapsulant to the solar cells and a backsheet. A protective package that includes the transparent top cover, encapsulated solar cells, and the backsheet is then optionally mounted on a frame.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: August 5, 2014
    Assignee: SunPower Corporation
    Inventor: Gabriela Bunea
  • Patent number: 8791465
    Abstract: A compound semiconductor device includes a compound semiconductor laminated structure, a passivation film formed on the compound semiconductor laminated structure and having a through-hole, and a gate electrode formed on the passivation film so as to plug the through-hole. A grain boundary between different crystalline orientations is formed in the gate electrode, and a starting point of the grain boundary is located apart from the through-hole on a flat surface of the passivation film.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: July 29, 2014
    Assignee: Fujitsu Limited
    Inventors: Naoya Okamoto, Kozo Makiyama, Toshihiro Ohki, Yuichi Minoura, Shirou Ozaki, Toyoo Miyajima
  • Patent number: 8785993
    Abstract: A solid-state imaging element includes a pixel having a photoelectric conversion section and a side pinning layer. The photoelectric conversion section is formed in a semiconductor substrate. The side pinning layer is formed on a side of the photoelectric conversion section. The side pinning layer is formed by performing ion implantation in a state of a trench being open, the trench being formed in a part on a side of a region in which the photoelectric conversion section is formed.
    Type: Grant
    Filed: August 1, 2012
    Date of Patent: July 22, 2014
    Assignee: Sony Corporation
    Inventor: Takashi Abe
  • Patent number: 8779532
    Abstract: Backside recesses in a base member host components, such as sensors or circuits, to allow closer proximity and efficient use of the surface space and internal volume of the base member. Recesses may include covers, caps, filters and lenses, and may be in communication with circuits on the frontside of the base member, or with circuits on an active backside cap. An array of recessed components may a form complete, compact sensor system.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: July 15, 2014
    Assignee: Analog Devices, Inc.
    Inventors: Alan J. O'Donnell, Michael J. Cusack, Rigan F. McGeehan, Garrett A. Griffin
  • Patent number: 8772883
    Abstract: A method for producing a sealed cavity, including: a) producing a sacrificial layer on a substrate; b) producing a cover layer covering at least the sacrificial layer and a portion of the face of the substrate not covered by the sacrificial layer, the cover layer including lateral flanks forming, with the substrate, an angle of less than 90°; c) producing a hole through one of the lateral flanks of the cover layer such that a maximum distance between the substrate and an edge of the hole is less than approximately 3 ?m, the hole crossing a portion of the cover layer deposited on a portion of the substrate not covered by the sacrificial layer; d) eliminating the sacrificial layer through the hole, forming the cavity; and e) depositing at least one material plugging the hole in a sealed fashion.
    Type: Grant
    Filed: July 6, 2010
    Date of Patent: July 8, 2014
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Jean-Louis Pornin, Fabrice Jacquet
  • Patent number: 8772919
    Abstract: The invention provides a chip package and a fabrication method thereof. In one embodiment, the chip package includes: a substrate having a semiconductor device and a conductive pad thereon; an insulator ring filling a trench formed in the substrate, wherein the insulator ring surrounds an intermediate layer below the conductive pad; and a conductive layer disposed below a backside of the substrate and electrically connected to the conductive pad.
    Type: Grant
    Filed: April 2, 2010
    Date of Patent: July 8, 2014
    Inventors: Wen-Cheng Chien, Wen-Ken Huang, Chien-Hung Liu, Joey Lai
  • Patent number: 8753915
    Abstract: The invention relates to the production of solar panels which comprise solar cells connected to one another. In this case, various layers are stacked onto one another, such as a film layer, bonding agent, insulating film, solar cells and a support layer. Combining all these layers to form the final panel is carried out on a carrier which stabilizes and supports the stack while it is conveyed past the various treatment stations. The turning over of the stack can also be carried out in a reliable manner by means of such a carrier without shifts between the various components with respect to one another occurring.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: June 17, 2014
    Assignee: Eurotron B.V.
    Inventors: Jan Bakker, Abraham Jan Verschoor, Simon Den Hartigh
  • Patent number: 8742522
    Abstract: A method of making a semiconductor radiation detector wherein the metal layers which serve as the cathode and anode electrodes are recessed from the designated prospective dice lines which define the total upper and lower surface areas for each detector such that the dicing blade will not directly engage the metal during dicing and therefore prevent metal from intruding upon (smearing) the vertical side walls of the detector substrate.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: June 3, 2014
    Assignee: eV Products, Inc.
    Inventors: Handong Li, Michael Prokesch, John F. Eger
  • Patent number: 8736009
    Abstract: The image sensor includes a substrate, an insulating structure formed on a first surface of the substrate and including a first metal wiring layer exposed by a contact hole penetrating the substrate, a conductive spacer formed on sidewalls of the contact hole and electrically connected to the first metal wiring layer, and a pad formed on a second surface of the substrate and electrically connected to the first metal wiring layer.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 27, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung Jun Park, Yong Woo Lee, Chang Rok Moon
  • Patent number: 8735946
    Abstract: Embodiments of the invention relate to substrates comprising a base wafer, an insulating layer and a top semiconductor layer, wherein the insulating layer comprises at least a zone wherein a density of charges is in absolute value higher than 1010 charges/cm2. The invention also relates to processes for making such substrates.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: May 27, 2014
    Assignee: Soitec
    Inventors: Mohamad A Shaheen, Frederic Allibert, Gweltaz Gaudin, Fabrice Lallement, Didier Landru, Karine Landry, Carlos Mazure
  • Patent number: 8723161
    Abstract: A two-color detector includes a first absorber layer. The first absorber layer exhibits a first valence band energy characterized by a first valence band energy function. A barrier layer adjoins the first absorber layer at a first interface. The barrier layer exhibits a second valence band energy characterized by a second valence band energy function. The barrier layer also adjoins a second absorber layer at a second interface. The second absorber layer exhibits a third valence band energy characterized by a third valence band energy function. The first and second valence band energy functions are substantially functionally or physically continuous at the first interface and the second and third valence band energy functions are substantially functionally or physically continuous at the second interface.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: May 13, 2014
    Assignee: Sandia Corporation
    Inventors: John F. Klem, Jin K. Kim
  • Patent number: 8704282
    Abstract: A method for forming a back-side illuminated image sensor from a semiconductor substrate, including the steps of: a) thinning the substrate from its rear surface; b) depositing, on the rear surface of the thinned substrate, an amorphous silicon layer of same conductivity type as the substrate but of higher doping level; and c) annealing at a temperature enabling to recrystallized the amorphous silicon to stabilize it.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: April 22, 2014
    Assignees: STMicroelectronics S.A., STMicroelectronics (Crolles 2) SAS
    Inventors: Michel Marty, François Roy, Jens Prima
  • Publication number: 20140103410
    Abstract: An image sensor pixel includes a photosensitive element, a floating diffusion (“FD”) region, and a transfer device. The photosensitive element is disposed in a substrate layer for accumulating an image charge in response to light. The FD region is dispose in the substrate layer to receive the image charge from the photosensitive element. The transfer device is disposed between the photosensitive element and the FD region to selectively transfer the image charge from the photosensitive element to the FD region. The transfer device includes a gate, a buried channel dopant region and a surface channel region. The gate is disposed between the photosensitive element and the FD region. The buried channel dopant region is disposed adjacent to the FD region and underneath the gate. The surface channel region is disposed between the buried channel dopant region and the photosensitive element and disposed underneath the gate.
    Type: Application
    Filed: October 11, 2012
    Publication date: April 17, 2014
    Applicant: OMNIVISION TECHNOLOGIES, INC.
    Inventors: Gang Chen, Hsin-Chih Tai, Duli Mao, Zhenhong Fu
  • Patent number: 8697988
    Abstract: Photovoltaic cells comprising an active layer comprising, as p-type material, conjugated polymers such as polythiophene and regioregular polythiophene, and as n-type material at least one fullerene derivative. The fullerene derivative can be C60, C70, or C84. The fullerene also can be functionalized with indene groups. Improved efficiency can be achieved.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: April 15, 2014
    Assignees: Plextronics, Inc., Nano-C, Inc.
    Inventors: Darin W. Laird, Henning Richter, Viktor Vejins, Larry Scott, Thomas A. Lada, Malika Daadi
  • Patent number: 8697481
    Abstract: Multijunction solar cells having at least four subcells are disclosed, in which at least one of the subcells comprises a base layer formed of an alloy of one or more elements from group III on the periodic table, nitrogen, arsenic, and at least one element selected from the group consisting of Sb and Bi, and each of the subcells is substantially lattice matched. Methods of manufacturing solar cells and photovoltaic systems comprising at least one of the multijunction solar cells are also disclosed.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: April 15, 2014
    Assignee: Solar Junction Corporation
    Inventors: Rebecca Elizabeth Jones-Albertus, Pranob Misra, Michael J. Sheldon, Homan B. Yuen, Ting Liu, Daniel Derkacs, Vijit Sabnis, Micahel West Wiemer, Ferran Suarez
  • Patent number: 8698264
    Abstract: A photoelectric conversion module includes: a substrate having a light transmitting property and having a mounting surface; a photoelectric conversion element mounted on the mounting surface of the substrate; a cover member fixed to the substrate via a solder layer constituted by solder and forming, cooperatively with the substrate, an airtight chamber housing the photoelectric conversion element; and a solder adsorbing film provided near an area fixed to the substrate by the solder layer, in a surface, of the cover member, facing the mounting surface, the solder having an adhesive property to the solder adsorbing film.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: April 15, 2014
    Assignee: Hitachi Cable, Ltd.
    Inventors: Kouki Hirano, Hiroki Yasuda, Yoshinori Sunaga, Shohei Hata
  • Publication number: 20140091374
    Abstract: A method of forming an integrated photonic semiconductor structure having a photonic device and a CMOS device may include depositing a first silicon nitride layer having a first stress property over the photonic device, depositing an oxide layer having a stress property over the deposited first silicon nitride layer, and depositing a second silicon nitride layer having a second stress property over the oxide layer. The deposited first silicon nitride layer, the oxide layer, and the second silicon nitride layer encapsulate the photonic device.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Solomon Assefa, Tymon Barwicz, Swetha Kamlapurkar, Marwan H. Khater, Steven M. Shank, Yurii A. Vlasov
  • Publication number: 20140084301
    Abstract: A radiation dosimeter includes a semiconductor substrate and a buried insulator layer disposed on the semiconductor substrate. The buried insulator layer has a plurality of charge traps. A semiconductor layer is disposed on the buried insulator layer. The semiconductor layer has an emitter, an intrinsic base, and a collector laterally arranged with respect to one another. In response to radiation exposure by the radiation dosimeter, positive charges are trapped in the plurality of charge traps in the buried insulator layer, the amount of positive charge trapped being used to determine the amount of radiation exposure.
    Type: Application
    Filed: September 24, 2012
    Publication date: March 27, 2014
    Applicant: International Business Machines Corporation
    Inventors: Jin Cai, Effendi Leobandung, Tak H. Ning, Jeng-Bang Yau
  • Patent number: 8680636
    Abstract: A solid-state imaging apparatus is provided. A solid-state imaging device chip is enclosed in a package having an optically transparent member. An adhesive layer is formed on an internal surface of the package, and a penetration hole is formed in a bottom part of the package to communicate with an open space in the package.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: March 25, 2014
    Assignee: Sony Corporation
    Inventors: Atsushi Yajima, Tokiko Katayama
  • Patent number: 8674406
    Abstract: A strain-balanced photodetector is provided for detecting infrared light at an extended cutoff wavelength in the range of 4.5 ?m or more. An InAsSb absorber layer has an Sb content is grown in a lattice-mismatched condition to a GaSb substrate, and a plurality of GaAs strain-compensating layers are interspersed within the absorber layer to balance the strain of the absorber layer due to the lattice mismatch. The strain-compensation layers allow the absorber to achieve a thickness exhibiting sufficient absorption efficiency while extending the cutoff wavelength beyond that possible in a lattice-matched state. Additionally, the strain-compensation layers are sufficiently thin to be substantially quantum-mechanically transparent such that they do not substantially affect the transmission efficiency of the absorber. The photodetector is preferably formed as a majority carrier filter photodetector exhibiting minimal dark current, and may be provided individually or in a focal plane array.
    Type: Grant
    Filed: July 15, 2010
    Date of Patent: March 18, 2014
    Assignee: Lockheed Martin Corp.
    Inventors: Jeffrey W. Scott, George Paloczi