Characterized By Semiconductor Body (epo) Patents (Class 257/E31.002)
  • Patent number: 9029969
    Abstract: There is provided an imaging element including a transmission channel region provided in an optical black pixel region shielded from light from an outside of a semiconductor substrate by a light shielding film, for transmitting a charge existing inside the semiconductor substrate of the optical black pixel region to an outside of the optical black pixel region.
    Type: Grant
    Filed: August 13, 2012
    Date of Patent: May 12, 2015
    Assignee: Sony Corporation
    Inventor: Suzunori Endo
  • Patent number: 8946839
    Abstract: An absorber is disclosed. The disclosed absorber contains a base layer, and a plurality of pillars disposed above the base layer and composed of material configured to absorb an incident light and generate minority electrical carriers and majority electrical carrier, wherein the height of the pillars is predetermined to provide a common pyramidal outline shared by the pillars in the plurality of pillars.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: February 3, 2015
    Assignee: HRL Laboratories, LLC
    Inventors: Daniel Yap, Rajesh D. Rajavel, Sarabjit Mehta, James H. Schaffner
  • Patent number: 8933458
    Abstract: A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: January 13, 2015
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Jack Kavalieros, Brian S. Doyle, Uday Shah, Suman Datta, Amlan Majumdar, Robert S. Chau
  • Patent number: 8860164
    Abstract: A light receiving element includes a core configured to propagate a signal light, a first semiconductor layer having a first conductivity type, the first semiconductor layer being configured to receive the signal light from the core along a first direction in which the core extends, an absorbing layer configured to absorb the signal light received by the first semiconductor layer, and a second semiconductor layer having a second conductivity type opposite to the first conductivity type.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: October 14, 2014
    Assignee: Fujitsu Limited
    Inventor: Kazumasa Takabayashi
  • Patent number: 8778708
    Abstract: There is provided a process for forming a layer of electroactive material having a substantially flat profile. The process includes: providing a workpiece having at least one active area; depositing a liquid composition including the electroactive material onto the workpiece in the active area, to form a wet layer; treating the wet layer on the workpiece at a controlled temperature in the range of ?25 to 80° C. and under a vacuum in the range of 10?6 to 1,000 Torr, for a first period of 1-100 minutes, to form a partially dried layer; heating the partially dried layer to a temperature above 100° C. for a second period of 1-50 minutes to form a dried layer.
    Type: Grant
    Filed: March 8, 2010
    Date of Patent: July 15, 2014
    Assignee: E I du Pont de Nemours and Company
    Inventors: Reid John Chesterfield, Justin Butler, Paul Anthony Sant
  • Patent number: 8729656
    Abstract: A germanium semiconductor radiation detector contact made of yttrium metal. A thin (˜1000 ?) deposited layer of yttrium metal forms a thin hole-barrier and/or electron-barrier contact on both p- and n-type germanium semiconductor radiation detectors. Yttrium contacts provide a sufficiently high hole barrier to prevent measurable contact leakage current below ˜120 K. The yttrium contacts can be conveniently segmented into multiple electrically independent electrodes having inter-electrode resistances greater than 10 G?. Germanium semiconductor radiation detector diodes fabricated with yttrium contacts provide good gamma-ray spectroscopy data.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: May 20, 2014
    Inventors: Ethan Hull, Richard Pehl, Bruce Suttle, James Lathrop
  • Patent number: 8716834
    Abstract: A semiconductor device that can prevent reduction in the amplitude of electromagnetic waves transmitted from a reader/writer, and can prevent heating of an element forming layer due to a change in a magnetic field. The semiconductor device of the invention has an element forming layer formed over a substrate, and an antenna connected to the element forming layer. The element forming layer has at least wires such as a power supply wire and a ground wire that are arranged in a non-circular shape. The element forming layer and the antenna may be provided so as to overlap each other at least partially. The antenna may be provided above or below the element forming layer.
    Type: Grant
    Filed: December 21, 2005
    Date of Patent: May 6, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kiyoshi Kato, Yoshitaka Moriya
  • Publication number: 20140120647
    Abstract: Techniques for manufacturing a device are disclosed. In accordance with one exemplary embodiment, the technique may be realized as a method for forming a solar cell. The method may comprise: implanting p-type dopants into a substrate via a blanket ion implantation process; implanting n-type dopants into the substrate via the blanket ion implantation process; and performing a first annealing process to form the p-type region and performing a second annealing process to form a second n-type region.
    Type: Application
    Filed: October 26, 2012
    Publication date: May 1, 2014
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Nicholas P.T. Bateman, Deepak A. Ramappa
  • Patent number: 8692112
    Abstract: An organic thin film solar cell comprises: positive and negative electrode layers; and an organic thin film layer disposed between the positive and negative electrode layers, the organic thin film layer including: a mixture of at least a first organic compound having a light-absorbing dye moiety and an electron-accepting second organic compound, in which the organic thin film layer further includes inorganic nanoparticles.
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: April 8, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Naoki Yoshimoto, Hiroto Naito
  • Patent number: 8647909
    Abstract: An array of radiation sensors or detectors is integrated within a three-dimensional semiconductor IC. The sensor array is located relatively close to the device layer of a circuit (e.g., a microprocessor) to be protected from the adverse effects of the ionizing radiation particles. As such, the location where the radiation particles intersect the device layer can be calculated with coarse precision (e.g., to within 10 s of microns).
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: February 11, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ethan H. Cannon, Michael J. Hauser, Timothy D. Sullivan
  • Patent number: 8647897
    Abstract: A method for producing and depositing air-stable, easily decomposable, vulcanized ink on any of a wide range of substrates is disclosed. The ink enables high-volume production of optoelectronic and/or electronic devices using scalable production methods, such as roll-to-roll transfer, fast rolling processes, and the like.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: February 11, 2014
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Benjamin D. Weil, Stephen T. Connor, Yi Cui
  • Publication number: 20140004651
    Abstract: A method for forming a photovoltaic device includes depositing one or more layers of a photovoltaic stack on a substrate by employing a high deposition rate plasma enhanced chemical vapor deposition (HDR PECVD) process. Contacts are formed on the photovoltaic stack to provide a photovoltaic cell. Annealing is performed on the photovoltaic cell at a temperature and duration configured to improve overall performance.
    Type: Application
    Filed: June 28, 2012
    Publication date: January 2, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Keith E. Fogel, Augustin J. Hong, Jeehwan Kim, Devendra K. Sadana
  • Patent number: 8609453
    Abstract: A reusable substrate and method for forming single crystal silicon solar cells are described. A method of forming a photovoltaic cell includes forming an intermediate layer on a monocrystalline silicon substrate, forming a monocrystalline silicon layer on the intermediate layer, and forming electrical features in the monocrystalline silicon layer. The method further includes forming openings in the monocrystalline silicon layer, and detaching the monocrystalline silicon layer from the substrate by selectively etching the intermediate layer through the openings.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: December 17, 2013
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak, Jed H. Rankin
  • Patent number: 8525298
    Abstract: A phase change memory device having a 3-D stack structure and a fabrication method for making the same are presented. The phase change memory device includes a semiconductor substrate, a word line structure and one or more phase change structures. The word line structure extends in one first direction on the semiconductor substrate. The one or more phase change structures extend mutually in parallel from one sidewall of the word line structure. The, the memory cell including a switching device, one side of the switching device contacted with the one sidewall of the word line structure, a heating electrode formed on the other side portion of the switching device, and a phase change pattern, one sidewall of the phase change pattern contacted with the heating electrode.
    Type: Grant
    Filed: May 19, 2010
    Date of Patent: September 3, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Ki Ho Yang
  • Patent number: 8525286
    Abstract: An integrated circuit device is provided. The integrated circuit device can include a substrate; a first radiation-sensing element disposed over a first portion of the substrate; and a second radiation-sensing element disposed over a second portion of the substrate. The first portion comprises a first radiation absorption characteristic, and the second portion comprises a second radiation absorption characteristic different from the first radiation absorption characteristic.
    Type: Grant
    Filed: August 6, 2009
    Date of Patent: September 3, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Hsuan Hsu, Chris Hsieh, Dun-Nian Yaung, Chung-Yi Yu
  • Patent number: 8513047
    Abstract: In accordance with the present invention, the dividing grooves 8 are formed so as not to be parallel to cleavage planes of the semiconductor substrate 1, and the semiconductor substrate 1 is bent along the dividing grooves 8, whereby the semiconductor substrate 1 is fractured along the dividing grooves 8.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: August 20, 2013
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hiroyuki Kannou, Masaki Shima
  • Publication number: 20130175431
    Abstract: A detector includes a substrate; two first regions, each first region having a linear shape, and the two first regions being separated from each other on the substrate and arranged in parallel; and a pixel region provided between the two first regions and including a plurality of pixels, the pixel region including a plurality of second regions perpendicular to the two first regions, each of the two first regions including a peripheral circuit portion, each of the plurality of second regions including a driver line, and a width of each of the plurality of second regions being equal to or less than a width of a single pixel.
    Type: Application
    Filed: August 7, 2012
    Publication date: July 11, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dae-kun YOON, Young KIM, Jae-chul PARK, Sang-wook HAN, Sun-il KIM, Chang-jung KIM, Jun-su LEE
  • Patent number: 8450823
    Abstract: Disclosed is an integrated circuit (100) comprising a substrate (110) carrying a plurality of light-sensitive elements (112) and a blazed grating (120) comprising a plurality of diffractive elements (122) for diffracting respective spectral components (123-125) of incident light (150) to respective light-sensitive elements (112), the blazed grating (120) comprising a stack of layers, at least some of these layers comprising first portions, e.g. metal portions (202, 222, 242) arranged such that each diffractive element (122) comprises a stepped profile of stacked first portions with a first portion in a higher layer laterally extending beyond a first portion in a lower layer of said stepped profile.
    Type: Grant
    Filed: September 12, 2009
    Date of Patent: May 28, 2013
    Assignee: NXP B.V.
    Inventors: Erwin Hijzen, Magali Lambert
  • Patent number: 8445312
    Abstract: A method of manufacturing a crystalline silicon solar cell, subsequently including: providing a crystalline silicon substrate having a first side and a second side opposite the first side; pre-diffusing Phosphorus into a first side of the substrate to render a Phosphorus diffused layer having an initial depth; blocking the first side of the substrate; exposing a second side of the substrate to a Boron diffusion source; heating the substrate for a certain period of time and to a certain temperature so as to diffuse Boron into the second side of the substrate and to simultaneously diffuse the Phosphorus further into the substrate.
    Type: Grant
    Filed: November 13, 2008
    Date of Patent: May 21, 2013
    Assignee: Stichting Energieonderzoek Centrum Nederland
    Inventors: Valentin Dan Mihailetchi, Yuji Komatsu
  • Publication number: 20130095597
    Abstract: A method of manufacturing a solar cell including providing a semiconductor substrate having a first conductivity type; performing a first deposition process that includes forming a first doping material layer having a second conductivity type different from the first conductivity type; performing a drive-in process that includes heating the substrate having the first doping material layer thereon; performing a second deposition process after performing the drive-in process and including forming a second doping material layer on the first doping material layer, wherein the second doping material layer has the second conductivity type; locally heating portions of the substrate, the first doping material layer, and the second doping material layer with a laser to form a contact layer at a first surface of the substrate; and forming a first electrode on the contact layer and a second electrode on a second surface of the substrate opposite to the first surface.
    Type: Application
    Filed: August 7, 2012
    Publication date: April 18, 2013
    Inventors: Sang-Jin Park, Min-Chul Song, Sung-Chan Park, Dong-Seop Kim, Won-Gyun Kim, Sang-Won Seo
  • Publication number: 20130084668
    Abstract: Apparatus for vapor deposition of a sublimated source material as a thin film on a photovoltaic module substrate is generally provided. The apparatus can include a deposition head; a distribution plate disposed below said distribution manifold and above an upper surface of a substrate transported through said apparatus and defining a pattern of passages therethrough; and, a carrying mechanism configured to transport the substrate in a machine direction under the distribution plate such that an upper surface of the substrate defines an arc in a cross-direction that is substantially perpendicular to the machine direction. Processes are also generally provided for vapor deposition of a sublimated source material to form thin film on a photovoltaic module substrate.
    Type: Application
    Filed: September 30, 2011
    Publication date: April 4, 2013
    Applicant: PRIMESTAR SOLAR, INC.
    Inventors: Fred Harper Seymour, Jeffrey Todd Knapp, Scott Daniel Feldman-Peabody, Robert Dwayne Gossman, Mark Jeffrey Pavol
  • Publication number: 20130076951
    Abstract: There is provided an imaging element including a transmission channel region provided in an optical black pixel region shielded from light from an outside of a semiconductor substrate by a light shielding film, for transmitting a charge existing inside the semiconductor substrate of the optical black pixel region to an outside of the optical black pixel region.
    Type: Application
    Filed: August 13, 2012
    Publication date: March 28, 2013
    Applicant: Sony Corporation
    Inventor: Suzunori ENDO
  • Publication number: 20130068936
    Abstract: A sub-mount having a photodiode region, includes a photodiode which has a first conductivity-type layer arranged in a surface portion of the sub-mount of the photodiode region to form a light-receiving surface and a second conductivity-type region arranged below the first conductivity-type layer and is configured to receive at the light-receiving surface a light emitted from a light-emitting element and convert the light into a photocurrent. A peak light-receiving wavelength at which the photocurrent of the photodiode becomes its maximum value is more than or equal to a minimum emission wavelength of the light-emitting element and less than or equal to a maximum emission wavelength of the light-emitting element.
    Type: Application
    Filed: September 13, 2012
    Publication date: March 21, 2013
    Applicant: ROHM CO., LTD.
    Inventor: Yoshiteru NAGAI
  • Patent number: 8399945
    Abstract: A semiconductor light detecting element includes: a semiconductor substrate; and a distributed Bragg reflector layer of a first conductivity type, an optical absorption layer, and a semiconductor layer of a second conductivity type, sequentially laminated on the semiconductor substrate. The distributed Bragg reflector layer includes first and second alternately laminated semiconductor layers with different band-gap wavelengths, sandwiching the wavelength of detected incident light. The sum of thicknesses a first and a second semiconductor layer is approximately one-half the wavelength of the incident light detected.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: March 19, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventors: Masaharu Nakaji, Ryota Takemura
  • Patent number: 8384196
    Abstract: Methods and structures are provided for formation of devices on substrates including, e.g., lattice-mismatched materials, by the use of aspect ratio trapping and epitaxial layer overgrowth. A method includes forming an opening in a masking layer disposed over a substrate that includes a first semiconductor material. A first layer, which includes a second semiconductor material lattice-mismatched to the first semiconductor material, is formed within the opening. The first layer has a thickness sufficient to extend above a top surface of the masking layer. A second layer, which includes the second semiconductor material, is formed on the first layer and over at least a portion of the masking layer. A vertical growth rate of the first layer is greater than a lateral growth rate of the first layer and a lateral growth rate of the second layer is greater than a vertical growth rate of the second layer.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: February 26, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zhiyuan Cheng, James Fiorenza, Jennifer M. Hydrick, Anthony J. Lochtefeld, Ji-Soo Park, Jie Bai, Jizhong Li
  • Patent number: 8383523
    Abstract: In a method for the treatment of silicon wafers in the production of solar cells, a treatment liquid is applied to the surface of the silicon wafers for the purpose of texturization thereof. The treatment liquid contains, as additive, ethyl hexanol or cyclohexanol in an amount ranging from 0.5% to 3%, by weight.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: February 26, 2013
    Assignee: Gebr. Schmid GmbH
    Inventor: Izaaryene Maher
  • Publication number: 20130044245
    Abstract: In a case when a structure of forming a p+ layer on a substrate rear surface side is employed in order to prevent dark current generation from the silicon boundary surface, various problems occur. According to this invention, an insulation film 39 is provided on a rear surface on a silicon substrate 31 and a transparent electrode 40 is further provided thereon, and by applying a negative voltage with respect to the potential of the silicon substrate 31 from a voltage supply source 41 to the insulation film 39 through the transparent electrode 40, positive holes are accumulated on a silicon boundary surface of the substrate rear surface side and a structure equivalent to a state in which a positive hole accumulation layer exists on aforesaid silicon boundary surface is to be created. Thus, various problems in the related art can be avoided.
    Type: Application
    Filed: October 19, 2012
    Publication date: February 21, 2013
    Applicant: SONY CORPORATION
    Inventor: SONY CORPORATION
  • Publication number: 20130037900
    Abstract: A solid-state imaging element includes a pixel having a photoelectric conversion section and a side pinning layer. The photoelectric conversion section is formed in a semiconductor substrate. The side pinning layer is formed on a side of the photoelectric conversion section. The side pinning layer is formed by performing ion implantation in a state of a trench being open, the trench being formed in a part on a side of a region in which the photoelectric conversion section is formed.
    Type: Application
    Filed: August 1, 2012
    Publication date: February 14, 2013
    Applicant: SONY CORPORATION
    Inventor: Takashi Abe
  • Publication number: 20130026366
    Abstract: A vertically stacked thermopile and an IR sensor using said stacked thermopiles are provided. The vertically stacked thermopile may include multiple thermocouples stacked vertically on one another. The thermocouples may be connected in series, parallel, or a combination of series and parallel. One or more vertically stacked thermopiles may be included in an IR sensor and the thermopiles may be connected in series, parallel, or a combination of series and parallel.
    Type: Application
    Filed: March 17, 2011
    Publication date: January 31, 2013
    Applicant: Excelitas Canada Inc.
    Inventors: Reiner Quad, Arthur Barlow, Yuan Hsi Chan, Michael Ersoni, Hermann Karagozoglu, Radu M. Marinescu
  • Publication number: 20130016258
    Abstract: Methods of optimizing the diameters of nanowire photodiode light sensors. The method includes comparing the response of nanowire photodiode pixels having predetermined diameters with standard spectral response curves and determining the difference between the spectral response of the photodiode pixels and the standard spectral response curves. Also included are nanowire photodiode light sensors with optimized nanowire diameters and methods of scene reconstruction.
    Type: Application
    Filed: September 17, 2012
    Publication date: January 17, 2013
    Applicant: ZENA TECHNOLOGIES, INC.
    Inventor: Munib WOBER
  • Publication number: 20130011954
    Abstract: A high power density photo-electronic and photo-voltaic material comprising a bio-inorganic nanophotoelectronic material with a photosynthetic reaction center protein encapsulated inside a multi-wall carbon nanotube or nanotube array. The array can be on an electrode. The photosynthetic reaction center protein can be immobilized on the electrode surface and the protein molecules can have the same orientation. A method of making a high power density photo-electronic and photo-voltaic material comprising the steps of immobilizing a bio-inorganic nanophotoelectronic material with a photosynthetic reaction center protein inside a carbon nanotube, wherein the immobilizing is by passive diffusion, wherein the immobilizing can include using an organic linker.
    Type: Application
    Filed: September 11, 2012
    Publication date: January 10, 2013
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Nikolai Lebedev, Scott A. Trammell, Stanislav Tsoi, Mark E. Twigg, Joel M. Schnur
  • Publication number: 20130000714
    Abstract: A paste composition contains an electrically conductive silver powder, one or more glass frits or fluxes, and a lithium compound dispersed in an organic medium. The paste is useful in forming an electrical contact on the front side of a solar cell device having an insulating layer. The lithium compound aids in establishing a low-resistance electrical contact between the front-side metallization and underlying semiconductor substrate during firing.
    Type: Application
    Filed: December 9, 2011
    Publication date: January 3, 2013
    Applicant: E.I. DU PONT DE NEMOURS AND COMPANY
    Inventors: STEVEN DALE ITTEL, Zhigang Rick Li, Kurt Richard Mikeska, Paul Douglas Vernooy
  • Publication number: 20120322192
    Abstract: An improved solar cell is disclosed. To create the internal p-n junction, one surface of the substrate is implanted with ions. After the implantation, the substrate is thermally treated. The thermal process distributes the dopant throughout the substrate, while repairing crystal damage caused by implantation. After the thermal process, residual crystal damage may remain, which adversely impacts solar cell efficiency. In order to further reduce the residual damage, the uppermost portion of the surface is then removed, thereby eliminating that portion of the substrate where most of the defects reside. The lower defect concentration reduces recombination and improves efficiency of the solar cell.
    Type: Application
    Filed: June 15, 2011
    Publication date: December 20, 2012
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: John Graff, Nicholas Bateman
  • Publication number: 20120313195
    Abstract: A semiconductor detector device, such as a PIN diode or silicon drift detector, including a substrate with an entrance window. The entrance window comprises a conductive layer, and an insulating layer disposed between the conductive layer and the substrate. The insulating layer and conductive layer cover a center portion of the surface of the substrate.
    Type: Application
    Filed: December 14, 2011
    Publication date: December 13, 2012
    Inventors: Keith W. Decker, Derek Hullinger, Mark Alan Davis
  • Patent number: 8319229
    Abstract: An optical semiconductor device is disclosed including an active region including an active layer and a diffraction grating having a ?/4 phase shift; passive waveguide regions each including a passive waveguide and a diffraction grating, disposed on the side of an emission facet and on the side of a rear facet sandwiching the active region between the passive waveguide regions, respectively; and an anti-reflection coating applied on the emission facet, wherein the passive waveguide region on the side of the emission facet has a length shorter than a length of the passive waveguide region on the side of the rear facet side.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: November 27, 2012
    Assignee: Fujitsu Limited
    Inventors: Tsuyoshi Yamamoto, Manabu Matsuda
  • Publication number: 20120295387
    Abstract: A method for producing a thin-film solar cell with a cell level integrated bypass diode includes forming at least first, second and third series-connected cells on a support, each cell being a laminated structure comprising a junction layer including semiconducting material of a first and second type, a front electrode formed of a transparent conductive oxide resistant to an etchant disposed in electrical contact with the semiconducting material of the first type, and a back electrode in electrical contact with the semiconducting material of the second type. A portion of both the back electrode and the junction layer are separated from a selected parent solar cell. Using the separated portion of the back electrode the semiconducting material of the second type of the separated portion of the junction layer is connected to the semiconducting material of the first type of any one chosen solar cell in the array.
    Type: Application
    Filed: November 16, 2011
    Publication date: November 22, 2012
    Applicant: E. I. DU PONT DE NEMOURS AND COMPANY
    Inventors: MEIJUN LU, Lap-Tak Andrew Cheng
  • Publication number: 20120295386
    Abstract: A stratified photodiode for high resolution CMOS image sensors implemented with STI technology is provided. The photodiode includes a semi-conductive layer of a first conductivity type, multiple doping regions of a second conductivity type, multiple doping regions of the first conductivity type, and a pinning layer. The multiple doping regions of the second conductivity type are formed to different depths in the semi-conductive layer. The multiple doping regions of the first conductivity type are disposed between the multiple doping regions of the second conductivity type and form multiple junction capacitances without full depletion. In particular, the stratified doping arrangement allows the photodiode to have a small size, high charge storage capacity, low dark current, and low operation voltages.
    Type: Application
    Filed: July 31, 2012
    Publication date: November 22, 2012
    Applicant: Intellectual Ventures II LLC (remove and reenter with front before filing)
    Inventor: Jaroslav Hynecek
  • Publication number: 20120295385
    Abstract: Embodiments of the present invention are directed to an image sensor having pixel transistors and peripheral transistors disposed in a silicon substrate. For some embodiments, a protective coating is disposed on the peripheral transistors and doped silicon is epitaxially grown on the substrate to form lightly-doped drain (LDD) areas for the pixel transistors. The protective oxide may be used to prevent epitaxial growth of silicon on the peripheral transistors during formation of the LDD areas of the pixel transistors.
    Type: Application
    Filed: July 26, 2012
    Publication date: November 22, 2012
    Applicant: OMNIVISION TECHNOLOGIES, INC.
    Inventors: Duli Mao, Hsin-Chih Tai, Howard E. Rhodes, Vincent Venezia, Yin Qian
  • Publication number: 20120288979
    Abstract: At least one exemplary embodiment is directed to a solid state image sensor including at least one antireflective layer and/or non rectangular shaped wiring layer cross section to reduce dark currents and 1/f noise.
    Type: Application
    Filed: July 23, 2012
    Publication date: November 15, 2012
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Toru Koizumi, Akira Okita, Tetsuya Itano, Sakae Hashimoto, Ryuichi Mishima
  • Publication number: 20120286144
    Abstract: A photodiode comprises a semiconductor material having a p-n junction, the p-n junction being located between a first doping region of a first doping type and a second doping region of a second doping type, the second doping region comprising a highly doped layer and a lightly doped layer. A photodiode further comprises a voltage source being capable to apply a variable voltage between the first doping region and the lightly doped layer of the second doping region in order to vary the expansion of a space charge zone of the p-n junction.
    Type: Application
    Filed: November 10, 2011
    Publication date: November 15, 2012
    Applicant: NaMLab GmbH
    Inventors: Juergen Holz, Andre Wachowiak, Stefan Slesazeck
  • Publication number: 20120276678
    Abstract: A solar cell includes a substrate layer and a plurality of nanowires grown outwardly from the substrate layer, at least two of the nanowires including a plurality of sub-cells. The solar cell also includes one or more light guiding layers formed of a transparent, light scattering material and filling the area between the plurality of nanowires.
    Type: Application
    Filed: June 28, 2012
    Publication date: November 1, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Siegfried F. Karg
  • Publication number: 20120273805
    Abstract: The invention relates to a liquid-phase method for the thermal production of silicon layers on a substrate, wherein at least one higher silicon that can be produced from at least one hydridosilane of the generic formula SiaH2a+2 (with a=3-10) being applied to a substrate and then being thermally converted to a layer that substantially consists of silicon, the thermal conversion of the higher silane proceeding at a temperature of 500-900° C. and a conversion time of ?5 minutes. The invention also relates to silicon layers producible according to said method and to their use.
    Type: Application
    Filed: November 10, 2010
    Publication date: November 1, 2012
    Applicant: Evonik Degussa GmbH
    Inventors: Stephan Wieber, Matthias Patz, Reinhard Carius, Torsten Bronger, Michael Cölle
  • Publication number: 20120256181
    Abstract: The invention discloses a power-generating module with solar cell and method for fabricating the same. The power-generating module includes a flexible substrate, a circuit and a solar cell. Both of the circuit and the solar cell are formed on the flexible substrate and are connected with each other, such that the solar cell is capable of providing the power needed by the circuit for operation.
    Type: Application
    Filed: June 10, 2011
    Publication date: October 11, 2012
    Inventors: Jia-Min SHIEH, Chang-Hong Shen, Wen-Hsien Huang, Bau-Tong Dai, Jung Y. Huang, Hao-Chung Kuo
  • Publication number: 20120244650
    Abstract: A method for producing and depositing air-stable, easily decomposable, vulcanized ink on any of a wide range of substrates is disclosed. The ink enables high-volume production of optoelectronic and/or electronic devices using scalable production methods, such as roll-to-roll transfer, fast rolling processes, and the like.
    Type: Application
    Filed: March 21, 2012
    Publication date: September 27, 2012
    Applicant: The Board of Turstees of the Leland Stanford Junior University
    Inventors: Benjamin D. Weil, Stephen T. Connor, Yi Cui
  • Publication number: 20120227794
    Abstract: Embodiments of the invention relate to methods of forming solar cell devices to reduce recombination losses and solar cell devices made by such methods, for example back contact solar cells, such as emitter-wrap-through (EWT) solar cells. The methods may include disposing an amount of impurities into a charge compensating region formed on a rear surface of a substrate and forming a rear surface passivation layer over at least a portion of the charge compensating region, wherein the amount of the impurities disposed in the charge compensating region is selected to compensate for an amount of charge formed in the rear surface passivation layer.
    Type: Application
    Filed: September 20, 2010
    Publication date: September 13, 2012
    Applicant: Applied Materials, Inc.
    Inventors: James M. Gee, Prabhat Kumar
  • Publication number: 20120228730
    Abstract: A plasma treatment or an ozone treatment is applied to the respective bonding surfaces of the single-crystal Si substrate in which the ion-implanted layer has been formed and the quartz substrate, and the substrates are bonded together. Then, a force of impact is applied to the bonded substrate to peel off a silicon thin film from the bulk portion of single-crystal silicon along the hydrogen ion-implanted layer, thereby obtaining an SOI substrate having an SOI layer on the quartz substrate. A concave portion, such as a hole or a micro-flow passage, is formed on a surface of the quartz substrate of the SOI substrate thus obtained, so that processes required for a DNA chip or a microfluidic chip are applied. A silicon semiconductor element for the analysis/evaluation of a sample attached/held to this concave portion is formed in the SOI layer.
    Type: Application
    Filed: May 21, 2012
    Publication date: September 13, 2012
    Applicant: Shin-Etsu Chemical Co., Ltd.
    Inventors: Shoji AKIYAMA, Yoshihiro Kubota, Atsuo Ito, Koichi Tanaka, Makoto Kawai, Yuuji Tobisaka
  • Patent number: 8258002
    Abstract: A phase change memory device resistant to stack pattern collapse is presented. The phase change memory device includes a silicon substrate, switching elements, heaters, stack patterns, bit lines and word lines. The silicon substrate has a plurality of active areas. The switching elements are connected to the active areas. The heaters are connected to the switching elements. The stack patterns are connected to the heaters. The bit lines are connected to the stack patterns. The word lines are connected to the active areas of the silicon substrate.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: September 4, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Heon Yong Chang
  • Patent number: 8253245
    Abstract: A communication device according to an embodiment includes an antenna transmitting/receiving a high frequency signal, a semiconductor chip having four corners and four sides processing the high frequency signal, and a substrate on which a first wiring connected to ground, a second wiring supplying power to the semiconductor chip, a third wiring connected to a protection element or circuit of the semiconductor chip, and fourth wirings transmitting a signal from the semiconductor chip are formed by plating, and the semiconductor chip is mounted.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: August 28, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoko Ono, Toshiya Mitomo
  • Patent number: 8236602
    Abstract: A phase change memory device resistant to stack pattern collapse is presented. The phase change memory device includes a silicon substrate, switching elements, heaters, stack patterns, bit lines and word lines. The silicon substrate has a plurality of active areas. The switching elements are connected to the active areas. The heaters are connected to the switching elements. The stack patterns are connected to the heaters. The bit lines are connected to the stack patterns. The word lines are connected to the active areas of the silicon substrate.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: August 7, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Heon Yong Chang
  • Publication number: 20120187287
    Abstract: The subject matter provided herein relates to substrates for desorbing and ionizing analytes, and kits and methods of use thereof. The substrate provided herein comprises a porous semiconductor, a fluorous initiator, and a photoactive compound containing a fluorous group.
    Type: Application
    Filed: January 23, 2012
    Publication date: July 26, 2012
    Inventors: Michael Charles Nyman, Matthew Paul Greving, Joseph Cohen