Including Thin Film Deposited On Metallic Or Insulating Substrate (epo) Patents (Class 257/E31.041)
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Patent number: 10392293Abstract: The present invention provides a high-transparency glass having a high fining action at a low temperature and capable of achieving redox lowering more than before. The present invention relates to a glass containing 1 to 500 ppm of a total iron oxide (t-Fe2O3) in terms of Fe2O3, having a redox ([divalent iron (Fe2+) in terms of Fe2O3]/[total (Fe2++Fe3+) of divalent iron (Fe2+) and trivalent iron (Fe3+) in terms of Fe2O3]) of 0% or more and 25% or less, containing, as expressed by mass percentage based on oxides, 50 to 81% of SiO2, 1 to 20% of Al2O3, 0 to 5% of B2O3, 5 to 20% of Li2O+Na2O+K2O, and 5 to 27% of MgO+CaO+SrO+BaO, and having a bubble disappearance-starting temperature (TD) of 1485° C. or lower.Type: GrantFiled: March 23, 2018Date of Patent: August 27, 2019Assignee: AGC Inc.Inventors: Yusaku Matsuo, Yutaka Kuroiwa, Yusuke Arai, Hiroyuki Hijiya, Yuki Kondo
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Patent number: 10312279Abstract: Multi-photodiode image pixels may include sub-pixels with differing light sensitivities. Microlenses may be formed over the multi-photodiode image pixels so that light sensitivity of sub-pixels in an outer group of sub-pixels is enhanced. To prevent high angle light incident upon one of the sub-pixels of the image pixel from generating charges in a photosensitive region of another sub-pixel of the image pixel, intra-pixel isolation structures may be formed. Intra-pixel isolation structures may surround, and in some embodiments, overlap the light collecting region of an inner photodiode. When the intra-pixel isolation structures have a different index of refraction than light filtering material formed adjacent to the isolation structures, high angle light incident upon the isolation structures may be reflected back into the sub-pixel it was initially incident upon.Type: GrantFiled: October 31, 2017Date of Patent: June 4, 2019Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Swarnal Borthakur, Marc Allen Sulfridge
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Patent number: 9971924Abstract: A two-substrate fingerprint recognition device includes a first substrate and a second substrate. A plurality of electrodes, a plurality of connection pads and a plurality of connection traces are deployed on one surface of the first substrate. A plurality of conductive connection pads, a plurality of connection pads, a plurality of connection traces and a plurality of switch circuits are deployed on one surface of the second substrate that faces the first substrate. At least one electrode connection pad of the second substrate is electrically connected to a corresponding electrode of the first substrate.Type: GrantFiled: August 16, 2016Date of Patent: May 15, 2018Assignee: SUPERC-TOUCH CORPORATIONInventors: Hsiang-Yu Lee, Shang Chin, Ping-Tsun Lin
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Patent number: 9029266Abstract: According to one embodiment, a semiconductor device manufacturing method includes depositing a silicon film above a semiconductor substrate, forming an insulating film which includes silicon oxide or silicon nitride on the silicon film, forming a physical guide having a depressed portion above the insulating film, forming a directed self-assembly material layer which includes a first polymer and a second polymer in the depressed portion of the physical guide, phase-separating the directed self-assembly material layer into a first region which includes the first polymer and a second region which includes the second polymer, removing the second region, processing the insulating film by using the physical guide and the first region as masks, and transferring a pattern corresponding to the second region to the insulating film. Further, the silicon film is processed by using the pattern transferred onto the insulating film as a mask.Type: GrantFiled: August 21, 2013Date of Patent: May 12, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Yusuke Kasahara, Noriko Sakurai
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Patent number: 9023736Abstract: A solar cell module manufacturing apparatus includes a stage, a holding member, a moving mechanism, and a pushing member. The stage suctions a plurality of elongated solar cells that is arranged to form a solar cell module. The holding member releasably holds a portion of a solar cell to be placed on the stage. The moving mechanism moves the holding member forward and backward with respect to the stage. The moving mechanism moves the holding member backward in a state that an end portion in a front side of the cell held by the holding member that has been moved forward is suctioned on the stage, and then the portion of the cell is released by the holding member. The pushing member moves over the cell such that the pushing member pushes a lift portion of the cell down to the stage while the holding member moves backward.Type: GrantFiled: February 13, 2012Date of Patent: May 5, 2015Assignee: Toray Engineering Co., Ltd.Inventors: Takashi Iwade, Toyoharu Terada, Kazunori Nakakita
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Patent number: 8916397Abstract: A method for producing an electronic component comprising barrier layers for the encapsulation of the component comprises, in particular, the following steps: providing a substrate (1) with at least one functional layer (22), applying at least one first barrier layer (3) on the functional layer (22) by means of plasmaless atomic layer deposition (PLALD), and applying at least one second barrier layer (4) on the functional layer (22) by means of plasma-enhanced chemical vapor deposition (PECVD).Type: GrantFiled: January 29, 2009Date of Patent: December 23, 2014Assignee: OSRAM Opto Semiconductors GmbHInventors: Christian Schmid, Tilman Schlenker, Heribert Zull, Ralph Paetzold, Markus Klein, Karsten Heuser
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Patent number: 8859321Abstract: Fabrication of a tandem photovoltaic device includes forming a bottom cell having an N-type layer, a P-type layer and a bottom intrinsic layer therebetween. A top cell is formed relative to the bottom cell. The top cell has an N-type layer, a P-type layer and a top intrinsic layer therebetween. The top intrinsic layer is formed of an undoped material deposited at a temperature that is different from the bottom intrinsic layer such that band gap energies for the top intrinsic layer and the bottom intrinsic layer are progressively lower for each cell.Type: GrantFiled: January 31, 2011Date of Patent: October 14, 2014Assignee: International Business Machines CorporationInventors: Ahmed Abou-Kandil, Keith E. Fogel, Augustin J. Hong, Jeehwan Kim, Devendra K. Sadana
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Patent number: 8772071Abstract: A method for manufacturing thin film solar cells, includes forming a light permeable first electrode layer in the back light surface of a glass substrate, and formed in the first electrode layer a plurality of first openings for exposing a part of the back light surface therefrom; forming a photoelectric conversion layer on the first electrode layer and the exposed back light surface, and forming a plurality of second openings in the photoelectric conversion layer for exposing a part of the first electrode layer therefrom; and forming a glistening second electrode layer having a plurality of third openings formed therein, wherein the second electrode layer comprises a conductive colloid comprised of non-diffractive fillings and polymeric base material.Type: GrantFiled: December 8, 2011Date of Patent: July 8, 2014Assignee: Industrial Technology Research InstituteInventors: Jun-Chin Liu, Yu-Hung Chen, Chien-Liang Wu, Yu-Ru Chen, Yu-Ming Wang
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Patent number: 8519453Abstract: A transistor device having a metallic source electrode, a metallic drain electrode, a metallic gate electrode and a channel in a deposited semiconductor material, the transistor device comprising: a first layer comprising the metallic gate electrode, a first metal portion of the metallic source electrode and a first metal portion of the metallic drain electrode; a second layer comprising a second metal portion of the metallic source electrode, a second metal portion of the metallic drain electrode, the deposited semiconductor material and dielectric material between the semiconductor material and the metallic gate electrode; and a third layer comprising a substrate, wherein the first, second and third layers are arranged in order such that the second layer is positioned between the first layer and the third layer.Type: GrantFiled: July 9, 2004Date of Patent: August 27, 2013Assignee: Hewlett-Packard Development Company, L.P.Inventor: John Christopher Rudin
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Patent number: 8466447Abstract: A crystal oriented metal back contact for solar cells is disclosed herein. In one embodiment, a photovoltaic device and methods for making the photovoltaic device are disclosed. The photovoltaic device includes a metal substrate with a crystalline orientation and a heteroepitaxial crystal silicon layer having the same crystal orientation of the metal substrate. A heteroepitaxial buffer layer having the crystal orientation of the metal substrate is positioned between the substrate and the crystal silicon layer to reduce diffusion of metal from the metal foil into the crystal silicon layer and provide chemical compatibility with the heteroepitaxial crystal silicon layer. Additionally, the buffer layer includes one or more electrically conductive pathways to electrically couple the crystal silicon layer and the metal substrate.Type: GrantFiled: August 6, 2009Date of Patent: June 18, 2013Assignee: Alliance for Sustainable Energy, LLCInventors: Howard M. Branz, Charles Teplin, Pauls Stradins
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Publication number: 20130139875Abstract: The present invention discloses a thin-film solar cell and a method for forming the same. The thin-film solar cell includes a substrate and a semiconductor layer containing a P-type crystalline silicon layer over the substrate, a first I-type crystalline silicon layer on the P-type crystalline silicon layer, a first N-type crystalline silicon layer on the first I-type crystalline silicon layer, a second I-type crystalline silicon layer on the first N-type crystalline silicon layer and a second N-type crystalline silicon layer on the second I-type crystalline silicon layer. Wherein, the semiconductor layer is formed with additional I-type and N-type crystalline silicon layers, thereby enhancing the photoelectric conversion efficiency of the thin-film solar cell.Type: ApplicationFiled: February 27, 2012Publication date: June 6, 2013Inventors: Chia-Ling LEE, Chien-Chung BI
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Patent number: 8415679Abstract: It is an object of the present invention to provide a peeling method that causes no damage to a layer to be peeled and to allow not only a layer to be peeled with a small surface area but also a layer to be peeled with a large surface area to be peeled entirely. Further, it is also an object of the present invention to bond a layer to be peeled to various base materials to provide a lighter semiconductor device and a manufacturing method thereof. Particularly, it is an object to bond various elements typified by a TFT, (a thin film diode, a photoelectric conversion element comprising a PIN junction of silicon, or a silicon resistance element) to a flexible film to provide a lighter semiconductor device and a manufacturing method thereof.Type: GrantFiled: May 1, 2012Date of Patent: April 9, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Toru Takayama, Junya Maruyama, Yumiko Ohno
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Patent number: 8357547Abstract: A method of manufacturing a semiconductor bio-sensor comprises providing a substrate, forming a first dielectric layer on the substrate, forming a patterned first conductive layer on the first dielectric layer, the patterned first conductive layer including a first portion and a pair of second portions, forming a second dielectric layer, a third dielectric layer and a fourth dielectric layer in sequence over the patterned first conductive layer, forming cavities into the fourth dielectric layer, forming vias through the cavities, exposing the second portions of the patterned first conductive layer, forming a patterned second conductive layer on the fourth dielectric layer, forming a passivation layer on the patterned second conductive layer, forming an opening to expose a portion of the third dielectric layer over the first portion of the patterned first conductive layer, and forming a chamber through the opening.Type: GrantFiled: June 29, 2012Date of Patent: January 22, 2013Assignee: Macronix International Co., Ltd.Inventors: Ming-Tung Lee, Shih-Chin Lien, Chia-Huan Chang
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Publication number: 20120119213Abstract: A thin film transistor of the present invention has an active layer including at least source, drain and channel regions formed on an insulating surface. A high resistivity region is formed between the channel region and each of the source and drain regions. A film capable of trapping positive charges therein is provided on at least the high resistivity region so that N-type conductivity is induced in the high resistivity region. Accordingly, the reliability of N-channel type TFT against hot electrons can be improved.Type: ApplicationFiled: November 7, 2011Publication date: May 17, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Yasuhiko TAKEMURA, Satoshi TERAMOTO
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Patent number: 8110887Abstract: Provided are a photodetector capable of suppressing variations in the output characteristics among photodiodes, and a display device provided with the photodetector. A display device in use has an active matrix substrate (20) including a transparency base substrate (2), a plurality of active elements and a photodetector. The photodetector includes a light-shielding layer (3) provided on the base substrate (2), and a photodiode (1) arranged on an upper layer of the light-shielding layer (3). The light-shielding layer (3) is overlapped with the photodiode (1) in the thickness direction of the base substrate (2). The photodiode (1) includes a silicon layer (11) insulated electrically from the light-shielding layer (3). The silicon layer (11) includes a p-layer (11c), an i-layer (11b) and an n-layer (11a) that are provided adjacent to each other in the planar direction. The p-layer (11c) is formed so that its area (length Lp) will be larger than the area (length Ln) of the n-layer (11a).Type: GrantFiled: June 12, 2008Date of Patent: February 7, 2012Assignee: Sharp Kabushiki KaishaInventors: Christopher Brown, Hiromi Katoh
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Publication number: 20120025190Abstract: The present invention provides a radiation detector that may set output characteristics of an electrical signal for output so as to match the detection range of an amplifier. Namely, a charge storage capacitor is provided to each sensor section so as to be electrically connected to a bias line in parallel to the respective sensor section.Type: ApplicationFiled: May 18, 2011Publication date: February 2, 2012Applicant: FUJIFILM CorporationInventor: Yoshihiro Okada
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Patent number: 8026565Abstract: A thin film semiconductor in the form of a metal semiconductor field effect transistor, includes a substrate 10 of paper sheet material and a number of thin film active inorganic layers that are deposited in layers on the substrate. The active layers are printed using an offset lithography printing process. A first active layer comprises source 12.1 and drain 12.2 conductors of colloidal silver ink, that are printed directly onto the paper substrate. A second active layer is an intrinsic semiconductor layer 14 of colloidal nanocrystalline silicon ink which is printed onto the first layer. A third active layer comprises a metallic conductor 16 of colloidal silver which is printed onto the second layer to form a gate electrode. This invention extends to other thin film semiconductors such as photovoltaic cells and to a method of manufacturing semiconductors.Type: GrantFiled: January 30, 2004Date of Patent: September 27, 2011Assignee: University of Cape TownInventors: Margit Harting, David Thomas Britton
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Publication number: 20110115004Abstract: An embedded photodetector apparatus for a three-dimensional complementary metal oxide semiconductor (CMOS) stacked chip assembly having a CMOS chip and one or more thinned CMOS layers is provided. At least one of the one or more thinned CMOS layers includes an active photodiode area defined within the one or more thinned CMOS layers, the active photodiode area being receptive of an optical signal incident thereon, and the active photodiode area comprising a bulk substrate portion of the thinned CMOS layer. The bulk substrate portion has a diode photodetector formed therein.Type: ApplicationFiled: November 16, 2009Publication date: May 19, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Fadi H. Gebara, Tak H. Ning, Qiqing C. Ouyang, Jeremy D. Schaub
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Patent number: 7915101Abstract: Thin film transistors and organic light emitting displays using the same are provided. The thin film transistor may include a substrate, a semiconductor layer, a gate electrode, and source/drain electrodes on the substrate. The semiconductor layer is composed of a P-type semiconductor layer obtained by diffusing phosphorus into a zinc oxide semiconductor. The phosphorus is doped in the semiconductor layer to a concentration ranging from about 1×1014 to about 1×1018 cm?3.Type: GrantFiled: May 9, 2008Date of Patent: March 29, 2011Assignee: Samsung Mobile Display Co., Ltd.Inventors: Jae-kyeong Jeong, Yeon-gon Mo, Jin-seong Park, Hyun-soo Shin, Hun-jung Lee, Jong-han Jeong
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Publication number: 20110041902Abstract: A method for producing monocrystalline n-silicon solar cells having a rear-side passivated p+ emitter and rear-side, spatially separate heavily doped n++-base regions near the surface, as well as an interdigitated rear-side contact finger structure, which is in conductive connection with the p+-emitter regions and the n++-base regions. An aluminum thin layer or an aluminum-containing thin layer is first deposited on the rear side of the n-silicon wafer, and the thin layer is subsequently structured so that openings are obtained in the region of the future base contacts. In a further process step, the aluminum is then diffused into the n-silicon wafer in order to form a structured emitter layer.Type: ApplicationFiled: February 11, 2009Publication date: February 24, 2011Inventors: Hans-Joachim Krokoszinski, Jan Lossen
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Patent number: 7858450Abstract: An optic mask for crystallizing amorphous silicon comprises a first slit region including a plurality of slits regularly arranged for defining incident region of laser beam, wherein the slits of the first slit region are formed to slope by a predetermined angle to the direction of transfer of the optic mask in crystallization process, and wherein the slits of the first slit region includes a first slit having a first length and a second slit having a second length which is longer than the first length.Type: GrantFiled: January 5, 2005Date of Patent: December 28, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Ui-Jin Chung, Myung-Koo Kang, Jae-Bok Lee
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Patent number: 7767506Abstract: An exposure mask is provided, which includes: a light blocking opaque area blocking incident light; a translucent area; and a transparent area passing the most of incident light, wherein the translucent area generates the phase differences in the range of about ?70° to about +70°.Type: GrantFiled: October 24, 2008Date of Patent: August 3, 2010Assignee: Samsung Electronics Co. Ltd.Inventors: Jong-An Kim, Ji-Haeng Han, Young-Bae Jung, Bae-Hyoun Jung
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Patent number: 7750422Abstract: In a solid state image pickup apparatus with a photodetecting device and one or more thin film transistors connected to the photodetecting device formed in one pixel, a part of the photodetecting device is formed over at least a part of the thin film transistor, and the thin film transistor is constructed by a source electrode, a drain electrode, a first gate electrode, and a second gate electrode arranged on the side opposite to the first gate electrode with respect to the source electrode and the drain electrode, and the first gate electrode is connected to the second gate electrode every pixel, thereby, suppressing an adverse effect of the photodetecting device on the TFT, a leakage at turn-off TFT, variation in a threshold voltage of the TFT due to an external electric field, and accurately transferring photo carrier to a signal processing circuit.Type: GrantFiled: March 12, 2007Date of Patent: July 6, 2010Assignee: Canon Kabushiki KaishaInventors: Minoru Watanabe, Masakazu Morishita, Chiori Mochizuki, Takamasa Ishii, Keiichi Nomura
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Patent number: 7736997Abstract: A flexible electronic device excellent in heat liberation characteristics and toughness and a production method for actualizing thereof in low cost and with satisfactory reproducibility are provided. A protection film is adhered onto the surface of a substrate on which surface a thin film device is formed. Successively, the substrate is soaked in an etching solution to be etched from the back surface thereof so as for the residual thickness of the substrate to fall within the range larger than 0 ?m and not larger than 200 ?m. Then, a flexible film is adhered onto the etched surface of the substrate, and thereafter the protection film is peeled to produce a flexible electronic device.Type: GrantFiled: March 11, 2005Date of Patent: June 15, 2010Assignee: NEC CorporationInventor: Kazushige Takechi
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Patent number: 7709886Abstract: A fabricating method of a TFT includes first forming a source on a substrate. Then, a first insulation pattern layer is formed to cover parts of the source and the substrate. The first insulation pattern layer has an opening exposing a part of the source. Thereafter, a gate pattern layer is formed on the first insulation pattern layer. Then, the gate pattern layer and a second insulation pattern layer formed thereon surround the opening. Moreover, a second lateral protection wall is formed on an edge of the gate pattern layer in the opening. Afterwards, a channel layer is formed in the opening and covers the second lateral protection wall and the source. Then, a passivation layer with a contact window is formed on the channel layer and the second insulation pattern layer to expose a portion of the channel layer. Thereafter, a drain is formed on the exposed channel layer.Type: GrantFiled: December 4, 2007Date of Patent: May 4, 2010Assignee: Au Optronics CorporationInventors: Wei-Hsiang Lo, Hao-Chieh Lee
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Patent number: 7646022Abstract: The present invention provides an active matrix type display device having a high aperture ratio and a required auxiliary capacitor. A source line and a gate line are overlapped with part of a pixel electrode. This overlapped region functions to be a black matrix. Further, an electrode pattern made of the same material as the pixel electrode is disposed to form the auxiliary capacitor by utilizing the pixel electrode. It allows a required value of auxiliary capacitor to be obtained without dropping the aperture ratio. Also, it allows the electrode pattern to function as a electrically shielding film for suppressing the cross-talk between the source and gate lines and the pixel electrode.Type: GrantFiled: May 9, 2006Date of Patent: January 12, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hongyong Zhang, Satoshi Teramoto
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Patent number: 7638802Abstract: A flat panel display includes a plurality of gate lines; a plurality of data lines insulated with the gate lines, the data lines defining a pixel by intersecting the gate line; and a thin film transistor (TFT) being provided in each of the pixels and containing an organic semiconductor layer, wherein a distance between the adjacent TFTs in a direction extended to the gate line is longer than a width of the pixel in a direction extended to the gate line.Type: GrantFiled: August 18, 2006Date of Patent: December 29, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Keun-kyu Song, Yong-uk Lee
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Publication number: 20090289283Abstract: A wafer for backside illumination type solid imaging device has a plurality of pixels inclusive of a photoelectric conversion device and a charge transfer transistor at its front surface side and a light receiving surface at its back surface side, wherein said wafer is a SOI wafer obtained by forming a given active layer on a support substrate made of C-containing p-type semiconductor material through an insulating layer.Type: ApplicationFiled: May 20, 2009Publication date: November 26, 2009Applicant: Sumco CorporationInventors: Kazunari Kurita, Shuichi Omote
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Patent number: 7566904Abstract: A thin film transistor has a semiconductor thin film including zinc oxide, a protection film formed on entirely the upper surface of the semiconductor thin film, a gate insulating film formed on the protection film, a gate electrode formed on the gate insulating film above the semiconductor thin film, and a source electrode and drain electrode formed under the semiconductor thin film so as to be electrically connected to the semiconductor thin film.Type: GrantFiled: June 7, 2006Date of Patent: July 28, 2009Assignee: Casio Computer Co., Ltd.Inventor: Hiromitsu Ishii
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Patent number: 7550771Abstract: A thin film transistor includes a metal substrate, a first conductive barrier layer placed on the metal substrate to prevent diffusion of substance of the metal substrate, a protective insulating film placed on the first conductive barrier layer, a semiconductor layer placed on the protective insulating film and including a source region, a drain region and a channel region, a gate insulating film placed on the semiconductor layer, and a gate electrode placed above the semiconductor layer with the gate insulating film interposed therebetween. The first conductive barrier layer and the semiconductor layer are electrically connected through a first opening of the protective insulating film.Type: GrantFiled: April 5, 2007Date of Patent: June 23, 2009Assignee: Mitsubishi Electric CorporationInventor: Hitoshi Nagata
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Patent number: 7449352Abstract: An exposure mask is provided, which includes: a light blocking opaque area blocking incident light; a translucent area; and a transparent area passing the most of incident light, wherein the translucent area generates the phase differences in the range of about ?70° to about +70°.Type: GrantFiled: December 14, 2005Date of Patent: November 11, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-An Kim, Ji-Haeng Han, Young-Bae Jung, Bae-Hyoun Jung
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Publication number: 20080227236Abstract: This invention comprises manufacture of photovoltaic cells by deposition of thin film photovoltaic junctions on metal foil substrates. The photovoltaic junctions may be heat treated if appropriate following deposition in a continuous fashion without deterioration of the metal support structure. In a separate operation, an interconnection substrate structure is provided, optionally in a continuous fashion. Multiple photovoltaic cells are then laminated to the interconnection substrate structure and conductive joining methods are employed to complete the array. In this way the interconnection substrate structure can be uniquely formulated from polymer-based materials employing optimal processing unique to polymeric materials. Furthermore, the photovoltaic junction and its metal foil support can be produced in bulk without the need to use the expensive and intricate material removal operations currently taught in the art to achieve series interconnections.Type: ApplicationFiled: May 19, 2008Publication date: September 18, 2008Inventor: Daniel Luch
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Publication number: 20080116516Abstract: A TFT array substrate is provided. The TFT array substrate includes a substrate, a patterned first metallic layer, a patterned semiconductor layer, a patterned transparent conductive layer, a patterned dielectric layer, and a patterned second metallic layer. Elements of each TFT of the TFT array substrate are arranged vertically, so that the TFT array substrate has relatively small fabrication area and is operable with a high conducting current. Further, the storage capacitance can be enhanced by enclosing or sandwiching the transparent electrodes with the common lines and the second metallic layer, or alternatively by enclosing or sandwiching the second metallic layer with the common lines and the transparent electrodes.Type: ApplicationFiled: February 13, 2007Publication date: May 22, 2008Applicant: AU OPTRONICS CORPORATIONInventors: Yeong-Feng Wang, Chih-Jui Pan, Liang-Bin Yu
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Publication number: 20080099840Abstract: A method for forming an etch-stop layer and a resulting structure fabricated therefrom. The etch-stop layer has a semiconductor layer having a first surface and a boron layer formed below the first surface of the semiconductor layer. The boron layer has a full-width half-maximum (FWHM) thickness value of less than 100 nanometers. The boron layer is formed by a chemical vapor deposition (CVD) system.Type: ApplicationFiled: October 26, 2006Publication date: May 1, 2008Applicant: Atmel CorporationInventor: Darwin G. Enicks
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Publication number: 20080092954Abstract: Disclosed herein is a light-absorbing layer for a solar cell with enhanced sunlight absorption comprising CuGaSe2, CuIn1-xGaxSe2 and CuInSe2 thin films laminated one another. Further disclosed is a method of manufacturing the light absorbing layer. The method comprises the steps of: forming an InSe thin film from a single precursor containing In and Se on a substrate by metal organic chemical vapor deposition; forming a Cu2Se thin film using a Cu precursor on the InSe thin film by metal organic chemical vapor deposition; forming a CuGaSe2 thin film using a single precursor containing Ga and Se on the Cu2Se thin film by metal organic chemical vapor deposition; and forming a CuGaSe2/CuInSe2 multilayer thin-film structure using the single precursor containing In and Se and the Cu precursor on the CuGaSe2 thin film by metal organic chemical vapor deposition.Type: ApplicationFiled: February 3, 2005Publication date: April 24, 2008Applicant: In-Solar Tech. Co. Ltd.Inventor: In-hwan Choi
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Patent number: 7358101Abstract: The present invention relates to a method for preparing an optical active layer with 1˜10 nm distributed silicon quantum dots, it adopts high temperature processing and atmospheric-pressure chemical vapor deposition (APCVD), and directly deposit to form a silicon nitrite substrate containing 1˜10 nm distributed quantum dots, said distribution profile of quantum dot size from large to small is corresponding to from inner to outer layers of film respectively, and obtain a 400˜700 nm range of spectrum and white light source under UV photoluminescence or electro-luminescence.Type: GrantFiled: September 6, 2005Date of Patent: April 15, 2008Assignee: Institute of Nuclear Energy ResearchInventors: Tsun Neng Yang, Shan Ming Lan
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Publication number: 20080067591Abstract: A semiconductor device includes a semiconductor substrate having an insulation layer and a semiconductor layer formed on the insulation layer; a channel area formed in the semiconductor layer; a gate electrode formed on the channel area; a source area formed in the semiconductor layer and having a depth not reaching the insulation layer; a drain area formed in the semiconductor layer adjacent to the source area with the channel area in between and having a depth reaching the insulation layer; a separation area disposed next to the source area opposite to the channel area and having a depth not reaching the insulation layer; a high-concentration body area formed in the semiconductor layer at lease in a surface layer thereof and between the first separation area and the second separation area; and a body contact disposed on the high-concentration body area.Type: ApplicationFiled: May 11, 2007Publication date: March 20, 2008Inventor: Kouichi Tani
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Publication number: 20080038885Abstract: A thin film transistor array panel includes a source electrode and a drain electrode composed of a Mo alloy layer and a Cu layer, and an alloying element of the Mo alloy layer forms a nitride layer as a diffusion barrier against the Cu layer. The nitride layer can be formed between the Mo alloy layer and the Cu layer, between the Mo alloy layer and the semiconductor layer or in the Mo alloy layer. A method of fabricating a thin film transistor array panel includes forming a data line having a first conductive layer and a second conductive layer, the first conductive layer containing a Mo alloy and the second conductive layer containing Cu, and performing a nitrogen treatment so that an alloying element in the first conductive layer forms a nitride layer. The nitrogen treatment can be performed before forming the first conductive layer, after forming the first conductive layer, or during forming the first conductive layer.Type: ApplicationFiled: August 24, 2007Publication date: February 14, 2008Inventors: Je Lee, Yang Bae, Beom Cho, Chang Jeong
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Publication number: 20070272982Abstract: Provided is an electro-optical apparatus including a first thin-film transistor having a first gate electrode, a first gate insulating layer and a first active layer, which are respectively formed of a conductive film, an insulating film and a semiconductor film, in a pixel region of a device substrate, the apparatus including: a second thin-film transistor having a first gate electrode formed of the conductive film, a second gate insulating layer formed by removing a portion of the insulating film in a thickness direction and a second active layer formed of the semiconductor film, in a region other than the pixel region of the device substrate.Type: ApplicationFiled: April 16, 2007Publication date: November 29, 2007Applicant: EPSON IMAGING DEVICES CORPORATIONInventor: Takashi Sato
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Publication number: 20070262383Abstract: A semiconductor IC device includes a base substrate comprising P?-type silicon, a first P+-type silicon layer is provided on the base substrate, and an N+-type silicon layer and a second P+-type silicon layer are provided in the same layer thereon. The impurity concentration of the first P+-type silicon layer and the N+-type silicon layer is higher than that of the base substrate. Also, a buried oxide layer and an SOI layer are provided on the entire upper surface of the N+-type silicon layer and the second P+-type silicon layer. The first P+-type silicon layer is connected to ground potential wiring GND, and the N+-type silicon layer is connected to power-supply potential wiring VDD. Accordingly, a decoupling capacitor, which is connected in parallel to the power supply, is formed between the P+-type silicon layer and the N+-type silicon layer.Type: ApplicationFiled: June 22, 2007Publication date: November 15, 2007Applicant: NEC ELECTRONICS CORPORATIONInventors: Hiroaki OHKUBO, Masayuki Furumiya, Ryota Yamamoto, Yasutaka Nakashiba
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Patent number: 7285809Abstract: An image input apparatus includes an insulating substrate; polycrystalline silicon islands formed on said insulating substrate; pixels each including thin film transistors and a photodiode formed above said thin film transistors, each of the thin film transistors have a source region, a channel region and a drain region foamed in one of the polycrystalline silicon islands.Type: GrantFiled: April 24, 2006Date of Patent: October 23, 2007Assignee: NEC CorporationInventors: Hiroshi Tanabe, Hiroshi Haga
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Patent number: 7220681Abstract: A semiconductor device including a gate insulating film selectively formed on a predetermined region of a semiconductor substrate; a gate electrode formed on said gate insulating film; and a source region and drain region formed, in a surface portion of said semiconductor substrate, on two sides of a channel region positioned below said gate electrode; wherein a carbon concentration in an interface where said gate insulating film is in contact with said gate electrode is not more than 5×1022 atoms/cm3.Type: GrantFiled: February 4, 2005Date of Patent: May 22, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Katsuyuki Sekine, Akio Kaneko, Motoyuki Sato, Seiji Inumiya, Kazuhiro Eguchi
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Patent number: 7153730Abstract: A method is provided for crystallizing a silicon film in liquid crystal display (LCD) fabrication. The method comprises: forming an amorphous silicon film having a thickness in the range of 100 to 1000 Angstroms (?); irradiating the silicon film with a laser pulse having a pulse width of 50 nanoseconds (ns) or greater, as measured at the full-width-half-maximum (FWHM), using a beamlet width in the range of 3 to 20 microns; and, in response to irradiating the silicon film, laterally growing crystal grains. In one example, irradiating the silicon film may include irradiating with a pulse having a pulse width in the range between 30 and 300 ns FWHM, and an energy density in the range from 200 to 1300 millijoules per square centimeter (mJ/cm2).Type: GrantFiled: March 10, 2003Date of Patent: December 26, 2006Assignee: Sharp Laboratories of America, IncInventor: Apostolos Voutsas