Abstract: A high sensitivity image sensor including a pixel, the pixel including a single electron field effect transistor (SEFET), the SEFET including a first conductive type well in a second conductive type substrate, second conductive type source and drain regions in the well and a first conductive type gate region in the well between the source and the drain regions.

Abstract: A silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) device that includes a substrate; a buried oxide layer near a bottom of the substrate; a collector region above and in contact with the buried oxide layer; a field oxide region on each side of the collector region; a pseudo buried layer under each field oxide region and in contact with the collector region; and a through region under and in contact with the buried oxide layer. A method for manufacturing a SiGe HBT device is also disclosed. The SiGe HBT device can isolate noise from the bottom portion of the substrate and hence can improve the intrinsic noise performance of the device at high frequencies.

Abstract: A solid-state imaging device includes semiconductor substrate; a plurality of photoelectric conversion sections of n-type that are formed at an upper part of semiconductor substrate and arranged in a matrix; output circuit that is formed on a charge detection surface that is one surface of semiconductor substrate and detects charges stored in photoelectric conversion sections; a plurality of isolating diffusion layers of a p-type that are formed under output circuit and include high concentration p-type layers adjacent to respective photoelectric conversion sections; and color filters formed on a light incident surface that is the other surface opposing the one surface of semiconductor substrate and transmit light with different wavelengths. Shapes of respective photoelectric conversion sections correspond to color filters and differ depending on the high concentration p-type layer configuring isolating diffusion layer.

Abstract: In accordance with the invention, an improved image sensor includes an array of germanium photosensitive elements integrated with a silicon substrate and integrated with silicon readout circuits. The silicon transistors are formed first on a silicon substrate, using well known silicon wafer fabrication techniques. The germanium elements are subsequently formed overlying the silicon by epitaxial growth. The germanium elements are advantageously grown within surface openings of a dielectric cladding. Wafer fabrication techniques are applied to the elements to form isolated germanium photodiodes. Since temperatures needed for germanium processing are lower than those for silicon processing, the formation of the germanium devices need not affect the previously formed silicon devices. Insulating and metallic layers are then deposited and patterned to interconnect the silicon devices and to connect the germanium devices to the silicon circuits.

Abstract: An electronically scannable multiplexing device is capable of addressing multiple bits within a volatile or non-volatile memory cell. The multiplexing device generates an electronically scannable conducting channel with two oppositely formed depletion regions. The depletion width of each depletion region is controlled by a voltage applied to a respective control gate at each end of the multiplexing device. The present multi-bit addressing technique allows, for example, 10 to 100 bits of data to be accessed or addressed at a single node. The present invention can also be used to build a programmable nanoscale logic array or for randomly accessing a nanoscale sensor array.

Abstract: A homojunction type high-speed photodiode has an active area of greater than at least 50 microns (?m) or preferably greater than 60 microns (?m) in diameter, which has an p-i-n junction epitaxial layer formed on a semiconductor substrate and includes a first ohmic contact layer, an absorption layer, a collector layer and a second ohmic contact layer. No more absorbance occurs in the collector layer of InGaAs, by means of completely absorbing the photon energy in advance by the absorption layer in which the absorption layer has powerful optical absorption constant. Not only can the prior art problems be solved, such as surface absorbance, but also improved electron transport can be achieved by using InGaAs as the constructing material, compared to other materials. The resistance capacitance (RC) for the entire structure can be significantly reduced, and the limitations to the bandwidth resulted from the carrier transport time can be improved.

Abstract: Embodiments of the invention include a method for forming a tunable semiconductor device and the resulting structure. The invention comprises forming a semiconductor substrate. Next, pattern a first mask over the semiconductor substrate. Dope regions of the semiconductor substrate not protected by the first mask to form a first discontinuous subcollector. Remove the first mask. Pattern a second mask over the semiconductor substrate. Dope regions of the semiconductor substrate not protected by the second mask and on top of the first discontinuous subcollector to form a second discontinuous subcollector. Remove the second mask and form a collector above the second discontinuous subcollector. Breakdown voltage of the device may be tuned by varying the gaps separating doped regions within the first and second discontinuous subcollectors. Doped regions of the first and second discontinuous subcollectors may be formed in a mesh pattern.

Abstract: A photoelectric converting apparatus has first and third semiconductor layers of a first conductivity type which respectively output signals obtained by photoelectric conversion, and second and fourth semiconductor layers of a second conductivity type supplied with potentials from a potential supplying unit. In the photoelectric converting apparatus, the first, second, third and fourth semiconductor layers are arranged in sequence, the second and fourth semiconductor layers are electrically separated from each other, and the potential to be supplied to the second semiconductor layer and the potential to be supplied to the fourth semiconductor layer are controlled independently from each other.

Abstract: A multiple-junction photoelectric device includes a substrate with a first conducting layer thereon, at least two elementary photoelectric devices of p-i-n or p-n configuration, with a second conducting layer thereon, and at least one intermediate layer between two adjacent elementary photoelectric devices. The intermediate layer has, on the incoming light side, opposite top and bottom faces, the top and bottom faces having respectively a surface morphology including inclined elementary surfaces so ?90bottom is smaller than ?90top by at least 3°, preferably 6°, more preferably 10°, and even more preferably 15°; where ?90top is the angle for which 90% of the elementary surfaces of the top face of the intermediate layer have an inclination equal to or less than this angle, and ?90bottom is the angle for which 90% of the elementary surfaces of the bottom face of the intermediate layer have an inclination equal to or less than this angle.

Abstract: Vertical heterojunction bipolar transistors with reduced base-collector junction capacitance, as well as fabrication methods for vertical heterojunction bipolar transistors and design structures for BiCMOS integrated circuits. The vertical heterojunction bipolar transistor includes a barrier layer between the intrinsic base and the extrinsic base that blocks or reduces diffusion of a dopant from the extrinsic base to the intrinsic base. The barrier layer has at least one opening that permits direct contact between the intrinsic base and a portion of the extrinsic base disposed in the opening.

Abstract: A sensor including an array of light sensitive pixels, each pixel including: at least one hetero-junction phototransistor having a floating base without contact, wherein each phototransistor is a mesa device having active layers exposed at side-walls of the mesa device; and at least one atomic layer deposited high-k dielectric material adjacent to and passivating at least the side-wall exposed active layers.

Abstract: A two-terminal mesa phototransistor and a method for making it are disclosed. The photo transistor has a mesa structure having a substantially planar semiconductor surface. In the mesa structure is a first semiconductor region of a first doping type, and a second semiconductor region of a second doping type opposite to that of the first semiconductor region, forming a first semiconductor junction with the first region. In addition, a third semiconductor region of the first doping type forms a second semiconductor junction with the second region. The structure also includes a dielectric layer. The second semiconductor region, first semiconductor junction, and second semiconductor junction each has an intersection with the substantially planar semiconductor surface. The dielectric covers, and is in physical contact with, all of the intersections.

Abstract: An optoelectronic semiconductor chip including a radiation passage area, where a contact metallization is applied to the radiation passage area, and a first reflective layer sequence is applied to that surface of the contact metallization which is remote from the radiation passage area, and an optoelectronic component that includes such a chip.

Abstract: A method for making a nanowire element includes: providing an imprint mold including a first substrate and a conductive pattern-transferring layer, the pattern-transferring layer includes first conductive strips; electrifying the pattern-transferring layer with an alternating current; applying a nanowire-containing suspension on the pattern-transferring layer; reorienting the nanowires in the nanowire-containing suspension using a dielectrophoresis method, thereby the nanowires connected between two adjacent first conductive strips; providing a pattern-receiving body, the pattern-receiving body including a second substrate and a pattern-receiving layer; pressing the imprint mold onto the pattern-receiving body with the conductive pattern-transferring layer facing the pattern-receiving layer, thereby defining a patterned recess in the pattern-receiving layer and transferring the nanowires to the second substrate; forming a first conductive layer on the second substrate to obtain a conductive pattern layer, the

Abstract: Vertical heterojunction bipolar transistors with reduced base-collector junction capacitance, as well as fabrication methods for vertical heterojunction bipolar transistors and design structures for BiCMOS integrated circuits. The vertical heterojunction bipolar transistor includes a barrier layer between the intrinsic base and the extrinsic base that blocks or reduces diffusion of a dopant from the extrinsic base to the intrinsic base. The barrier layer has at least one opening that permits direct contact between the intrinsic base and a portion of the extrinsic base disposed in the opening.

Abstract: The present invention provides a multi-finger structure of a SiGe heterojunction bipolar transistor (HBT). It is consisted of plural SiGe HBT single cells. The multi-finger structure is in a form of C/BEBC/BEBC/.../C, wherein, C, B, E respectively stands for collector, base and emitter; CBEBC stands for a SiGe HBT single cell. The collector region is consisted of an n type ion implanted layer inside the active region. The bottom of the implanted layer is connected to two n type pseudo buried layers. The two pseudo buried layers are formed through implantation to the bottom of the shallow trenches that surround the collector active region. Two collectors are picked up by deep trench contact through the field oxide above the two pseudo buried layers. The present invention can reduce junction capacitance, decrease collector electrode output resistance, and improve device frequency characteristics.

Abstract: A light-sensitive component which has a semiconductor junction between a thin relatively highly doped epitaxial layer and a relatively lightly doped semiconductor substrate. Outside a light incidence window, an insulating layer is arranged between epitaxial layer and semiconductor substrate. In this case, the thickness of the epitaxial layer is less than 50 nm, with the result that a large proportion of the light quanta incident in the light incidence window can be absorbed in the lightly doped semiconductor substrate.

Abstract: The MEMS package has a mounting substrate on which one or more transducer chips are mounted wherein the mounting substrate has an opening. A top cover is attached to and separated from the mounting substrate by a spacer forming a housing enclosed by the top cover, the spacer, and the mounting substrate and accessed by the opening. Electrical connections are made between the one or more transducer chips and the mounting substrate and/or between the one or more transducer chips and the top cover. A bottom cover can be mounted on a bottom surface of the mounting substrate wherein a hollow chamber is formed between the mounting substrate and the bottom cover, wherein a second opening in the bottom cover is not aligned with the first opening. Pads on outside surfaces of the top and bottom covers can be used for further attachment to printed circuit boards. The top and bottom covers can be a flexible printed circuit board folded under the mounting substrate.

Abstract: A method of manufacturing a photo-detector array device integrated with a read-out integrated circuit (ROIC) monolithically integrated for a laser-radar image signal. A detector array device, a photodiode and control devices for selecting and outputting a laser-radar image signal are simultaneously formed on an InP substrate. In addition, after the photodiode and the control devices are simultaneously formed on the InP substrate, the photodiode and the control devices are electrically separated from each other using a polyamide, whereby a PN junction surface of the photodiode is buried to reduce surface leakage current and improve electrical reliability, and the structure of the control devices can be simplified to improve image signal reception characteristics.

Abstract: An optical semiconductor device includes a phototransistor for receiving incident light. The phototransistor includes a collector layer of a first conductivity type formed on a semiconductor substrate, a base layer of a second conductivity type formed on the collector layer, and an emitter layer of a first conductivity type formed on the base layer. A thickness of the emitter layer is equal to or less than an absorption length of the incident light in the semiconductor substrate.

Abstract: A semiconductor light emitting device includes a multi-layered semiconductor layer having at least a first conductive type cladding layer, an active layer, a second conductive type first cladding layer, an etching stop layer, and a second conductive type second cladding layer on a substrate. An upper section of a ridge groove is formed by an anisotropic etching process, as a first groove in such a way as to have a depth from a surface of the multi-layered semiconductor layer and as not to cross the etching stop layer at the depth. A bottom groove of the ridge groove is formed by an isotropic etching process, as a second groove by performing etching in such a way as to be stopped by the etching stop layer.

Abstract: A pixel space is narrowed without increasing PN junction capacitance. A photoelectric conversion device includes a plurality of pixels arranged therein, each including a first impurity region of a first conductivity type forming a photoelectric conversion region, a second impurity region of a second conductivity type forming a signal acquisition region arranged in the first impurity region, a third impurity region of the first conductivity type and a fourth impurity region of the first conductivity type are arranged in a periphery of each pixel for isolating the each pixel, the fourth impurity region is disposed between adjacent pixels, and an impurity concentration of the fourth impurity region is smaller than an impurity concentration of the third impurity region.

Abstract: A method of manufacturing a photo-detector array device integrated with a read-out integrated circuit (ROIC) monolithically integrated for a laser-radar image signal. A detector array device, a photodiode and control devices for selecting and outputting a laser-radar image signal are simultaneously formed on an InP substrate. In addition, after the photodiode and the control devices are simultaneously formed on the InP substrate, the photodiode and the control devices are electrically separated from each other using a polyamide, whereby a PN junction surface of the photodiode is buried to reduce surface leakage current and improve electrical reliability, and the structure of the control devices can be simplified to improve image signal reception characteristics.

Abstract: Described herein are single-sided lateral-field optoelectronic tweezers (LOET) devices which use photosensitive electrode arrays to create optically-induced dielectrophoretic forces in an electric field that is parallel to the plane of the device. In addition, phototransistor-based optoelectronic tweezers (PhOET) devices are described that allow for optoelectronic tweezers (OET) operation in high-conductivity physiological buffer and cell culture media.

Abstract: An image sensor includes a semiconductor layer, and first and second photoelectric converting units including first and second impurity regions in the semiconductor layer that are spaced apart from each other and that are at about an equal depth in the semiconductor layer, each of the impurity regions including an upper region and a lower region. A width of the lower region of the first impurity region may be larger than a width of the lower region of the second impurity region, and widths of upper regions of the first and second impurity regions are equal.

Abstract: A BJT (bipolar junction transistor)-based uncooled IR sensor and a manufacturing method thereof are provided. The BJT-based uncooled IR sensor includes: a substrate; at least one BJT which is formed to be floated apart from the substrate; and a heat absorption layer which is formed on an upper surface of the at least one BJT, wherein the BJT changes an output value according heat absorbed through the heat absorption layer. Accordingly, it is possible to provide a BJT-based uncooled IR sensor capable of being implemented through a CMOS compatible process and obtaining more excellent temperature change detection characteristics.

Abstract: A sensor including an array of light sensitive pixels, each pixel including: at least one hetero-junction phototransistor having a floating base without contact, wherein each phototransistor is a mesa device having active layers exposed at side-walls of the mesa device; and at least one atomic layer deposited high-k dielectric material adjacent to and passivating at least the side-wall exposed active layers.

Abstract: An optical semiconductor device includes a phototransistor for receiving incident light. The phototransistor includes a collector layer of a first conductivity type formed on a semiconductor substrate, a base layer of a second conductivity type formed on the collector layer, and an emitter layer of a first conductivity type formed on the base layer. A thickness of the emitter layer is equal to or less than an absorption length of the incident light in the semiconductor substrate.

Abstract: A bipolar transistor comprising a collector region of a first conduction type, and a subcollector region of the first conduction type at a first side of the collector region. The transistor further includes a base region of the second conduction type provided at a second side of the collector region, and an emitter region of the first conduction type which is provided above the base region on the side remote from the collection region. A carbon-doped semiconductor region is provided on the first side alongside the collector region. The bipolar transistor is characterized in that the carbon-doped semiconductor region has a carbon concentration of 1019-1021 cm?3 and the base region has a smaller cross section than the collector region and the collector region has, in the overlap region with the base region, a region having an increased doping compared with the remaining region.

Abstract: A phototransistor (400) comprises an emitter (43) comprising antimony, a base (42) comprising antimony, and a collector (41) comprising antimony. Preferably, the emitter, the base and the collector each comprises at least one of AlInGaAsSb, AlGaAsSb, AlGaSb, GaSb and InGaAsSb. The base comprises an emitter-contacting portion (41b) with a base-contacting portion (43a) of the emitter. The collector comprises a base-contacting portion (41b) which is in contact with a collector-contacting portion (421a) of the base. The phototransistor produces an internal gain upon being contacted with light within a receivable wavelength range, preferably greater than 1.7 micrometers. Also, a method of detecting light using such a phototransistor.

Abstract: An integrated circuit, and method for manufacturing the integrated circuit, where the integrated circuit can include a phototransistor comprising a base having a SiGe base layer of a predetermined germanium composition and a thickness of more than 65 nm and less than about 90 nm. The integrated circuit can further include a transimpedance amplifier (TIA) receiving an output from the phototransistor. The phototransistor and the TIA can be built on a silicon substrate.

Abstract: The invention relates to a method for producing integrable semiconductor components, especially transistors or logic gates, using a p-doped semiconductor substrate. First of all, a mask is applied to the semiconductor substrate in order to define a window that is delimited by a peripheral edge. An n-doped trough is then produced in the semiconductor substrate by means of ion implantation using an energy that is sufficient for ensuring that a p-doped inner area remains on the surface of the semiconductor substrate. The edge area of the n-doped trough extends as far as the surface of the semiconductor substrate. The other n-doped and/or p-doped areas that make up the structure of the transistor or logic gate are then inserted into the p-doped inner area of the semiconductor substrate. The inventive method is advantageous in that it no longer comprises expensive epitaxy and insulation processes. In an n-doped semiconductor substrate, all of the implanted ions are replaced by the complementary species; i.e.

Abstract: An GaN light emitting diode (LED) having a nanorod (or, nanowire) structure is disclosed. The GaN LED employs GaN nanorods in which a n-type GaN nanorod, an InGaN quantum well and a p-type GaN nanorod are subsequently formed in a longitudinal direction by inserting the InGaN quantum well into a p-n junction interface of the p-n junction GaN nanorod. In addition, a plurality of such GaN nanorods are arranged in an array so as to provide an LED having much greater brightness and higher light emission efficiency than a conventional laminated-film GaN LED.