Abstract: A pixel structure and its fabrication method are provided. The pixel structure includes a channel layer, a first patterned metal layer, a first insulation layer, a second patterned metal layer, a second insulation layer, and a pixel electrode. The first patterned metal layer includes a data line, a source, and a drain. The first insulation layer has a first opening exposing the drain. The second patterned metal layer includes a scan line and a capacitor electrode. The capacitor electrode has at least one first portion overlapping the data line. The second insulation layer has a second opening communicating with the first opening to expose the drain. The pixel electrode is connected to the drain through the first opening and the second opening and at least overlaps the first portion of the capacitor electrode.

Abstract: A pixel structure includes a substrate; a scan line; a gate electrode; an insulating layer disposed on the scan line, the gate electrode and the substrate; a channel and a data line disposed on the insulating layer; a source electrode and a drain electrode disposed on the channel; a passivation layer; a pixel electrode and a connecting electrode. The data line does not overlap the scan line. The passivation layer disposed on the source electrode and the drain electrode includes a first contact hole partially exposing the drain electrode, and a plurality of second contact holes partially exposing the data line or the scan line. The pixel electrode disposed on the passivation layer is electrically connected to the drain electrode through the first contact hole. Furthermore, the connecting electrode disposed on the passivation layer is electrically connected to the data line or the scan line through the second contact holes.

Abstract: A display device is manufactured with five photolithography steps: a step of forming a gate electrode, a step of forming a protective layer for reducing damage due to an etching step or the like, a step of forming a source electrode and a drain electrode, a step of forming a contact hole, and a step of forming a pixel electrode. The display device includes a groove portion which is formed in the step of forming the contact hole and separates the semiconductor layer.

Abstract: An OLED device includes: a TFT including an active layer, gate, source and drain electrodes, a first insulating layer between the active layer and the gate electrode, and a second insulating layer between the source and drain electrodes, a pixel electrode on the first and second insulating layers, connected to one of the source and drain electrodes, a capacitor including a first electrode on the same layer as the active layer, a second electrode on the same layer as the gate electrode, and a third electrode formed of the same material as the pixel electrode, a third insulating layer between the second insulating layer and the pixel electrode and between the second and third electrodes, a fourth insulating layer covering the source, drain and third electrodes, exposing a portion of the pixel electrode, an organic light-emitting layer on the pixel electrode, and a counter electrode on the organic light-emitting layer.

Abstract: An electro-optical device formed on a semiconductor substrate, includes: a first transistor controlling a current level according to a voltage between a gate and a source; a second transistor electrically connected between a data line and the gate of the first transistor; a third transistor electrically connected between the gate and a drain of the first transistor; and a light-emitting element emitting light at a luminance according to the current level, in which one of a source and a drain of the second transistor and one of a source and a drain of the third transistor are formed by a common diffusion layer.

Abstract: The display device includes a gate electrode, a gate insulating film provided over the gate electrode, a semiconductor film provided over the gate insulating film to overlap with the gate electrode, an island-shaped first insulating film provided over the semiconductor film to overlap with the gate electrode, a first conductive film provided over the semiconductor film, a pair of second conductive films which is provided over the semiconductor film and between which the first insulating film is sandwiched, and a second insulating film provided over the first insulating film, the first conductive film, and the pair of second conductive films. In the second insulating film and the semiconductor film, an opening portion which is positioned between the first conductive film and the one or the other of the pair of second conductive films is provided.

Abstract: In an electro-optical device substrate, first and second pixel switching elements each include a gate electrode formed of a first conductive film, a gate insulation film formed of a first insulation film, a semiconductor layer, a source electrode formed of a second conductive film, and a drain electrode formed of the second conductive film. A first storage capacitor includes a first storage capacitor electrode formed of the second conductive film, a protective film formed of a second insulation film so as to over at least the first storage capacitor electrode, and a pixel electrode formed so as to overlap with the first storage capacitor electrode at least partially with the protective film interposed therebetween.

Abstract: Disclosed is a high-quality, efficiently manufacturable thin film transistor in which leakage current is minimized. The thin film transistor is provided with a semiconductor layer (34) that contains a channel region (34C) having a microcrystalline semiconductor; source and drain contact layers (35S and 35D) that contains impurities; a first source metal layer (36S) and a first drain metal layer (36D), and a second source metal layer (37S) and a second drain metal layer (37D). The end portion of the second metal source layer (37S) is located at a position receded from the end portion of the first metal source layer (36S) and the end portion of the second drain metal layer (37D) is located at a position receded from the end portion of the first drain metal layer (36D). The semiconductor layer (34) contains low concentration impurity diffusion regions formed near the end portions of the aforementioned source contact layer (35S) and drain contact layer (35D).

Abstract: A TFT array substrate including: a thin-film transistor including an active layer, gate, source and drain electrodes, a first insulation layer between the active layer and the gate electrode, and a second insulation layer between the gate and the source and drain electrodes; a pixel electrode on the first and second insulation layers, and connected to one of the source and drain electrodes; a capacitor including a first electrode on the same layer as the gate electrode, a second electrode formed of the same material as the pixel electrode, a first protection layer on the second electrode, and a second protection layer on the first protection layer; a third insulation layer between the second insulation layer and the pixel electrode, and between the first electrode and the second electrode; and a fourth insulation layer covering the source and drain electrodes and the second protection layer, and exposing the pixel electrode.

Abstract: A display apparatus includes a plurality of first gate lines extended in a first direction and disposed on a substrate on which a plurality of pixels is disposed, a plurality of second gate line extended in a second direction to cross the first gate lines, a plurality of data lines disposed substantially parallel to the first gate lines, and a first insulating layer disposed between the first gate lines and the second gate lines and provided with a plurality of via holes to expose a portion of a corresponding first gate line of the first gate lines. Each of the first gate lines makes contact with a corresponding second gate line of the second gate lines through a corresponding via hole of the via holes.

Abstract: A fringe field switching (FFS) liquid crystal display (LCD) device which uses an organic insulating layer and consumes less power, in which film quality of an upper layer of a low temperature protective film is changed to improve undercut within a pad portion contact hole, and a method for fabricating the same is provided.

Abstract: On each of wiring conversion parts connected to a first conductive film and a second conductive film each functioning as a wiring, a first transparent conductive film does not cover an end surface of the second conductive film in proximity to a corner of the first transparent conductive film, and has a portion covering the end surface of the second conductive film on a portion other than the proximity of the corners. A second transparent conductive film as an upper layer of the first transparent conductive film is connected to the first conductive film and the second conductive film, so that the first conductive film and the second conductive film are electrically connected.

Abstract: A light-emitting microelectronic device including a first N-type transistor (T1) and a second P-type transistor (T2), the respective gates of which are formed opposite one another, either side of an intrinsic semiconductor material region.

Abstract: A display device includes a first substrate, a gate line disposed on the first substrate and including a gate electrode, a gate insulating layer disposed on the gate line, a semiconductor layer disposed on the gate insulating layer, a data line disposed on the semiconductor layer and connected to a source electrode, a drain electrode disposed on the semiconductor layer and facing the source electrode and a passivation layer disposed on the data line, in which the semiconductor layer is formed of an oxide semiconductor including indium, tin, and zinc. The indium is present in an amount of about 5 atomic percent (at %) to about 50 at % , and a ratio of the zinc to the tin is about 1.38 to about 3.88.

Abstract: Disclosed is an organic light emitting display device and a method of manufacturing the same. The organic light emitting display device includes the thin film transistor of the drive unit that has the activation layer formed in a structure where the first oxide semiconductor layer and the second oxide semiconductor layer are stacked, the thin film transistor of the pixel unit that has the activation layer formed of the second oxide semiconductor layer, and the organic light emitting diode coupled to the thin film transistor of the pixel unit. The thin film transistor of the drive unit has channel formed on the first oxide semiconductor layer having a higher carrier concentration than the second oxide semiconductor layer, having a high charge mobility, and the thin film transistor of the pixel unit has a channel formed on the second oxide semiconductor layer, having a stable and uniform functional property.

Abstract: Disclosed herein is a method for manufacturing an array substrate. The method includes forming a source electrode and a drain electrode on a substrate. A semiconductor layer, an organic insulating layer, and a gate electrode layer are sequentially formed to cover the substrate, the source electrode, and the drain electrode. A patterned photoresist layer is formed on the gate electrode layer. The exposed portion of the gate electrode layer, and a portion of the organic insulative layer and a portion of the semiconductor layer thereunder are removed to form a gate electrode. An organic passivation layer is formed on the gate electrode, the source electrode, and the drain electrode. The organic passivation layer has a contact window to expose a portion of the drain electrode. A pixel electrode is formed on the organic passivation layer and the exposed portion of the drain electrode.

Abstract: Disclosed are a thin film transistor array substrate and a manufacture method thereof. The thin film transistor array substrate comprises scan lines parallel with each other, data lines intersect with the scan lines insulatively and orthogonally, a pixel unit defined by any two adjacent scan lines and any two adjacent data lines, and a capacitor line between any two adjacent scan lines, wherein an elongate hole is along the capacitor line on the capacitor line, and at a junction of the capacitor line and the data line, and comprises auxiliary capacitor lines symmetrically arranged along the data line and at two sides of the capacitor line corresponding to two hole walls of the elongate hole. By employing the present invention, it is easy to cut off the connection between the auxiliary capacitor line and the capacitor line under circumstance without increasing the manufacture difficulty of the auxiliary capacitor line.

Abstract: A display panel having a non-display region and having a display region that includes a plurality of pixel regions, each of the pixel regions including a thin film transistor, the display panel including: an array substrate including the display region, the non-display region, a first base substrate including a gate line, a data line and a thin film transistor, an insulating layer covering the first base substrate, and a pixel electrode on the insulating layer; an opposite substrate over the array substrate; a light blocking pattern on the array substrate, the light blocking pattern surrounding the display region and intersecting the gate line and the data line; and an encapsulating element on the light blocking pattern, the encapsulating element bonding and sealing the array substrate and the opposite substrate, wherein: the thin film transistor is coupled to the gate line and the data line, the insulating layer has a contact hole exposing a drain electrode of the thin film transistor, and the pixel electrod

Abstract: A lower substrate for a liquid crystal display device and the method of making the same are disclosed. The method includes steps of: (a) providing a substrate; (b) forming a patterned transparent layer having plural recess on the substrate; (c) forming a first barrier layer on the surface of the recess; (d) coating a first metal layer on the first barrier layer and making the surfaces of the first metal layer and the transparent layer in substantially the same plane; and (e) forming a first insulated layer and a semi-conductive layer in sequence. The method further can optionally comprise the steps of: (f) forming a patterned second metal layer, wherein part of the semi-conductive layer is exposed, thus forming the source electrode and the drain electrode; and (g) forming a transparent electrode layer on part of the transparent layer and part of the second metal layer.

Abstract: To avoid a phenomenon of deterioration which is characteristic to an organic EL display device, such as a dark spot, without forming a pin hole in an organic material used for forming an organic EL layer. A reflective anode for an organic EL display device includes: an Ag-based alloy film (6) containing 0.01 to 1.5 atomic % of Nd and formed on a substrate (1); and an oxide conductive film (7) formed on the Ag-based alloy film (6) and in direct contact with the film (6).

Abstract: An active matrix substrate includes a substrate; a plurality of data lines provided on the substrate; a plurality of scanning lines provided to cross the data lines on the substrate when seen in a plan view; a thin film transistor that is electrically connected to one of the plurality of data lines and one of the plurality of scanning lines and has an organic semiconductor layer; a pixel electrode electrically connected to the thin film transistor; and a capacitive element electrically connected in parallel with the thin film transistor between the data line and the pixel electrode.

Abstract: A liquid crystal display panel and its manufacturing method are proposed. The liquid crystal display includes pixels, scan lines, and data lines. The scan lines are formed by a first metallic layer. Each pixel includes multiple subpixels. Each subpixel includes a pixel electrode, a thin-film transistor, and a common electrode line. The common electrode line includes a main branch, a first shielding metallic area, and a second shielding metallic area. The first and second shielding metallic areas are parallel to the scan lines and are connected to the main branch. The data lines and the common electrode lines are formed by the second metallic layer. The scan line and the common electrode line are formed after the first and second metallic layers undergo different etching processes, causing the distance between the scan line and the common electrode line to be shortened and the width of the common electrode line serving as a shielding metallic area partially to be properly decreased.

Abstract: A pixel structure and a manufacturing method thereof and a display panel are provided. An electrode material layer, a shielding material layer, an inter-layer dielectric material layer, a semiconductor material layer and a photoresist-layer are sequentially formed on a substrate. The semiconductor material layer, the inter-layer dielectric material layer, the shielding material layer and the electrode material layer are patterned using the photoresist-layer as a mask to form a semiconductor pattern, an inter-layer dielectric pattern, a shielding pattern and a pixel electrode. A source/drain electrically connected to the pixel electrode and covering a portion of the semiconductor pattern is formed on the pixel electrode. A channel is another portion of the semiconductor uncovered by the source/drain.

Abstract: The first transistor includes first and second electrodes which are a source and a drain, and a first gate electrode overlapping with a first channel formation region with an insulating film provided therebetween. The second transistor includes third and fourth electrodes which are a source and a drain, and a second channel formation region which is provided between a second gate electrode and a third gate electrode with insulating films provided between the second channel formation region and the second gate electrode and between the second channel formation region and the third gate electrode. The first and second channel formation regions contain an oxide semiconductor, and the second electrode is connected to the second gate electrode.

Abstract: A pixel structure including a scan line, a data line, an active device, a shielding electrode, and a pixel electrode is provided on a substrate. The data line includes an upper conductive wire and a bottom conductive wire. The upper conductive wire is disposed over and across the scan line. The bottom conductive wire is electrically connected to the upper conductive wire. The active device is electrically connected to the scan line and the upper conductive wire. The shielding electrode is disposed over the bottom conductive wire. The pixel electrode disposed over the shielding electrode is electrically connected to the active device. In addition, parts of the pixel electrode and parts of the shielding electrode form a storage capacitor.

Abstract: A method of manufacturing a display unit includes: forming, on a substrate, a thin-film transistor having an oxide semiconductor layer; and forming, above the thin-film transistor, a display region that includes a plurality of display elements. The oxide semiconductor layer is formed using a sputtering method in which a target and the substrate are opposed to each other. The target is made of an oxide semiconductor and includes a plurality of divided portions that are jointed in a planar form. A spacing interval between two joints that are formed by the plurality of divided portions and are side-by-side with one another of the target is equal to or less than a width of a luminance distribution arising in the display region in a direction substantially orthogonal to the joints.

Abstract: Carbon-based light emitting diodes (LEDs) and techniques for the fabrication thereof are provided. In one aspect, a LED is provided. The LED includes a substrate; an insulator layer on the substrate; a first bottom gate and a second bottom gate embedded in the insulator layer; a gate dielectric on the first bottom gate and the second bottom gate; a carbon material on the gate dielectric over the first bottom gate and the second bottom gate, wherein the carbon material serves as a channel region of the LED; and metal source and drain contacts to the carbon material.

Abstract: An array substrate includes a base substrate and a contact part. The contact part is disposed on the base substrate. The contact part includes a first metal pattern, a disconnection control pattern and a connecting pattern. The second metal pattern is disposed on a layer different from the first metal pattern, the disconnection control pattern overlaps a side surface of the second metal pattern and a connecting pattern is formed on the first and second metal patterns and the disconnection control pattern and connects the first metal pattern with the second metal pattern.

Abstract: Disclosed are a thin film transistor substrate and a method of fabricating the same in which the number of processes is reduced. The method includes forming a first conductive pattern including gate electrodes and gate lines on a substrate through a first mask process, depositing a gate insulating film and forming a second conductive pattern including a semiconductor pattern, source and drain electrodes and data lines through a second mask process, depositing first and second passivation films and forming pixel contact holes passing through the first and second passivation films and exposing the drain electrodes through a third mask process, and forming a third conductive pattern including a common electrode and a common line and forming a third passivation film formed in an undercut structure with the common electrode through a fourth mask process, simultaneously, and forming a fourth conductive pattern including pixel electrodes through a lift-off process.

Abstract: The present invention relates to a thin film transistor array panel and a manufacturing method thereof that prevent disconnection of wiring due to misalignment of a mask, and simplify a process and reduce cost by reducing the number of masks. The thin film transistor array panel according to the disclosure includes a source electrode enclosing an outer part of the first contact hole and formed on the second insulating layer; a drain electrode enclosing an outer part of the second contact hole and formed on the second insulating layer; a first connection electrode connecting the source region of the semiconductor layer and the source electrode through the first contact hole; and a second connection electrode connecting the drain region of the semiconductor layer and the drain electrode through the second contact hole.

Abstract: In a thin film transistor substrate, an active pattern of a thin film transistor includes a lower semiconductor pattern and an upper semiconductor pattern that are patterned through different process steps. The lower semiconductor pattern defines a channel area of the thin film transistor, and the upper semiconductor pattern is connected to a side portion of the lower semiconductor pattern and makes contact with the source electrode and the drain electrode. An etch stop layer is formed on the lower semiconductor pattern corresponding to the channel area, and the etch stop layer is formed through the same patterning process as the lower semiconductor pattern. Also, an ohmic contact pattern is formed on the upper semiconductor pattern, and the ohmic contact pattern is formed by the same patterning process as the upper semiconductor pattern.

Abstract: A pixel structure of a display panel includes a substrate, a thin film transistor (TFT), a first transparent connecting pad, a passivation layer and a transparent pixel electrode. The TFT disposed on the substrate includes a gate electrode, a gate insulating layer, a semiconductor layer, a source electrode and a drain electrode. The gate insulating layer is disposed on the gate electrode, the semiconductor layer is disposed on the gate insulating layer, and the source electrode and the drain electrode are disposed on the semiconductor layer. The first transparent connecting pad disposed on the drain electrode partially overlaps and is electrically connected to the drain electrode. The passivation layer disposed on the first transparent connecting pad includes at least a contact hole. Furthermore, the transparent pixel electrode disposed on the passivation layer is electrically connected to the first transparent connecting pad through the contact hole of the passivation layer.

Abstract: A thin-film transistor array includes first and second bottom-gate transistors, a passivation film, a conductive oxide film below the passivation film, and a relay electrode between a first conductive material in a same layer as a first electrode of the first transistor and a second conductive material in an electroluminescence layer. A first line is in a layer lower than the passivation film and a second line is above the passivation film. A terminal to which an external signal is input is provided in a periphery of the substrate in the same layer as the first electrode. The conductive oxide film covers an upper surface of the terminal and is between the relay electrode and the first conductive material. The relay electrode is formed in a same layer and comprises a same material as the second line.

Abstract: A display substrate including a base substrate, a plurality of pixel electrodes and a plurality of sub pixel electrodes. The pixel electrodes are formed on the base substrate, are spaced apart from each other, and are electrically connected with a plurality of transistors, respectively. The sub pixel electrodes are disposed between the pixel electrodes, and are electrically connected with a thin-film transistor (TFT). Thus, quality of an image displayed by the display apparatus may be enhanced.

Abstract: Each pixel region includes first and second pixel electrodes (17a, 17b) and first and second capacitor electrodes (67x, 67y) positioned on a layer where a data signal line (15) exists. The first and second capacitor electrodes are aligned in a row direction in such a manner as to overlap a retention capacitor line (18) via a first insulating film and to overlap the second pixel electrode (17b) via a second insulating film. A drain electrode (9) of a transistor (12), the first pixel electrode (17a), a first connection line (38) connected with the first capacitor electrode (67x), and the second connection line connected with the second capacitor electrode (67y) are electrically connected with one another. A part of the first connection line (38) and a part of the second connection line (39) do not overlap the retention capacitor line (18).

Abstract: A manufacturing method of a liquid crystal display includes: forming a thin film transistor on a first substrate; forming a color filter on the thin film transistor; forming a pixel electrode on the color filter; and forming a light blocking member including a column spacer protruded from the light blocking member on the color filter. The forming the light blocking member uses a mask including a first region, a second region, and a third region. The first region passes light generated from a light exposer, the second region includes a blocking filter layer which selectively passes the light generated from the light exposer, and the third region blocks the light generated from the light exposer.

Abstract: According to one embodiment, a method is disclosed for manufacturing a display device. A film material layer is formed on a support substrate. A first heating process for the film material layer at a first temperature to form a film layer and a second heating process for a second region surrounding a first region at a second temperature higher than the first temperature are performed. The first region is provided in a central part of the film layer. A display layer is formed in the first region and a peripheral circuit section is formed at least in a part of the second region. A third heating process is performed for at least a part of the film layer at a third temperature higher than the second temperature. In addition, the film layer is peeled off from the support substrate.

Abstract: A pixel structure disposed on a substrate having an array of pixel areas is provided. The common electrode wire is positioned only in a portion of the pixel area. A first capacitance storage electrode is disposed in each of the pixel areas and electrically connected between two adjacent common electrode wires. A gate insulation layer covers the scan line, the gate electrode, the common electrode wire and the first capacitance storage electrode. A semiconductor layer is disposed on the gate insulation layer above the gate electrode. The source and the drain are disposed on two sides of the semiconductor layer. A passivation layer is disposed on the substrate to cover the data line, the source and the drain. The passivation layer above the drain has a contact window. A pixel electrode is electrically connected with the drain through the contact window.

Abstract: A transistor substrate and a method of manufacturing the transistor substrate. The transistor substrate includes a semiconductor layer arranged on a base layer, a first layer arranged on the semiconductor layer and having a first light transmissivity, source and drain electrodes, the source electrode arranged on a first side of the semiconductor layer and extending onto a first portion of the first layer, the drain electrode arranged on a second and opposite side of the semiconductor layer and extending onto a second portion of the first layer and separated from the source electrode by a distance, a second layer arranged between the first layer and the source and drain electrodes and having a second light transmissivity that is lower than the first light transmissivity, a gate insulating layer arranged on the first layer and a gate electrode arranged on the gate insulating layer.

Abstract: A thin film transistor array substrate includes a gate line disposed on a substrate, the gate line comprising a gate electrode including a lower film and an upper film thicker than the lower film, a gate insulating layer formed on the gate line, a semiconductor layer formed on the gate insulating layer, an ohmic contact layer formed on the semiconductor layer, a data line electrically connected to a source electrode and a drain electrode formed on the ohmic contact layer, the lower film of the gate line is in contact with the gate insulating layer at a crossing portion of the gate line and the data line and the heights of the source electrode and the drain electrode are substantially the same as or less than a height of the semiconductor layer.

Abstract: A fabricating method of a pixel structure is provided. A substrate has an array of pixel areas. The common electrode wire is positioned only in a portion of the pixel area. A first capacitance storage electrode is formed in each of the pixel areas and electrically connected between two adjacent common electrode wires. A gate insulation layer covers the scan line, the gate electrode, the common electrode wire and the first capacitance storage electrode. A semiconductor layer is formed on the gate insulation layer above the gate electrode. The source and the drain is formed on two sides of the semiconductor layer. A passivation layer is formed on the substrate to cover the data line, the source and the drain. A pixel electrode is formed in each of the pixel areas, and the pixel electrode is electrically connected with the drain through the contact window.

Abstract: A thin film transistor array panel includes a gate line and the driver connection line formed with the same layer material, a data line and a driving pad formed with the same layer material, a first field generating electrode and a connecting member formed with the same layer material, and a second field generating electrode and a dummy electrode layer formed with the same layer material.

Abstract: The invention discloses a method of manufacturing TFT array substrate and a TFT array substrate, wherein the manufacturing method comprises the following steps: sequentially depositing a metal film, a insulating layer, and a semiconductor layer, and manufacturing a gate line and a gate electrode using a composition method; depositing a insulating layer, and manufacturing a channel region protecting layer using the composition method; sequentially depositing a doped semiconductor layer and a metal layer; forming a source electrode, a drain electrode and a data line using the composition method; and cutting the doped semiconductor layer and the metal layer to form an energizing channel; and depositing an ITO layer, and forming a pixel electrode by the ITO layer using the composition method.

Abstract: The present invention improves the aperture ratio of a pixel of a reflection-type display device or a reflection type display device without increasing the number of masks and without using a blackmask. A pixel electrode (167) is arranged so as to partially overlap a source wiring (137) for shielding the gap between pixels from light, and a thin film transistor is arranged so as to partially overlap a gate wiring (166) for shielding a channel region of the thin film transistor from light, thereby realizing a high pixel aperture ratio.

Abstract: In an oxide semiconductor layer, a degree of oxidation S1 of a portion located on the side of the gate insulating film, and a degree of oxidation S2 of surface layer portions located in connection regions with source and drain electrodes have a relation of S2<S1 within a range in which the oxide semiconductor layer has predetermined electric resistance, and a degree of oxidation S3 of a surface layer portion of the channel region is made higher than the degrees of oxidation S1, S2 of the other regions within the range in which the oxide semiconductor layer has the predetermined electric resistance, by annealing the oxide semiconductor layer in an oxygen-containing atmosphere after formation of the source electrode and the drain electrode.

Abstract: A method of manufacturing an LCD device includes providing a lower substrate including a first substrate on which a thin film transistor, a pixel electrode, and a common electrode are formed, and forming a first light alignment layer on the first substrate that is light aligned in a ultraviolet (UV) irradiation process; providing an upper substrate including a second substrate on which a color filter and a black matrix are formed, and forming a second light alignment layer on the second substrate that is light aligned in the UV irradiation process; providing a light polymerization compound between the lower substrate and upper substrate; and forming an alignment assistant layer between a liquid crystal layer and the first and second light alignment layers by performing a front UV irradiation process on the upper substrate and lower substrate which are coupled to each other with the liquid crystal layer therebetween.

Abstract: The present invention provides a thin film transistor array panel comprising an insulating substrate; a gate line formed on the insulating substrate; a gate insulating layer formed on the gate line; a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode being adjacent to the source electrode with a gap therebetween; and a pixel electrode coupled to the drain electrode, wherein at least one of the gate line, the data line, and the drain electrode comprises a first conductive layer comprising a conductive oxide and a second conductive layer comprising copper (Cu).

Abstract: Provided is a thin film transistor capable of improving reliability in the thin film transistor including an oxide semiconductor layer. A thin film transistor including: a gate electrode; a gate insulating film formed on the gate electrode; an oxide semiconductor layer forming a channel region corresponding to the gate electrode on the gate insulating film; a channel protective film formed at least in a region corresponding to the channel region on the oxide semiconductor layer; and a source/drain electrode. A top face and a side face of the oxide semiconductor layer are covered with the source/drain electrode and the channel protective layer on the gate insulating film.

Abstract: A display apparatus includes a first substrate including a plurality of pixels, a first electrode arranged on the first substrate, a second substrate facing the first substrate, and a second electrode arranged on the second substrate and spaced apart from the first electrode, the second electrode to form an electric field in cooperation with the first electrode. At least one of the first and second electrodes includes a transparent conductive nanomaterial having a transmittance of no less than 73% to no more than 100% and a sheet resistance of 0 ohms to 100 ohms.

Abstract: At present, a forming process of a base film through an amorphous silicon film is conducted in respective film forming chambers in order to obtain satisfactory films. When continuous formation of the base film through the amorphous silicon film is performed in a single film forming chamber with the above film formation condition, crystallization is not sufficiently attained in a crystallization process. By forming the amorphous silicon film using silane gas diluted with hydrogen, crystallization is sufficiently attained in the crystallization process even with the continuous formation of the base film through the amorphous silicon film in the single film forming chamber.