Characterized By Material (epo) Patents (Class 257/E39.006)
  • Patent number: 11104976
    Abstract: A bi-continuous composite of a refractory alloy and copper, and a method for manufacturing the same, are provided. The method for manufacturing a bi-continuous composite of a refractory alloy and copper includes: providing an alloy melt swapping (AMS) precursor; providing a copper melt with a temperature in a range of 1085° C. to 3410° C.; immersing the AMS precursor into the copper melt; and removing the AMS precursor from the copper melt. The AMS precursor includes elements having positive and negative mixing enthalpy with copper, respectively. The AMS precursor into which the copper melt is diffused becomes a bi-continuous composite with a first phase formed from the copper and a second phase formed from the AMS precursor.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: August 31, 2021
    Assignee: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Kooknoh Yoon, Il-Hwan Kim, Hyun Seok Oh, Sang Jun Kim, Eun Soo Park
  • Patent number: 8471245
    Abstract: An implementation of a single qubit phase gate for use in a quantum information processing scheme based on the ?=5/2 fractional quantum Hall (FQH) state is disclosed. Using sack geometry, a qubit consisting of two ?-quasiparticles, which may be isolated on respective antidots, may be separated by a constriction from the bulk of a two-dimensional electron gas in the ?=5/2 FQH state. An edge quasiparticle may induce a phase gate on the qubit. The number of quasiparticles that are allowed to traverse the edge path defines which gate is induced. For example, if a certain number of quasiparticles are allowed to traverse the path, then a ?/8 gate may be effected.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: June 25, 2013
    Assignee: Microsoft Corporation
    Inventors: Parsa Bonderson, Kirill Shtengel, David Clarke, Chetan Nayak
  • Publication number: 20120112168
    Abstract: Computing bus devices that enable quantum information to be coherently transferred between topological and conventional qubits are disclosed. A concrete realization of such a topological quantum bus acting between a topological qubit in a Majorana wire network and a conventional semiconductor double quantum dot qubit is described, The disclosed device measures the joint (fermion) parity of the two different qubits by using the Aharonov-Casher effect in conjunction. with an ancillary superconducting flux qubit that facilitates the measurement. Such a parity measurement, together with the ability to apply Hadamard gates to the two qubits, allows for the production of states in which the topological and conventional qubits are maximally entangled, and for teleporting quantum states between the topological and conventional quantum systems.
    Type: Application
    Filed: November 9, 2011
    Publication date: May 10, 2012
    Applicant: MICROSOFT COPORATION
    Inventors: Parsa Bonderson, Roman Lutchyn
  • Publication number: 20120049162
    Abstract: An implementation of a single qubit phase gate for use in a quantum information processing scheme based on the ?=5/2 fractional quantum Hall (FQH) state is disclosed. Using sack geometry, a qubit consisting of two ?-quasiparticles. which may be isolated on respective antidots, may be separated by a constriction from the bulk of a two-dimensional electron gas in the ?=5/2 FQH state. An edge quasiparticle may induce a phase gate on the qubit. The number of quasiparticles that are allowed to traverse the edge path defines which gate is induced. For example, if a certain number of quasiparticles are allowed to traverse the path, then a ?/8 gate may be effected.
    Type: Application
    Filed: November 8, 2011
    Publication date: March 1, 2012
    Applicant: Microsoft Corporation
    Inventors: Parsa Bonderson, Kirill Shtengel, David Clarke, Chetan Nayak
  • Publication number: 20120035057
    Abstract: Methods and apparatus characterized by distinct operating modes are provided. A thin graphite material defined by graphene layers is supported on a silicon substrate. The graphite material is defined by edge sites at the interface with the silicon. The graphite material is characterized by electrical superconductive-like behavior at room-temperatures while electrical current flows there through in a first direction. The graphite material is further characterized by a transition to Ohmic behavior while electrical current flows there through in a second direction opposite to the first. Devices exhibiting diode-like behavior can be formed accordingly.
    Type: Application
    Filed: August 3, 2010
    Publication date: February 9, 2012
    Inventors: Alexandre Bratkovski, Iakov Kopelevitch
  • Publication number: 20120012818
    Abstract: A Josephson device includes a first superconducting electrode layer, a barrier layer, and a second superconducting electrode layer that are successively stacked. The first and second superconducting electrode layers are made of an oxide superconductor material having (RE)1(AE)2Cu3Oy as a main component, where an element RE is at least one element selected from a group consisting of Y, La, Pr, Nd, Sm, Eu, Gd, Dy, Ho, Er, Tm, Yb and Lu, and an element AE is at least one element selected from a group consisting of Ba, Sr and Ca. The barrier layer is made of a material that includes the element RE, the element AE, Cu and oxygen, where the barrier layer has a composition different from compositions of the first and second superconducting electrode layers.
    Type: Application
    Filed: August 31, 2011
    Publication date: January 19, 2012
    Inventors: Hironori WAKANA, Seiji Adachi, Koji Tsubone, Keiichi Tanabe
  • Publication number: 20110129945
    Abstract: The invention describes a method of achieving superconductivity in Group IV semiconductors via the addition of doubly charged impurity atoms to the crystal lattice. The doubly charged impurities function as composite bosons in the semiconductor. Increasing the density of the composite bosons to a level where their wavefunctions overlap, results in the formation of a Bose condensate. The concentration of the doubly charged impurity atoms in the host lattice and the binding energy of the impurities are important factors in determining whether a Bose condensate will form. Doubly charged impurities must be present in the semiconductor at a concentration at which they exhibit overlapping wavefunctions, but still exist within the crystal lattice as bosons.
    Type: Application
    Filed: November 29, 2010
    Publication date: June 2, 2011
    Inventor: William Griffin Wise
  • Patent number: 7884450
    Abstract: A process for growth of boron-based nanostructures, such as nanotubes and nanowires, with a controlled diameter and with controlled chemical (such as composition, doping) as well as physical (such as electrical and superconducting) properties is described. The boron nanostructures are grown on a metal-substituted MCM-41 template with pores having a uniform pore diameter of less than approximately 4 nm, and can be doped with a Group Ia or Group IIa electron donor element during or after growth of the nanostructure. Preliminary data based on magnetic susceptibility measurements suggest that Mg-doped boron nanotubes have a superconducting transition temperature on the order of 100 K.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: February 8, 2011
    Assignee: Yale University
    Inventors: Lisa Pfefferle, Dragos Ciuparu
  • Publication number: 20100171098
    Abstract: A pressure detection apparatus (30) detects, among a plurality of superconductor thin films (11 to 14) having different critical pressures at which a transition from a superconductor to an insulator occurs, the superconductor thin films (12 to 14) that have undergone the transition to the insulator with ammeters (242, 252, 262); and to detect, as an internal pressure of a housing (10), the maximum critical pressure among the critical pressures of the detected superconductor thin films (12 to 14).
    Type: Application
    Filed: July 31, 2008
    Publication date: July 8, 2010
    Inventor: Takashi Suzuki
  • Patent number: 7741634
    Abstract: A Josephson junction (JJ) device includes a buffered substrate comprising a first buffer layer formed on a substrate. A second buffer layer is formed on the first buffer layer. The second buffer layer includes a hexagonal compound structure. A trilayer structure is formed on the buffered substrate comprising at least two layers of a superconducting material. A thin tunnel barrier layer is positioned between the at least two layers. The buffered substrate is used to minimize lattice mismatch and interdiffusion in the trilayer structure so as to allow the JJ device to operate above 20 K.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: June 22, 2010
    Assignee: Massachusetts Institute of Technology
    Inventors: Heejae Shim, Jagadeesh S. Moodera
  • Patent number: 7544964
    Abstract: A method for producing a thin layer device such as a superconductive device excellent in mechanical strength and useful as a submillimeter band receiver is provided. The thin layer device is produced by forming a multilayer structure substance comprising an NbN/MgO/NbN-SIS junction on an MgO temporary substrate, then forming SiO2, as a substrate, on said multilayer structure substance, and subsequently removing the MgO temporary substrate by etching. A superconductive device (a thin layer device) produced by a method of the present invention has excellent performance and high mechanical strength, and therefore introduction to a waveguide for a submillimeter band is also easy.
    Type: Grant
    Filed: September 25, 2006
    Date of Patent: June 9, 2009
    Assignee: National Institute of Information and Communications Technology, Incorporated Administrative Agency
    Inventor: Akira Kawakami
  • Patent number: 7531892
    Abstract: A process for growth of boron-based nanostructures, such as nanotubes and nanowires, with a controlled diameter and with controlled chemical (such as composition, doping) as well as physical (such as electrical and superconducting) properties is described. The boron nanostructures are grown on a metal-substituted MCM-41 template with pores having a uniform pore diameter of less than approximately 4 nm, and can be doped with a Group Ia or Group IIa electron donor element during or after growth of the nanostructure. Preliminary data based on magnetic susceptibility measurements suggest that Mg-doped boron nanotubes have a superconducting transition temperature on the order of 100 K.
    Type: Grant
    Filed: December 13, 2004
    Date of Patent: May 12, 2009
    Assignee: Yale University
    Inventors: Lisa Pfefferle, Dragos Ciuparu
  • Publication number: 20070254813
    Abstract: A superconductor has a conductive path with a metallic substrate strip, a super-conductive layer made of a AB2CU3Ox type high-Tc-super conductive material, at least one insulating buffer layer which is arranged therebetween, and a metallic cover layer which is arranged thereon. At least one contacting element made of a normal conductive contacting material and arranged at least on one longitudinal side of the structure between the cover layer and the substrate strip enables a predetermined normally conductive limitation of the current-limiting device to be obtained.
    Type: Application
    Filed: September 27, 2005
    Publication date: November 1, 2007
    Inventors: Hans-Peter Kramer, Wolfgang SChmidt
  • Patent number: 6777808
    Abstract: The self inductance associated with a capacitance A52 in a superconductor integrated circuit (FIG. 1) is reduced by adding a layer of superconductor metal (A54) overlying the capacitor, effectively producing a negative inductance to counteract the self-inductance of the capacitor leads, thereby reducing inductance of the circuit. As a result it possible to transfer a single flux quantum (“SFQ”) pulse through the capacitor. Capacitors (19 and 25 FIG. 5) of the foregoing type are incorporated in superconductor integrated circuit SFQ transmission lines (FIG. 5) to permit SQUID-to-SQUID transfer of SFQ pulses, while maintaining the circuit grounds of the respective SQUIDs in DC isolation. Bias current (10) may be supplied to multiple SQUIDs (1 & 3, 7 & 9 FIG. 5) serially, reducing the supply current required previously for operation of multiple SQUIDs.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: August 17, 2004
    Assignee: Northrop Grumman Corporation
    Inventors: Quentin P. Herr, Lynn A. Abelson, George L. Kerber