Abstract: Some embodiments include a memory cell having a first electrode, and an intermediate material over and directly against the first electrode. The intermediate material includes stabilizing species corresponding to one or both of carbon and boron. The memory cell also has a switching material over and directly against the intermediate material, an ion reservoir material over the switching material, and a second electrode over the ion reservoir material. Some embodiments include methods of forming memory cells.
Type:
Grant
Filed:
June 8, 2016
Date of Patent:
November 15, 2016
Assignee:
Micron Technology, Inc.
Inventors:
Martin Schubert, Shu Qin, Scott E. Sills, Durai Vishak Nirmal Ramaswamy, Allen McTeer, Yongjun Jeff Hu
Abstract: Some embodiments include a memory cell having a first electrode, and an intermediate material over and directly against the first electrode. The intermediate material includes stabilizing species corresponding to one or both of carbon and boron. The memory cell also has a switching material over and directly against the intermediate material, an ion reservoir material over the switching material, and a second electrode over the ion reservoir material. Some embodiments include methods of forming memory cells.
Type:
Grant
Filed:
October 15, 2015
Date of Patent:
July 5, 2016
Assignee:
Micron Technology, Inc.
Inventors:
Martin Schubert, Shu Qin, Scott E. Sills, Durai Vishak Nirmal Ramaswamy, Allen McTeer, Yongjun Jeff Hu
Abstract: A method for forming an interconnect structure includes forming a dielectric material layer on a semiconductor substrate. An oxygen-rich layer is formed over the dielectric material layer. The dielectric material layer and the oxygen-rich layer are patterned to form a plurality of vias in the semiconductor substrate. A barrier layer is formed in the plurality of vias and on the dielectric material layer leaving a portion of the oxygen-rich layer exposed. A metal layer is formed on the barrier layer and on the exposed portion of the oxygen-rich layer, wherein the metal layer fills the plurality of vias. The semiconductor substrate is annealed at a predetermined temperature range and at a predetermined pressure to transform the exposed portion of the oxygen-rich layer into a metal-oxide stop layer.
Abstract: A thin film capacitance element composition, wherein a bismuth layer compound having a c-axis oriented vertically with respect to a substrate surface is expressed by a composition formula of (Bi2O2)2+(Am?1BmO3m+1)2? or Bi2Am?1BmO3m+3, wherein “m” is an even number, “A” is at least one element selected from Na, K, Pb, Ba, Sr, Ca and Bi, and “B” is at least one element selected from Fe, Co, Cr, Ga, Ti, Nb, Ta, Sb, V, Mo and W; and Bi in the bismuth layer compound is excessively included with respect to the composition formula of (Bi2O2)2+(Am?1BmO3m+1)2? or Bi2Am?1BmO3m+3, and the excessive content of Bi is in a range of 0<Bi<0.5×m mol in of Bi.
Abstract: A method of manufacturing a ceramic includes forming a film which includes a complex oxide material having an oxygen octahedral structure and a paraelectric material having a catalytic effect for the complex oxide material in a mixed state, and performing a heat treatment to the film, wherein the paraelectric material is one of a layered catalytic substance which includes Si in the constituent elements and a layered catalytic substance which includes Si and Ge in the constituent elements. The heat treatment includes sintering and post-annealing. At least the post-annealing is performed in a pressurized atmosphere including at least one of oxygen and ozone. A ceramic is a complex oxide having an oxygen octahedral structure, and has Si and Ge in the oxygen octahedral structure.