Multilayered Structures, E.g., Super Lattices (epo) Patents (Class 257/E39.011)
  • Patent number: 10706991
    Abstract: There is provided a technique for producing a superconducting wire material in which the yield in a process of joining superconducting wire materials is improved over the related art. A method for producing a superconducting wire material lengthened by joining end portions of superconducting wire materials each having an oxide superconducting film, the end portions serving as joining surfaces, includes a step of disposing a micro-crystal of an oxide superconducting material on each of the joining surfaces of the oxide superconducting films, a pasting step of overlapping and pasting together the joining surfaces on which the micro-crystal is disposed, and a heat joining step of heating the overlapped joining surfaces to grow the micro-crystal, thereby forming, as a joining layer, a superconducting layer of the oxide superconducting material to join the joining surfaces to each other.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: July 7, 2020
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kotaro Ohki, Tatsuoki Nagaishi
  • Patent number: 10410781
    Abstract: According to an embodiment, a superconductor includes a base member, and a superconducting layer provided on the base member. The superconducting Layer has a first surface on the base member side, and a second surface on the side opposite to the first surface. The lattice constant of the base member substantially matches the lattice constant of the superconducting layer. The superconducting layer includes REA1-xREBxBa2Cu3O7-z. The x is not less than 0.01 and not more than 0.40. The z is not less than 0.02 and not more than 0.20. The REA includes at least one of Y, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, or Lu. The REB includes at least one of Nd or Sm. The superconducting layer includes a first surface-side region including a portion of the first surface. The first surface-side region includes a first region having an orientation property, and a second region.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: September 10, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Araki, Hiroyuki Fuke
  • Patent number: 10181647
    Abstract: An antenna apparatus can include a transmission medium that is positioned within layers of an antenna apparatus that are positioned adjacent to a first upper layer that is configured to include a signal receiving and transmission element (e.g. an antenna, patch antenna, etc.). The transmission medium can include or otherwise be connected to one or more resonators so that only a signal within a pre-selected band is passable through the transmission band. Any signal in a band outside of the pre-selected band may not be passable through the transmission medium due at least in part to the resonators. In some embodiments, the transmission medium may be part of a stripline or a microstrip. Embodiments of the apparatus may also be configured to block backward radiation emittable from the antenna to help prevent a body of a person near that device from absorbing such radiation.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: January 15, 2019
    Assignee: The Penn State Research Foundation
    Inventors: Douglas H. Werner, Zhihao Jiang
  • Patent number: 9558873
    Abstract: A method for manufacturing a superconducting wire material in which the superconducting current is not saturated even when a superconducting layer is made into a thick film, and a superconducting wire material. In the method a superconducting layer is formed on a metal substrate interposed by an intermediate layer, the method including heating the metal substrate up to the film-formation temperature of a superconducting film for forming the superconducting layer, forming a superconducting film having a film thickness of at least 10 nm and no more than 200 nm on the intermediate layer, and reducing the metal substrate temperature to a level below the film-formation temperature of the superconducting film, and the superconducting film-formation, including the heating, the film-formation, and the cooling, are performed a plurality of times.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: January 31, 2017
    Assignees: FURUKAWA ELECTRIC CO., LTD., CHUBU ELECTRIC POWER COMPANY, INCORPORATED
    Inventors: Ryusuke Nakasaki, Akinobu Nakai, Tomonori Watanabe, Naoji Kashima, Shigeo Nagaya
  • Patent number: 7692181
    Abstract: A number of light-emitting layer structures for the GaN-based LEDs that can increase the lighting efficiency of the GaN-based LEDs on one hand and facilitate the growth of epitaxial layer with better quality on the other hand are provided. The light-emitting layer structure provided is located between the n-type GaN contact layer and the p-type GaN contact layer. Sequentially stacked on top of the n-type GaN contact layer is the light-emitting layer containing a lower barrier layer, at least one intermediate layer, and an upper barrier layer. That is, the light-emitting layer contains at least one intermediate layer interposed between the upper and lower barrier layers. When there are multiple intermediate layers inside the light-emitting layer, there is an intermediate barrier layer interposed between every two immediately adjacent intermediate layers.
    Type: Grant
    Filed: July 19, 2006
    Date of Patent: April 6, 2010
    Assignee: Formosa Epitaxy Incorporation
    Inventors: Cheng-Tsang Yu, Liang-Wen Wu, Tzu-Chi Wen, Fen-Ren Chien
  • Patent number: 7202494
    Abstract: A semiconductor device may include at least one fin field-effect transistor (FINFET) comprising a fin, source and drain regions adjacent opposite ends of the fin, and a gate overlying the fin. The fin may include at least one superlattice including a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: April 10, 2007
    Assignee: RJ Mears, LLC
    Inventors: Richard A. Blanchard, Kalipatnam Vivek Rao, Scott A. Kreps
  • Patent number: 6913947
    Abstract: A multi-layer circuit board is manufactured by laminating and bonding together a plurality of resin films, on each of which a circuit pattern is directly drawn by injecting ink. The ink includes metal particles, having a diameter in the order of nanometers, dispersed therein. At the same time when the laminated resin films are bonded together under pressure and heat, the metal particles in the ink are sintered, thereby forming a solid electrical circuit printed on the resin film. Since the circuit pattern is directly drawn on the resin film, the process of manufacturing the multi-layer circuit board is simplified.
    Type: Grant
    Filed: October 8, 2003
    Date of Patent: July 5, 2005
    Assignee: Denso Corporation
    Inventor: Masashi Totokawa
  • Patent number: 6777808
    Abstract: The self inductance associated with a capacitance A52 in a superconductor integrated circuit (FIG. 1) is reduced by adding a layer of superconductor metal (A54) overlying the capacitor, effectively producing a negative inductance to counteract the self-inductance of the capacitor leads, thereby reducing inductance of the circuit. As a result it possible to transfer a single flux quantum (“SFQ”) pulse through the capacitor. Capacitors (19 and 25 FIG. 5) of the foregoing type are incorporated in superconductor integrated circuit SFQ transmission lines (FIG. 5) to permit SQUID-to-SQUID transfer of SFQ pulses, while maintaining the circuit grounds of the respective SQUIDs in DC isolation. Bias current (10) may be supplied to multiple SQUIDs (1 & 3, 7 & 9 FIG. 5) serially, reducing the supply current required previously for operation of multiple SQUIDs.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: August 17, 2004
    Assignee: Northrop Grumman Corporation
    Inventors: Quentin P. Herr, Lynn A. Abelson, George L. Kerber