Semiconductor Or Solid-state Devices Using Galvano-magnetic Or Similar Magnetic Effects, Processes Or Apparatus Peculiar To Manufacture Or Treatment Of Such Devices, Or Of Parts Thereof (epo) Patents (Class 257/E43.001)
  • Publication number: 20120206837
    Abstract: A magnetoresistive element includes a lamination body and a pair of electrodes. The lamination body includes a first magnetic layer, a second magnetic layer, and a spacer layer. The spacer layer is provided between the first magnetic layer and the second magnetic layer and includes an oxide layer. The oxide layer includes at least one element selected from the group consisting of Zn, In, Sn, and Cd, and at least one element selected from the group consisting of Fe, Co, and Ni.
    Type: Application
    Filed: September 15, 2011
    Publication date: August 16, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshihiko FUJI, Michiko Hara, Hideaki Fukuzawa, Hiromi Yuasa, Shuichi Murakami
  • Patent number: 8199568
    Abstract: A hard disk drive with a disk base including a disk wall with a first intake, a second intake off of the first intake, an outlet and an air filter configured to receive a first airflow from the first intake and suction from a second airflow from the second intake creating negative pressure at a trapping surface of the air filter away from the outlet. At least one disk rotates to create a rotating disk surface generating airflow configured to enter the first intake to create the first airflow. A disk damper includes an enclosing wall neighboring the air filter to create a flow chamber providing a third airflow through the outlet formed of the first air flow crossing the trapping surface and the second air flow. A disk cover mounts on the disk base to encapsulate the air chamber. The disk base and disk damper are disclosed.
    Type: Grant
    Filed: January 23, 2009
    Date of Patent: June 12, 2012
    Inventors: Haesung Kwon, Jaesuk Lee, Seong-Woo Kang, Hyung Jai Lee
  • Publication number: 20120139019
    Abstract: A method of manufacturing a magnetoresistive effect element includes forming a first electrode above a substrate, forming a metal layer of a metal material above the first electrode, forming a first magnetic layer above the metal layer, forming a tunnel insulating film above the first magnetic layer, forming a second magnetic layer above the tunnel insulating film, forming a second electrode layer above the second magnetic layer, patterning the second electrode layer, patterning the second magnetic layer, the tunnel insulating film, the first magnetic layer and the metal layer, while depositing sputtered particles of the metal film on side walls of the second magnetic layer, the tunnel insulating film, the first magnetic layer and the metal layer to form a sidewall metal layer, and oxidizing the sidewall metal layer to form an insulative sidewall metal oxide layer.
    Type: Application
    Filed: November 7, 2011
    Publication date: June 7, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Yoshihisa IBA
  • Patent number: 8193598
    Abstract: Nano-scale and multi-scale computational architectures using spin waves as a physical mechanism for device interconnection are provided. Solid-state spin-wave computing devices using nano-scale and multi-scale computational architectures comprised of a plurality of inputs and a plurality of outputs are described where such devices are configured to simultaneously transmit data elements from the inputs to the outputs by using spin-waves of differing frequencies. These devices include but are not limited to a spin-wave crossbar, a spin-wave reconfigurable mesh, a spin-wave fully-interconnected cluster, a hierarchical multi-scale spin-wave crossbar, a hierarchical multi-scale spin-wave reconfigurable mesh and a hierarchical multi-scale spin-wave fully-interconnected cluster.
    Type: Grant
    Filed: November 4, 2008
    Date of Patent: June 5, 2012
    Assignee: The Regents of the University of California
    Inventors: Mary M. Eshaghian-Wilner, Alexander Khitun, Kang L. Wang
  • Patent number: 8178361
    Abstract: There is provided a small-size magnetic sensor for detecting the intensity of a magnetic field in three axial directions, in which a plurality of giant magnetoresistive elements are formed on a single semiconductor substrate. A thick film is formed on the semiconductor substrate; giant magnetoresistive elements forming an X-axis sensor and a Y-axis sensor are formed on a planar surface thereof; and giant magnetoresistive elements forming a Z-axis sensor are formed using slopes of channels formed in the thick film. Regarding the channel formation, it is possible to use the reactive ion etching and high-density plasma CVD methods. In addition, an insulating film is formed between the thick film and passivation film and is used as an etching stopper. Each of the slopes of the channels can be constituted of a first slope and a second slope, so that a magneto-sensitive element is formed on the second slope having a larger inclination angle.
    Type: Grant
    Filed: March 15, 2006
    Date of Patent: May 15, 2012
    Assignee: Yamaha Corporation
    Inventors: Hiroshi Naito, Hideki Sato, Yukio Wakui, Masayoshi Omura
  • Publication number: 20120074511
    Abstract: A magnetic memory according to an embodiment includes: at least one memory cell comprising a magnetoresistive element as a memory element, and first and second electrodes that energize the magnetoresistive element. The magnetoresistive element includes: a first magnetic layer having a variable magnetization direction perpendicular to a film plane; a tunnel barrier layer on the first magnetic layer; and a second magnetic layer on the tunnel barrier layer, and having a fixed magnetization direction perpendicular to the film plane. The first magnetic layer including: a first region; and a second region outside the first region so as to surround the first region, and having a smaller perpendicular magnetic anisotropy energy than that of the first region. The second magnetic layer including: a third region; and a fourth region outside the third region, and having a smaller perpendicular magnetic anisotropy energy than that of the third region.
    Type: Application
    Filed: September 13, 2011
    Publication date: March 29, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shigeki TAKAHASHI, Yuichi OHSAWA, Junichi ITO, Chikayoshi KAMATA, Saori KASHIWADA, Minoru AMANO, Hiroaki YODA
  • Publication number: 20120061780
    Abstract: Disclosed herein is a storage element, including: a storage layer which has magnetization vertical to a film surface and in which a direction of the magnetization is changed in correspondence to information; a magnetization fixing layer which has magnetization vertical to a film surface becoming a reference of the information stored in the storage layer, which is composed of plural magnetic layers, and which has a multilayered ferri-pin structure into which the plural magnetic layers are laminated one upon another through a non-magnetic layer(s); and an insulating layer made of a non-magnetic material and provided between the storage layer and the magnetization fixing layer.
    Type: Application
    Filed: September 2, 2011
    Publication date: March 15, 2012
    Applicant: SONY CORPORATION
    Inventors: Hiroyuki Uchida, Masanori Hosomi, Hiroyuki Ohmori, Kazuhiro Bessho, Yutaka Higo, Kazutaka Yamane
  • Publication number: 20120061782
    Abstract: A spin wave device comprises a metal layer, a pinned layer, a nonmagnetic layer, a free layer, an antiferromagnetic layer, a first electrode, a first insulator layer, and a second electrode. The pinned layer has a magnetization whose direction is fixed. The free layer has a magnetization whose direction is variable.
    Type: Application
    Filed: September 12, 2011
    Publication date: March 15, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsuyoshi Kondo, Hirofumi Morise, Shiho Nakamura
  • Publication number: 20120049302
    Abstract: A magneto-resistance effect element includes: a first magnetization layer of which a magnetization is substantially fixed in one direction; a second magnetization layer of which a magnetization is rotated in accordance with an external magnetic field; an intermediate layer which contains insulating portions and magnetic metallic portions and which is provided between the first magnetic layer and the second magnetic layer; and a pair of electrodes to flow current in a direction perpendicular to a film surface of a multilayered film made of the first magnetic layer, the intermediate layer and the second magnetic layer; wherein the magnetic metallic portions of the intermediate layer contain non-ferromagnetic metal.
    Type: Application
    Filed: November 8, 2011
    Publication date: March 1, 2012
    Applicants: TDK CORPORATION, KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiromi FUKE, Susumu HASHIMOTO, Masayuki TAKAGISHI, Hitoshi IWASAKI
  • Patent number: 8124952
    Abstract: Programmable metallization memory cells having a first metal contact and a second metal contact with an ion conductor solid electrolyte material between the metal contacts. The first metal contact has a filament placement structure thereon extending into the ion conductor material. In some embodiments, the second metal contact also has a filament placement structure thereon extending into the ion conductor material toward the first filament placement structure. The filament placement structure may have a height of at least about 2 nm.
    Type: Grant
    Filed: January 27, 2011
    Date of Patent: February 28, 2012
    Assignee: Seagate Technology LLC
    Inventors: Insik Jin, Christina Hutchinson, Richard Larson, Lance Stover, Jaewoo Nam, Andrew Habermas
  • Publication number: 20120033478
    Abstract: A non-volatile memory device and a method for forming the same are disclosed, which relate to a ferroelectric memory device having non-volatile characteristics. The non-volatile memory device includes a control gate configured to receive a read voltage, an insulation film formed over the control gate, a metal layer formed over the insulation film, configured to include a channel region, and a drain region and source region at both ends of the channel region, a ferroelectric layer formed over the channel region of the metal layer, and a program and read gate formed over the ferroelectric layer. A write operation of data corresponding to a resistance state of the channel region is performed by changing polarity of the ferroelectric layer in response to a voltage applied to the program and read gate, the drain and source regions, and the control gate.
    Type: Application
    Filed: August 5, 2011
    Publication date: February 9, 2012
    Applicant: Hynix Semiconductor Inc.
    Inventor: Hee Bok KANG
  • Publication number: 20110297909
    Abstract: A magnetic memory element includes: a first magnetization free layer formed of a ferromagnetic material having perpendicular magnetic anisotropy; a second magnetization free layer provided near the first magnetization free layer and formed of a ferromagnetic material having in-plane magnetic anisotropy; a reference layer formed of a ferromagnetic material having in-plane magnetic anisotropy; and a non-magnetic layer provided between the second magnetization free layer and the reference layer. The first magnetization free layer includes: a first magnetization fixed region of which magnetization is fixed, a second magnetization fixed region of which magnetization is fixed, and a magnetization free region which is connected to the first magnetization fixed region and the second magnetization fixed region, and of which magnetization can be switched. The second magnetization free layer is included in the first magnetization free layer in a plane parallel to a substrate.
    Type: Application
    Filed: January 28, 2010
    Publication date: December 8, 2011
    Inventors: Shunsuke Fukami, Tetsuhiro Suzuki, Kiyokazu Nagahara, Nobuyuki Ishiwata, Norikazu Ohshima
  • Publication number: 20110260270
    Abstract: The performance of an MR device has been improved by inserting one or more Magneto-Resistance Enhancing Layers (MRELs) into approximately the center of one or more of the active layers (such as API, SIL, FGL, and Free layers). An MREL is a layer of a low band gap, high electron mobility semiconductor such as ZnO or a semimetal such as Bi.
    Type: Application
    Filed: April 26, 2010
    Publication date: October 27, 2011
    Inventors: Kunliang Zhang, Min Li, Yuchen Zhou
  • Publication number: 20110233524
    Abstract: A carrier-mediated magnetic phase change spin transistor is disclosed. In general, the spin transistor includes a Dilute Magnetic Semiconductor (DMS) channel and a gate stack formed on the DMS channel. The gate stack includes a multiferroic gate dielectric on the DMS channel, and a gate contact on a surface of the multiferroic gate dielectric opposite the DMS channel. The multiferroic gate dielectric is formed of a multiferroic material that exhibits a cross-coupling between magnetic and electric orders (i.e., magnetoelectric coupling), which in one embodiment is BiFeO3 (BFO). As a result, the multiferroic material layer enables an electrically modulated magnetic exchange bias that enhances paramagnetic to ferromagnetic switching of the DMS channel. The DMS channel is formed of a DMS material, which in one embodiment is Manganese Germanium (MnGe). In one embodiment, the DMS channel is a nanoscale DMS channel.
    Type: Application
    Filed: March 25, 2011
    Publication date: September 29, 2011
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Kang-Lung Wang, Ajey Poovannummoottil Jacob, Faxian Xiu
  • Patent number: 8004874
    Abstract: Embodiments of the invention provide a multi-terminal resistance device with first and second electrodes, a shared third electrode, and a resistance layer providing first and second current paths between the shared third electrode and the first and second electrodes, respectively. A current state of the device may be programmed by applying one or more electrical signals along the first and/or second current paths to change a resistance of the device. In some embodiments, applying an electrical signal may switch a junction resistance of the first and/or second electrodes and the resistance layer between two or more resistance values. The device may include a shared fourth electrode to provide extra programming capability. In some embodiments, the device may be used to store a data state, to determine a count of multiple electrical signals, or to perform a logic operation between two electrical signals.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: August 23, 2011
    Assignee: Seagate Technology LLC
    Inventors: Haiwen Xi, Kaizhong Gao, Song Xue
  • Patent number: 8003497
    Abstract: A method for is disclosed for fabricating diluted magnetic semiconductor (DMS) nanowires by providing a catalyst-coated substrate and subjecting at least a portion of the substrate to a semiconductor, and dopant via chloride-based vapor transport to synthesize the nanowires. Using this novel chloride-based chemical vapor transport process, single crystalline diluted magnetic semiconductor nanowires Ga1-xMnxN (x=0.07) were synthesized. The nanowires, which have diameters of ˜10 nm to 100 nm and lengths of up to tens of micrometers, show ferromagnetism with Curie temperature above room temperature, and magnetoresistance up to 250 Kelvin.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: August 23, 2011
    Assignee: The Regents of the University of California
    Inventors: Peidong Yang, Heonjin Choi, Sangkwon Lee, Rongrui He, Yanfeng Zhang, Tevye Kuykendal, Peter Pauzauskie
  • Patent number: 7999360
    Abstract: An MRAM structure is disclosed in which the bottom electrode has an amorphous TaN capping layer to consistently provide smooth and dense growth for AFM, pinned, tunnel barrier, and free layers in an overlying MTJ. Unlike a conventional Ta capping layer, TaN is oxidation resistant and has high resistivity to avoid shunting of a sense current caused by redeposition of the capping layer on the sidewalls of the tunnel barrier layer. Alternatively, the ?-TaN layer is the seed layer in the MTJ. Furthermore, the seed layer may be a composite layer of NiCr, NiFe, or NiFeCr layer on the oc-TaN layer. An ?-TaN capping layer or seed layer can also be used in a TMR read head. An MTJ formed on an ?-TaN capping layer has a high MR ratio, high Vb, and a RA similar to results obtained from MTJs based on an optimized Ta capping layer.
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: August 16, 2011
    Assignees: Headway Technologies, Inc., MagIC Technologies, Inc.
    Inventors: Liubo Hong, Cheng Horng, Mao-Min Chen, Ru-Yin Tong
  • Publication number: 20110186947
    Abstract: A magnetic material is disclosed including a two-dimensional array of carbon atoms and a two-dimensional array of nanoholes patterned in the two-dimensional array of carbon atoms. The magnetic material has long-range magnetic ordering at a temperature below a critical temperature Tc.
    Type: Application
    Filed: March 12, 2009
    Publication date: August 4, 2011
    Inventor: Feng Liu
  • Patent number: 7960186
    Abstract: The disclosure provides a method of forming a ferromagnetic material, including: forming a magnetic element layer on a semiconductor layer formed on an inhibition layer; and forming a ferromagnetic layer of a Heusler alloy layer on the inhibition layer by heat treatment to induce the semiconductor layer and the magnetic element layer to react with each other, and a transistor, and a method of manufacturing the same. The inhibition layer for inhibiting a reaction of the semiconductor layer and the magnetic element layer restricts a semiconductor to be supplied for a reaction of the semiconductor and the magnetic element. Therefore, it is possible to form a ferromagnetic material having a high composition ratio of a magnetic element.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: June 14, 2011
    Assignee: Tokyo Institute of Technology
    Inventors: Satoshi Sugahara, Yota Takamura
  • Publication number: 20110133298
    Abstract: A system and method for forming a magnetic tunnel junction (MTJ) storage element utilizes a composite free layer structure. The MTJ element includes a stack comprising a pinned layer, a barrier layer, and a composite free layer. The composite free layer includes a first free layer, a superparamagnetic layer and a nonmagnetic spacer layer interspersed between the first free layer and the superparamagnetic layer. A thickness of the spacer layer controls a manner of magnetic coupling between the first free layer and the superparamagnetic layer.
    Type: Application
    Filed: December 8, 2009
    Publication date: June 9, 2011
    Applicant: QUALCOMM INCORPORATED
    Inventors: Wei-Chuan Chen, Seung H. Kang
  • Publication number: 20110127998
    Abstract: An integrated circuit includes a leadframe, and a die having a top surface, a bottom surface, and a plurality of perimeter sides and including at least one magnetic field sensor element disposed proximate to the top surface, wherein the bottom surface is bonded to the leadframe. A molded magnetic material encapsulates the die and at least a portion of the leadframe, and provides a magnetic field substantially perpendicular to the top surface of the die. A non-magnetic material is disposed between the die and the molded magnetic material at least along perimeter sides of the die intersecting a lateral magnetic field component which is parallel to the top surface of the die.
    Type: Application
    Filed: November 30, 2009
    Publication date: June 2, 2011
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Klaus Elian, Martin Petz, Uwe Schindler, Horst Theuss, Adolf Koller
  • Patent number: 7936044
    Abstract: A memory device may include a switching device and a storage node coupled with the switching device. The storage node may include a first electrode, a second electrode, a data storage layer and at least one contact layer. The data storage layer may be disposed between the first electrode and the second electrode and may include a transition metal oxide or aluminum oxide. The at least one contact layer may be disposed at least one of above or below the data storage layer and may include a conductive metal oxide.
    Type: Grant
    Filed: April 14, 2006
    Date of Patent: May 3, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong Chul Kim, In-kyeong Yoo, Myoung-jae Lee, Sun-ae Seo, In-gyu Baek, Seung-eon Ahn, Byoung-ho Park, Young-kwan Cha, Sang-jin Park
  • Patent number: 7928524
    Abstract: A magnetoresistive element is disclosed, wherein the magnetoresistive element is composed of a synthetic anti-ferromagnetic (SAF) structure that may include a first pinned layer, an intermediate layer, and a second pinned layer; and a Cr layer between the first pinned layer and the intermediate layer and/or the second pinned layer and the intermediate layer.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: April 19, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kee-won Kim
  • Publication number: 20110084347
    Abstract: The present invention relates to a magnetic tunnel junction device and a manufacturing method thereof. The magnetic tunnel junction device includes i) a first magnetic layer having an switchable magnetization direction, ii) a nonmagnetic layer provided on the first magnetic layer, iii) a second magnetic layer provided on the nonmagnetic layer and having a fixed magnetization direction, iv) an oxidation-preventing layer provided on the second magnetic layer, v) a third magnetic layer provided on the oxidation-preventing layer and fixing the magnetization direction of the second magnetic layer through magnetic coupling with the second magnetic layer, and vi) an antiferromagnetic layer provided on the third magnetic layer and fixing a magnetization direction of the third magnetic layer.
    Type: Application
    Filed: February 17, 2010
    Publication date: April 14, 2011
    Applicant: Korea Institute of Science and Technology
    Inventors: Il-Jae Shin, Byoung-Chul Min, Kyung-Ho Shin
  • Patent number: 7897955
    Abstract: Programmable metallization memory cells having a first metal contact and a second metal contact with an ion conductor solid electrolyte material between the metal contacts. The first metal contact has a filament placement structure thereon extending into the ion conductor material. In some embodiments, the second metal contact also has a filament placement structure thereon extending into the ion conductor material toward the first filament placement structure. The filament placement structure may have a height of at least about 2 nm.
    Type: Grant
    Filed: November 3, 2008
    Date of Patent: March 1, 2011
    Assignee: Seagate Technology LLC
    Inventors: Insik Jin, Christina Hutchinson, Richard Larson, Lance Stover, Jaewoo Nam, Andrew Habermas
  • Patent number: 7893511
    Abstract: An integrated circuit includes a plurality of magnetic tunneling junction stacks, each magnetic tunneling junction stack including a reference layer, a barrier layer and a free layer, wherein the plurality of magnetic tunneling junction stacks share a continuous common reference layer.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: February 22, 2011
    Assignee: Qimonda AG
    Inventors: Manfred Ruehrig, Ulrich Klostermann, Michael Vieth
  • Patent number: 7889533
    Abstract: A semiconductor device using a magnetic domain wall movement and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a magnetic layer that is formed on a substrate and has a plurality of magnetic domains, and a unit that supplies energy to move a magnetic domain wall in the magnetic layer. The magnetic layer is formed parallel to the substrate, and includes a plurality of prominences and a plurality of depressions alternately formed along a lengthwise direction thereof. The magnetic layer has a stepped form that secures a reliable movement of the magnetic domain wall in units of one bit.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: February 15, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-jun Hwang, Sung-chul Lee
  • Publication number: 20100244164
    Abstract: Two opposing substrate layers each having one or more recesses filled with magnetic material guide the flow of flux through a coil in a MEMS device layer to provide for closed-loop operation. Flux flows from one pole piece through the coil to a second pole piece. A method of making using lithographic etching techniques is also provided.
    Type: Application
    Filed: March 26, 2009
    Publication date: September 30, 2010
    Applicant: Honeywell International Inc.
    Inventor: Ryan Roehnelt
  • Publication number: 20100232220
    Abstract: Electronic devices comprise a first substrate and a second substrate. The first substrate comprises circuitry including a plurality of conductive traces at least substantially parallel to each other through at least a portion of the first substrate. A plurality of bond pads are positioned on a surface of the first substrate and comprise a width extending over at least two of the plurality of conductive traces. A plurality of vias extend from adjacent at least some of the conductive traces to the plurality of bond pads. The second substrate is bonded to the first substrate and comprises circuitry coupled to the plurality of bond pads on the first substrate with a plurality of conductive bumps. Memory devices and related methods of forming electronic devices and memory devices are also disclosed, as are electronic systems.
    Type: Application
    Filed: March 10, 2009
    Publication date: September 16, 2010
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Roy E. Meade, Gurtej S. Sandhu
  • Publication number: 20100213519
    Abstract: An object of the present invention is to provide a silicon spin transport device manufacturing method and silicon spin transport device whereby improved voltage output characteristics can be obtained. The silicon spin transport device manufacturing method comprises: a first step of patterning a silicon film by wet etching and forming a silicon channel layer; and a second step of forming a magnetization free layer and a magnetization fixed layer, which are apart from each other, on the silicon channel layer.
    Type: Application
    Filed: January 20, 2010
    Publication date: August 26, 2010
    Applicant: TDK CORPORATION
    Inventors: Tomoyuki SASAKI, Tohru OIKAWA, Katsumichi TAGAMI
  • Publication number: 20100187583
    Abstract: A reconfigurable electric circuit includes first and second crystalline material layers positioned adjacent to each other and forming a first interface, and a first ferroelectric layer positioned adjacent to the first crystalline material layer and having ferroelectric domains applying an electric field to regions of the first interface to induce a quasi two-dimensional electron gas in the regions, wherein at least one of the regions forms a gate and at least one of the regions forms a channel.
    Type: Application
    Filed: January 26, 2009
    Publication date: July 29, 2010
    Applicant: Seagate Technology LLC
    Inventors: Stephen John Wrazien, Florin Zavaliche, Joachim Walter Ahner, Tong Zhao, Martin Gerard Forrester, Shan Hu
  • Patent number: 7759713
    Abstract: A tunneling element includes a thin film layer of ferroelectric material and a pair of dissimilar electrically-conductive layers disposed on opposite sides of the ferroelectric layer. Because of the dissimilarity in composition or construction between the electrically-conductive layers, the electron transport behavior of the electrically-conductive layers is polarization dependent when the tunneling element is below the Curie temperature of the layer of ferroelectric material. The element can be used as a basis of compact 1R type non-volatile random access memory (RAM). The advantages include extremely simple architecture, ultimate scalability and fast access times generic for all ferroelectric memories.
    Type: Grant
    Filed: March 6, 2006
    Date of Patent: July 20, 2010
    Assignee: UT-Battelle, LLC
    Inventors: Sergei V. Kalinin, Hans M. Christen, Arthur P. Baddorf, Vincent Meunier, Ho Nyung Lee
  • Publication number: 20100148167
    Abstract: A magnetic tunnel junction (300) structure includes a layer (308) of iron having a thickness in the range of 1.0 to 5.0 ? disposed between a tunnel barrier (306) and a free magnetic element (310) resulting in high magnetoresistance (MR), low damping and an improved ratio Vc/Vbd of critical switching voltage to tunnel barrier breakdown voltage for improved spin torque yield and reliability while requiring only a low temperature anneal. This improved structure (300) also has a very low resistance-area product MgON diffusion barrier (312) between the free magnetic element (310) and an electrode (314) to prevent diffusion of the electrode into the free layer, which assists in keeping the damping, and therefore also the switching voltage, low. With the low annealing temperature, the breakdown voltage is high, resulting in a favorable ratio of Vc/Vbd and in a high proportion of devices switching before breakdown, therefore improving the yield and reliability of the devices.
    Type: Application
    Filed: December 12, 2008
    Publication date: June 17, 2010
    Applicant: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Renu Whig, Frederick B. Mancoff, Nicholas D. Rizzo, Phillip G. Mather
  • Publication number: 20100140726
    Abstract: A method and system for providing a magnetic element are described. The magnetic element includes pinned and free layers, a nonmagnetic spacer layer between the free and pinned layers, and a stability structure. The free layer is between the spacer layer and the stability structure. The free layer has a free layer magnetization, at least one free layer easy axis, and at least one hard axis. The stability structure includes magnetic layers and is configured to decrease a first magnetic energy corresponding to the free layer magnetization being aligned with the at least one easy axis without decreasing a second magnetic energy corresponding to the free layer magnetization being aligned with the at least one hard axis. The magnetic element is configured to allow the free layer magnetization to be switched to between states when a write current is passed through the magnetic element.
    Type: Application
    Filed: December 4, 2008
    Publication date: June 10, 2010
    Applicant: GRANDIS, INC.
    Inventors: Dmytro Apalkov, Yunfei Ding
  • Publication number: 20100135068
    Abstract: A resistance-change memory device is provided and includes a stack constituting a tunnel magnetoresistance effect element that has a magnetic layer in which a direction of magnetization is switchable and that is formed on a conductive layer, and the stack is included in a resistance-change memory cell performing data writing utilizing a spin transfer effect caused by current injection. The stack is formed such that a line connecting centers of respective layers of the stack is tilted with respect to a direction perpendicular to a surface of the conductive layer having the stack formed thereon.
    Type: Application
    Filed: December 2, 2009
    Publication date: June 3, 2010
    Applicant: SONY CORPORATION
    Inventors: Minoru Ikarashi, Yutaka Higo, Masanori Hosomi, Hiroshi Kano, Shinichiro Kusunoki, Hiroyuki Ohmori, Yuki Oishi, Tetsuya Yamamoto, Kazutaka Yamane
  • Publication number: 20100123133
    Abstract: A device comprising a channel for charge carriers comprising non-ferromagnetic semiconducting in which charge carriers exhibit spin-orbit coupling, a region of semiconducting material of opposite conductivity type to the channel and configured so as to form a junction with the channel for injecting spin-polarised charge carriers into an end of the channel and at least one lead connected to the channel for measuring a transverse voltage across the channel.
    Type: Application
    Filed: August 21, 2009
    Publication date: May 20, 2010
    Inventors: Joerg Wunderlich, Tomas JUNGWIRTH, Andrew IRVINE, Jairo SINOVA
  • Patent number: 7719071
    Abstract: A bipolar spin transistor is provided. In one embodiment of the present invention, the bipolar spin transistor includes a first semiconductor region having a first conductivity type, a second semiconductor region having a second conductivity type that is different from the first conductivity type and also having a spin polarization, and a third semiconductor region having a conductivity type that is the same conductivity type of the first semiconductor region. The first semiconductor region and the second semiconductor region are adjacent to each other so as to form a first charge depletion layer therebetween, the first charge depletion layer having a first side facing the first semiconductor region and an opposing second side facing the second semiconductor region.
    Type: Grant
    Filed: May 26, 2004
    Date of Patent: May 18, 2010
    Assignee: University of iowa Research Foundation
    Inventors: Michael Edward Flatté, Zhi Gang Yu, Ezekiel Johnston-Halperin, David Awschalom
  • Patent number: 7714399
    Abstract: A magnetic memory element includes a laminated construction of an electrode, a first pinned layer, a first intermediate layer, a first memory layer, a second intermediate layer, a second memory layer, a third intermediate layer, a second pinned layer and electrode. The magnetization direction of the first memory layer takes a first and a second directions and that of the second memory layer takes a third and a fourth directions corresponding to a value and polarity of a current between the electrodes. In response to the current, the second intermediate layer has an electric resistance higher than the first intermediate layer and than the third intermediate layer.
    Type: Grant
    Filed: September 21, 2007
    Date of Patent: May 11, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirofumi Morise, Shiho Nakamura, Satoshi Yanagi
  • Patent number: 7705340
    Abstract: Disclosed herein is a magnetoresistive structure having a non-planar form. Embodiments of the present MR structure includes those having at least one inflection between a first portion of the MR structure that is somewhat vertical relative to a substrate and a second portion of the MR structure that is somewhat horizontal relative to the substrate. Such a structure can be used for memory device, for example an MRAM memory device, wherein the memory density is increased compared to devices having prior planar MR structures without reducing the surface area of the MR structures.
    Type: Grant
    Filed: October 5, 2005
    Date of Patent: April 27, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chun-Chieh Lin
  • Patent number: 7687284
    Abstract: A small-size magnetic sensor comprises three axial sensors each configured using plural giant magnetoresistive elements, wherein an X-axis sensor and a Y-axis sensor are arranged on the planar surface of an embedded layer of a substrate, and giant magnetoresistive elements forming a Z-axis sensor are formed on slopes of projections, which are formed by etching the embedded layer. It is possible to form an elongated projection on a substrate by way of the high-density plasma CVD method or by way of plasma etching and microwave etching, so that giant magnetoresistive elements are formed on the slopes of the elongated projection.
    Type: Grant
    Filed: January 10, 2006
    Date of Patent: March 30, 2010
    Assignee: Yamaha Corporation
    Inventors: Hiroshi Naito, Hideki Sato, Hiroaki Fukami, Syuusei Takami
  • Patent number: 7683444
    Abstract: Materials and structures whose index of refraction can be tuned over a broad range of negative and positive values by applying above band-gap photons to a structure with a strip line element, a split ring resonator element, and a substrate, at least one of which is a photoconductive semiconductor material. Methods for switching between positive and negative values of n include applying above band-gap photons to different numbers of elements. In another embodiment, a structure includes a photoconductive semiconductor wafer, the wafer operable to receive above band-gap photons at an excitation frequency in an excitation pattern on a surface of the wafer, the excitation patterns generating an effective negative index of refraction. Methods for switching between positive and negative values of n include projecting different numbers of elements on the wafer. The resonant frequency of the structure is tuned by changing the size of the split ring resonator excitation patterns.
    Type: Grant
    Filed: November 14, 2006
    Date of Patent: March 23, 2010
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: Ronald J Tonucci
  • Patent number: 7679155
    Abstract: The present invention provides a low resistance high magnetoresistance (MR) device comprised of a junction of two magnetic elements separated by a magnesium oxide (MgO) layer doped with such metals as Al and Li. Such device can be used as a sensor of magnetic field in magnetic recording or as a storage element in magnetic random access memory (MRAM). The invention provides a high-MR device possessing a diode function, comprised of a double junction of two outer magnetic elements separated by two MgO insulating layer and a center MgO layer doped with such metals as Al and Li. Such device provides design advantages when used as a storage element in MRAM. The invention with MR wherein a gate electrode is placed in electrical or physical contact to the center layer of the double tunnel junction.
    Type: Grant
    Filed: February 8, 2007
    Date of Patent: March 16, 2010
    Assignee: VNK Innovation AB
    Inventor: Vladislav Korenivski
  • Publication number: 20100044680
    Abstract: An MRAM structure is disclosed in which the bottom electrode has an amorphous TaN capping layer to consistently provide smooth and dense growth for AFM, pinned, tunnel barrier, and free layers in an overlying MTJ. Unlike a conventional Ta capping layer, TaN is oxidation resistant and has high resistivity to avoid shunting of a sense current caused by redeposition of the capping layer on the sidewalls of the tunnel barrier layer. Alternatively, the ?-TaN layer is the seed layer in the MTJ. Furthermore, the seed layer may be a composite layer comprised of a NiCr, NiFe, or NiFeCr layer on the ?-TaN layer. An ?-TaN capping layer or seed layer can also be used in a TMR read head. An MTJ formed on an ?-TaN capping layer has a high MR ratio, high Vb, and a RA similar to results obtained from MTJs based on an optimized Ta capping layer.
    Type: Application
    Filed: October 23, 2009
    Publication date: February 25, 2010
    Inventors: LIUBO HONG, Cheng Horng, Mao-Min Chen, Ru-Yin Tong
  • Publication number: 20100041168
    Abstract: A magnetic memory device includes a free layer and a guide layer on a substrate. An insulating layer is interposed between the free layer and the guide layer. At least one conductive bridge passes through the insulating layer and electrically connects the free layer and the guide layer. A diffusion barrier may be interposed between the guide layer and the insulating layer. The device may further include a reference layer having a fixed magnetization direction on a side of the free layer opposite the insulating layer and a tunnel barrier between the reference layer and the free layer. Related fabrication methods are also described.
    Type: Application
    Filed: August 12, 2009
    Publication date: February 18, 2010
    Inventors: KyungTae Nam, Jangeun Lee, Sechung Oh, Woojin Kim, Dae Kyom Kim, Junho Jeong
  • Publication number: 20100032778
    Abstract: Magnetic memory having separate read and write paths is disclosed. The magnetic memory unit includes a ferromagnetic strip having a first end portion with a first magnetization orientation, an opposing second end portion with a second magnetization orientation, and a middle portion between the first end portion and the second end portion, the middle portion having a free magnetization orientation. The first magnetization orientation opposes the second magnetization orientation. A tunneling barrier separates a magnetic reference layer from the middle portion forming a magnetic tunnel junction. A bit line is electrically coupled to the second end portion. A source line is electrically coupled to the first end portion and a read line is electrically coupled to the magnetic tunnel junction.
    Type: Application
    Filed: December 2, 2008
    Publication date: February 11, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Yong Lu, Hongyue Liu, Zheng Gao, Insik Jin, Dimitar V. Dimitrov
  • Publication number: 20100034011
    Abstract: Embodiments of the invention provide a multi-terminal resistance device with first and second electrodes, a shared third electrode, and a resistance layer providing first and second current paths between the shared third electrode and the first and second electrodes, respectively. A current state of the device may be programmed by applying one or more electrical signals along the first and/or second current paths to change a resistance of the device. In some embodiments, applying an electrical signal may switch a junction resistance of the first and/or second electrodes and the resistance layer between two or more resistance values. The device may include a shared fourth electrode to provide extra programming capability. In some embodiments, the device may be used to store a data state, to determine a count of multiple electrical signals, or to perform a logic operation between two electrical signals.
    Type: Application
    Filed: March 27, 2009
    Publication date: February 11, 2010
    Applicant: Seagate Technology, LLC
    Inventors: Haiwen Xi, Kaizhong Gao, Song Xue
  • Publication number: 20100013035
    Abstract: An integrated circuit includes a plurality of magnetic tunneling junction stacks, each magnetic tunneling junction stack including a reference layer, a barrier layer and a free layer, wherein the plurality of magnetic tunneling junction stacks share a continuous common reference layer.
    Type: Application
    Filed: July 17, 2008
    Publication date: January 21, 2010
    Inventors: Manfred Ruehrig, Ulrich Klostermann, Michael Vieth
  • Publication number: 20090315129
    Abstract: An integrated circuit includes a first plate-shaped part and at least a plate-shaped second part separate from the first part and attached to the first part by deformable mechanical connection defining a non-zero angle with the first part. A method of producing the integrated circuit includes depositing deformable connecting means in contact with a first portion of the structure and a second portion of the structure, etching the structure to separate the first portion and the second portion, relatively moving the first and second portions to deform the connecting means and fastening together the first portion and the second portion.
    Type: Application
    Filed: July 11, 2007
    Publication date: December 24, 2009
    Inventor: Jean Baptiste Albertini
  • Publication number: 20090316475
    Abstract: Provided are an information storage device and a method of operating the same. The information storage device includes: a magnetic layer having a plurality of magnetic domain regions and a magnetic domain wall interposed between the magnetic domain regions; a first unit disposed on a first region which is one of the plurality of magnetic domain regions for recording information to the first region; a second unit connected to the first unit for inducing a magnetic field so as to record information to the first region.
    Type: Application
    Filed: September 22, 2008
    Publication date: December 24, 2009
    Inventors: Sung-chul Lee, Sun-ae Seo, Young-Jin Cho, Ung-hwan Pi, Ji-young Bae
  • Publication number: 20090309145
    Abstract: A magnetic thin film includes a magnetic tunnel junction defined by a surrounding region including a fluorinated, non-magnetic, electrically insulating material.
    Type: Application
    Filed: August 20, 2009
    Publication date: December 17, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David William Abraham, Eugene John O'Sullivan