Processes Or Apparatus Peculiar To Manufacture Or Treatment Of These Devices Or Of Parts Thereof (epo) Patents (Class 257/E43.006)
  • Patent number: 10418334
    Abstract: A semiconductor die is disclosed including corner recesses to prevent cracking of the semiconductor die during fabrication. Prior to dicing the semiconductor die from the wafer, recesses may be formed in the wafer at corners between any pair of semiconductor die. The recesses may be formed by a laser or photolithographic processes in the kerf area between semiconductor die. Once formed, the corner recesses prevent cracking and damage to semiconductor die which could otherwise occur at the corners of adjacent semiconductor die as the adjacent semiconductor die move relative to each other during the backgrind process.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: September 17, 2019
    Assignee: SanDisk Semiconductor (Shanghai) Co. Ltd.
    Inventors: Hang Zhang, Weili Wang, Junrong Yan, Kim Lee Bock, Chee Keong Chin, Chong Un Tan, Xin Tian
  • Patent number: 10364140
    Abstract: In some embodiments a method of manufacturing a sensor system can comprise forming a first structure having a substrate layer and a first sensor that is positioned on a first side of the substrate layer, bonding a cap structure over the first sensor on the first side of the substrate layer, and depositing a first dielectric layer over the cap structure. After bonding the cap structure and depositing the first dielectric layer, a second sensor is fabricated on the first dielectric layer. The second sensor includes material that would be adversely affected at a temperature that is used to bond the cap structure to the first side of the substrate layer.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: July 30, 2019
    Assignee: NXP USA, Inc.
    Inventors: Lianjun Liu, David J. Monk
  • Patent number: 10151806
    Abstract: A method and an apparatus are for the permanent magnetization of at least one ferromagnetic layer in a magnetic field sensor device deposited on a chip substrate. The method includes production of at least one resistance element on a chip substrate, deposition of at least one soft magnetic structuring element on the chip substrate; heating of the resistance element to above the blocking temperature and coupling of a preconditioning magnetic field; cooling of the resistance element to below the blocking temperature; and removal of the preconditioning magnetic field. The soft magnetic structuring element is arranged such that the coupled preconditioning magnetic field penetrates the structuring element substantially perpendicular to the chip surface and, at the location of the resistance element, generates magnetic field components parallel to the chip surface which penetrate the ferromagnetic layer of the resistance element at least in some areas.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: December 11, 2018
    Assignee: SENSITEC GMBH
    Inventors: Jochen Schmitt, Johannes Paul, Ronald Lehndorff, Jürgen Wahrhusen, Claudia Glenske
  • Patent number: 10082431
    Abstract: System and methods for magnetic Tunnel Junction pressure sensors are provided. In at least one implementation, a pressure sensor device comprises a magnetic tunnel junction comprising a free layer structure, a tunnel barrier, and a reference layer structure, wherein one or more surfaces of the free layer structure is exposed to respond to a pressure medium; and a voltage source coupled to the magnetic tunnel junction, the voltage source providing electrical power to the free layer structure and the reference layer structure. The device further comprises a current detector coupled between the magnetic tunnel junction and the voltage source; and a pressure calculating device, configured to calculate a pressure based on a current detected by the current detector.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: September 25, 2018
    Assignee: Honeywell International Inc.
    Inventor: Romney R. Katti
  • Patent number: 9577185
    Abstract: An integrated fluxgate device, which includes a magnetic core, an excitation coil, and a sense coil. The magnetic core has a longitudinal edge and a terminal edge. The excitation coil coils around the longitudinal edge of the magnetic core, and the excitation coil has a first number of excitation coil members within a proximity of the terminal edge. The sense coil coils around the longitudinal edge of the magnetic core, and the sense coil has a second number of sense coil members within the proximity of the terminal edge. For reducing fluxgate noise, the second number of sense coil members may be less than the first number of excitation coil members within the proximity of the terminal edge.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: February 21, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Dok Won Lee, Sudtida Lavangkul, Erika Lynn Mazotti, William David French
  • Patent number: 9040953
    Abstract: According to one embodiment, a storage device includes first electrodes, second electrodes, a resistance change layer provided between the first electrodes and the second electrodes, and ion metal particles that are formed in an island form between the first electrodes and the resistance change layer and that contain a metal movable inside the resistance change layer. The first electrodes and the second electrodes are formed of a material which is more unlikely to be ionized as compared to the metal, and the first electrodes are in contact with the resistance change layer in an area around the ion metal particles.
    Type: Grant
    Filed: March 2, 2014
    Date of Patent: May 26, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yusuke Arayashiki, Hidenori Miyagawa, Tomohito Kawashima
  • Patent number: 9029964
    Abstract: A method for manufacturing a semiconductor device includes forming plural layers of a MTJ device, depositing a conductive layer over the plural layers, forming a hard mask pattern used for patterning the plural layers over the conductive layer, where the conductive layer is exposed through the hard mask pattern, performing hydrogen peroxide process to volatilize the exposed conductive layer and removing the volatilized conductive layer, and patterning the plural layers by using the hard mask pattern as an etch mask to form the MTJ device.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: May 12, 2015
    Assignee: Hynix Semiconductor Inc.
    Inventors: Ga Young Ha, Ki Seon Park
  • Patent number: 9006849
    Abstract: This invention comprises a method to make small MTJ element using hybrid etching and oxygen plasma immersion ion implantation. The method has no removal of the magnetic free layer (or memory layer) and hence prevents any possible physical damage near the free layer edges. After photolithography patterning, alternative Ta, Ru, Ta etchings are performed before it stops on an MgO intermediate layer above the free layer. Then an oxygen plasma immersion ion implantation is performed to completely oxidize the exposed portion of the free layer, leaving the hard mask covered portion unchanged which define the lateral width of the MTJ element.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: April 14, 2015
    Inventor: Yimin Guo
  • Patent number: 8981503
    Abstract: An STT MTJ cell is formed with a magnetic anisotropy of its free and reference layers that is perpendicular to their planes of formation. The reference layer of the cell is an SAF multilayered structure with a single magnetic domain to enhance the bi-stability of the magnetoresistive states of the cell. The free layer of the cell is etched back laterally from the reference layer, so that the fringing stray field of the reference layer is no more than 15% of the coercivity of the free layer and has minimal effect on the free layer.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: March 17, 2015
    Assignee: Headway Technologies, Inc.
    Inventors: Robert Beach, Guenole Jan, Yu-Jen Wang, Witold Kula, Po-Kang Wang
  • Patent number: 8962349
    Abstract: The present invention is directed to a method for fabricating a magnetic tunnel junction (MTJ) memory element. The method comprises the steps of providing a substrate having a contact dielectric layer, a bottom dielectric layer, a bottom electrode layer, an etch stop layer, an MTJ layer stack, and a top electrode layer sequentially formed thereon; etching the top electrode layer with a first mask thereon to form a top electrode; etching the MTJ layer stack with the top electrode thereon to form a patterned MTJ; encapsulating the patterned MTJ with a passivation layer; depositing a top dielectric layer on top of the passivation layer and planarizing the same layer; forming a second mask on the top dielectric layer; and etching the bottom electrode layer, the etch stop layer, the passivation layer, and the top dielectric layer with the second mask thereon to form a bottom electrode.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: February 24, 2015
    Assignee: Avalanche Technology, Inc.
    Inventors: Benjamin Chen, Kimihiro Satoh, Jing Zhang, Dong Ha Jung
  • Patent number: 8852963
    Abstract: A method for making a current-perpendicular-to-the-plane (CPP) magnetoresistive (MR) sensor that has a reference layer with low coercivity includes first depositing, within a vacuum chamber, a seed layer and an antiferromagnetic layer on a substrate without the application of heat. The substrate with deposited layers is then heated to between 200-600° C. for between 1 to 120 minutes. The substrate with deposited layers is then cooled, preferably to room temperature (i.e., below 50° C., but to at least below 100° C., in the vacuum chamber. After cooling of the antiferromagnetic layer, the ferromagnetic reference layer is deposited on the antiferromagnetic layer. Then the substrate with deposited layers is removed from the vacuum chamber and subjected to a second annealing, in the presence of a magnetic field, by heating to a temperature between 200-400° C. for between 0.5-50 hours.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: October 7, 2014
    Assignee: HGST Netherlands B.V.
    Inventors: Matthew J. Carey, Shekar B. Chandrashekariaih, Jeffrey R. Childress, Young-suk Choi, John Creighton Read
  • Patent number: 8835268
    Abstract: A method for manufacturing a semiconductor device includes forming a mask film on a partial region of a semiconductor substrate; forming a mask member above the semiconductor substrate in both the region where the mask film is formed and a region where the mask film is not formed; patterning the mask film and an upper portion of the semiconductor substrate by performing etching using the mask member as a mask. The method further includes removing part of the patterned upper portion of the semiconductor substrate by performing etching using the patterned mask film as a mask.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: September 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Gaku Sudo
  • Patent number: 8836061
    Abstract: A spin transfer torque magnetic random access memory (STTMRAM) magnetic tunnel junction (MTJ) stack includes layers to which when electric current is applied cause switching of the direction of magnetization of at least one of the layer. The STTMRAM MTJ stack includes a reference layer (RL) with a direction of magnetization that is fixed upon manufacturing of the STTMRAM MTJ stack, a junction layer (JL) formed on top of the RL, a free layer (FL) formed on top of the JL. The FL has a direction of magnetization that is switchable relative to that of the RL upon the flow of electric current through the spin transfer torque magnetic random access memory (STTMRAM) magnetic tunnel junction (MTJ) stack. The STTMRAM MTJ stack further includes a spin confinement layer (SCL) formed on top of the FL, the SCL made of ruthenium.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: September 16, 2014
    Assignee: Avalanche Technology, Inc.
    Inventors: Yuchen Zhou, Yiming Huai, Zihui Wang, Dong Ha Jung
  • Patent number: 8836056
    Abstract: Magnetic tunnel junctions (MTJ) suitable for spin transfer torque memory (STTM) devices, include perpendicular magnetic layers and one or more anisotropy enhancing layer(s) separated from a free magnetic layer by a crystallization barrier layer. In embodiments, an anisotropy enhancing layer improves perpendicular orientation of the free magnetic layer while the crystallization barrier improves tunnel magnetoresistance (TMR) ratio with better alignment of crystalline texture of the free magnetic layer with that of a tunneling layer.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: September 16, 2014
    Assignee: Intel Corporation
    Inventors: Kaan Oguz, Mark L. Doczy, Brian Doyle, Uday Shah, David L. Kencke, Roksana Golizadeh Mojarad, Robert S. Chau
  • Publication number: 20140256061
    Abstract: A method for fabricating a magnetic film structure is provided. The method comprises forming a magnetic structure on a bottom electrode layer, the magnetic structure comprising at least one pinned bottom magnetic film layer having a fixed magnetic orientation; at least one top magnetic film layer whose magnetic orientation can be manipulated by a current; and a tunneling layer between the bottom magnetic film layer and the top magnetic film layer; forming a metallic hard mask atop the magnetic structure; patterning and etching the metallic hard mask to define exposed areas of the magnetic structure; selectively etching the exposed areas of the magnetic structure by a chemical etch process based on a CO etch chemistry to form discrete magnetic bits.
    Type: Application
    Filed: August 19, 2011
    Publication date: September 11, 2014
    Applicant: MAGSIL CORPORATION
    Inventors: Krishnakumar Mani, Benjamin Chen
  • Patent number: 8826726
    Abstract: A gas sensor is described which incorporates a sensor stack comprising a first film layer of a ferromagnetic material, a spacer layer, and a second film layer of the ferromagnetic material. The first film layer is fabricated so that it exhibits a dependence of its magnetic anisotropy direction on the presence of a gas, That is, the orientation of the easy axis of magnetization will flip from out-of-plane to in-plane when the gas to be detected is present in sufficient concentration. By monitoring the change in resistance of the sensor stack when the orientation of the first layer's magnetization changes, and correlating that change with temperature one can determine both the identity and relative concentration of the detected gas.
    Type: Grant
    Filed: April 29, 2010
    Date of Patent: September 9, 2014
    Assignee: The Regents of the University of California
    Inventors: Andreas K. Schmid, Arantzazu Mascaraque, Benito Santos, Juan de la Figuera
  • Patent number: 8802451
    Abstract: Methods of fabricating MTJ arrays using two orthogonal line patterning steps are described. Embodiments are described that use a self-aligned double patterning method for one or both orthogonal line patterning steps to achieve dense arrays of MTJs with feature dimensions one half of the minimum photo lithography feature size (F). In one set of embodiments, the materials and thicknesses of the stack of layers that provide the masking function are selected so that after the initial set of mask pads have been patterned, a sequence of etching steps progressively transfers the mask pad shape through the multiple mask layer and down through all of the MTJ cell layers to the form the complete MTJ pillars. In another set of embodiments, the MTJ/BE stack is patterned into parallel lines before the top electrode layer is deposited.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: August 12, 2014
    Assignee: Avalanche Technology Inc.
    Inventors: Roger Klas Malmhall, Kimihiro Satoh, Jing Zhang, Parviz Keshtbod, Rajiv Yadav Ranjan
  • Patent number: 8796042
    Abstract: A method of fabricating a magnetic tunnel junction structure includes forming a magnetic tunnel junction layer on a substrate. A mask pattern is formed on a region of the second magnetic layer. A magnetic tunnel junction layer pattern and a sidewall dielectric layer pattern on at least one sidewall of the magnetic tunnel junction layer pattern are formed by performing at least one etch process and at least one oxidation process multiple times. The at least one etch process may include a first etch process to etch a portion of the magnetic tunnel junction layer using an inert gas and the mask pattern to form a first etch product. The at least one oxidation process may include a first oxidation process to oxidize the first etch product attached on an etched side of the magnetic tunnel junction layer.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: August 5, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hee-Ju Shin, Jun-Ho Jeong, Jang-Eun Lee, Se-Chung Oh
  • Patent number: 8796041
    Abstract: A semiconductor device includes a substrate including an M2 patterned area. A VA pillar structure is formed over the M2 patterned area. The VA pillar structure includes a substractively patterned metal layer. The VA pillar structure is a sub-lithographic contact. An MTJ stack is formed over the oxide layer and the metal layer of the VA pillar. A size of the MTJ stack and a shape anisotropy of the MTJ stack are independent of a size and a shape anisotropy of the sub-lithographic contact.
    Type: Grant
    Filed: August 28, 2009
    Date of Patent: August 5, 2014
    Assignee: International Business Machines Corporation
    Inventors: Solomon Assefa, Michael C. Gaidis, Eric A. Joseph, Eugene J. O'Sullivan
  • Patent number: 8772888
    Abstract: Use of a multilayer etching mask that includes a stud mask and a removable spacer sleeve for MTJ etching to form a bottom electrode that is wider than the rest of the MTJ pillar is described. The first embodiment of the invention described includes a top electrode and a stud mask. In the second and third embodiments the stud mask is a conductive material and also serves as the top electrode. In embodiments after the stud mask is formed a spacer sleeve is formed around it to initially increase the masking width for a phase of etching. The spacer is removed for further etching, to create step structures that are progressively transferred down into the layers forming the MTJ pillar. In one embodiment the spacer sleeve is formed by net polymer deposition during an etching phase.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: July 8, 2014
    Assignee: Avalanche Technology Inc.
    Inventors: Dong Ha Jung, Kimihiro Satoh, Jing Zhang, Yuchen Zhou, Yiming Huai
  • Patent number: 8772886
    Abstract: A spin transfer torque memory random access memory (STTMRAM) element is capable of switching states when electrical current is applied thereto for storing data and includes the following layers. An anti-ferromagnetic layer, a fixed layer formed on top of the anti-ferromagnetic layer, a barrier layer formed on top of the second magnetic layer of the fixed layer, and a free layer including a first magnetic layer formed on top of the barrier layer, a second magnetic layer formed on top of the first magnetic layer, a non-magnetic insulating layer formed on top of the second magnetic layer and a third magnetic layer formed on top of the non-magnetic insulating layer. A capping layer is formed on top of the non-magnetic insulating layer.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: July 8, 2014
    Assignee: Avalanche Technology, Inc.
    Inventors: Yiming Huai, Rajiv Yadav Ranjan, Ioan Tudosa, Roger Klas Malmhall, Yuchen Zhou
  • Patent number: 8710605
    Abstract: A magnetic memory according to an embodiment includes: at least one memory cell comprising a magnetoresistive element as a memory element, and first and second electrodes that energize the magnetoresistive element. The magnetoresistive element includes: a first magnetic layer having a variable magnetization direction perpendicular to a film plane; a tunnel barrier layer on the first magnetic layer; and a second magnetic layer on the tunnel barrier layer, and having a fixed magnetization direction perpendicular to the film plane. The first magnetic layer including: a first region; and a second region outside the first region so as to surround the first region, and having a smaller perpendicular magnetic anisotropy energy than that of the first region. The second magnetic layer including: a third region; and a fourth region outside the third region, and having a smaller perpendicular magnetic anisotropy energy than that of the third region.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: April 29, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeki Takahashi, Yuichi Ohsawa, Junichi Ito, Chikayoshi Kamata, Saori Kashiwada, Minoru Amano, Hiroaki Yoda
  • Patent number: 8685757
    Abstract: A method for fabricating a magnetic tunnel junction element includes forming a magneto resistance layer including a first magnetic layer, an insulation layer and a second magnetic layer on a substrate, forming a magnetic loss area by doping a magnetic loss impurity into a region of the magneto resistance layer to cause a magnetic loss, and etching the magnetic loss area to form a magnetic tunnel junction element.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: April 1, 2014
    Assignee: SK Hynix Inc.
    Inventors: Dong Ha Jung, Gyu An Jin, Su Ryun Min
  • Publication number: 20140084398
    Abstract: Magnetic tunnel junctions (MTJ) suitable for spin transfer torque memory (STTM) devices, include perpendicular magnetic layers and one or more anisotropy enhancing layer(s) separated from a free magnetic layer by a crystallization barrier layer. In embodiments, an anisotropy enhancing layer improves perpendicular orientation of the free magnetic layer while the crystallization barrier improves tunnel magnetoresistance (TMR) ratio with better alignment of crystalline texture of the free magnetic layer with that of a tunneling layer.
    Type: Application
    Filed: September 26, 2012
    Publication date: March 27, 2014
    Inventors: Kaan OGUZ, Mark L. DOCZY, Brian DOYLE, Uday SHAH, David L. KENCKE, Roksana GOLIZADEH MOJARAD, Robert S. CHAU
  • Patent number: 8680592
    Abstract: A method of forming a magnetic tunnel junction device is disclosed that includes forming a trench in a substrate, the trench including a first sidewall, a second sidewall, a third sidewall, a fourth sidewall, and a bottom wall. The method includes depositing a first conductive material within the trench proximate to the first sidewall and depositing a second conductive material within the trench. The method further includes depositing a magnetic tunnel junction (MTJ) structure within the trench. The MTJ structure includes a fixed magnetic layer having a magnetic field with a fixed magnetic orientation, a tunnel junction layer, and a free magnetic layer having a magnetic field with a configurable magnetic orientation. The method further includes selectively removing a portion of the MTJ structure that is adjacent to the fourth sidewall to create an opening such that the MTJ structure is substantially u-shaped.
    Type: Grant
    Filed: May 14, 2010
    Date of Patent: March 25, 2014
    Assignee: QUALCOMM Incorporated
    Inventor: Xia Li
  • Publication number: 20140070342
    Abstract: Methods of forming memory cells, magnetic memory cell structures, and arrays of magnetic memory cell structures are disclosed. Embodiments of the methods include patterning a precursor structure to form a stepped structure including at least an upper discrete feature section and a lower feature section with a broader width, length, or both than the upper discrete feature section. The method uses patterning acts directed along a first axis, e.g., an x-axis, and then along a second axis, e.g., a y-axis, that is perpendicular to or about perpendicular to the first axis. The patterning acts may therefore allow for more unifoimity between a plurality of formed, neighboring cell core structures, even at dimensions below about thirty nanometers. Magnetic memory structures and memory cell arrays are also disclosed.
    Type: Application
    Filed: September 13, 2012
    Publication date: March 13, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Gurtej S. Sandhu, Witold Kula, Wayne I. Kinney
  • Publication number: 20140048893
    Abstract: The present disclosure provides a semiconductor memory device. The device includes a pinning layer having an anti-ferromagnetic material and disposed over a first electrode; a pinned layer disposed over the pinning layer; a tunneling layer disposed over the pinned layer, a free layer disposed over the tunneling layer and a capping layer disposed over the free layer. The capping layer includes metal-oxide and metal-nitride materials.
    Type: Application
    Filed: August 16, 2012
    Publication date: February 20, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Ming Wu, Kai-Wen Cheng, Cheng-Yuan Tsai, Chia-Shiung Tsai
  • Publication number: 20140042567
    Abstract: Use of a multilayer etching mask that includes a stud mask and a removable spacer sleeve for MTJ etching to form a bottom electrode that is wider than the rest of the MTJ pillar is described. The first embodiment of the invention described includes a top electrode and a stud mask. In the second and third embodiments the stud mask is a conductive material and also serves as the top electrode. In embodiments after the stud mask is formed a spacer sleeve is formed around it to initially increase the masking width for a phase of etching. The spacer is removed for further etching, to create step structures that are progressively transferred down into the layers forming the MTJ pillar. In one embodiment the spacer sleeve is formed by net polymer deposition during an etching phase.
    Type: Application
    Filed: August 10, 2012
    Publication date: February 13, 2014
    Inventors: Dong Ha Jung, Kimihiro Satoh, Jing Zhang, Yuchen Zhou, Yiming Huai
  • Publication number: 20130334629
    Abstract: An all (111) MTJ stack is disclosed in which there are no transitions between different crystalline orientations when going from layer to layer. This is accomplished by providing strongly (111)-textured layers immediately below the MgO tunnel barrier to induce a (111) orientation therein.
    Type: Application
    Filed: June 18, 2012
    Publication date: December 19, 2013
    Applicant: HEADWAY TECHNOLOGIES, INC.
    Inventors: Witold Kula, Ru-Ying Tong, Guenole Jan, Yu-Jen Wang
  • Patent number: 8609440
    Abstract: A semiconductor device includes a substrate and a ferroelectric capacitor including a lower electrode, a ferroelectric film, and an upper electrode. The upper electrode includes a first layer formed of an oxide whose stoichiometric composition is expressed as AOx1 and whose actual composition is expressed as AOx2; a second layer formed on the first layer and formed of an oxide whose stoichiometric composition is expressed as BOy1 and whose actual composition is expressed as BOy2; and a metal layer formed on the second layer. The second layer is higher in ratio of oxidation than the first layer. The composition parameters x1, x2, y1, and y2 satisfy y2/y1>x2/x1, and the second layer includes an interface layer of the stoichiometric composition formed at an interface with the metal layer. The interface layer is higher in ratio of oxidation than the rest of the second layer.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: December 17, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Wensheng Wang
  • Patent number: 8592928
    Abstract: According to one embodiment, a magnetic random access memory includes a selection element formed on a semiconductor substrate, an interlayer dielectric film formed above the selection element, a contact layer formed in the interlayer dielectric film, and electrically connected to the selection element, a lower electrode layer made of a metal material, and electrically connected to the contact layer, a metal oxide insulating film made of an oxide of the metal material, and surrounding a side surface of the lower electrode layer, a magnetoresistive element formed on the lower electrode layer, an upper electrode layer formed on the magnetoresistive element, a sidewall insulating film formed on a side surface of the magnetoresistive element and a side surface of the upper electrode layer, and a bit line electrically connected to the upper electrode layer.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: November 26, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keiji Hosotani, Hiroyuki Kanaya, Takeshi Kajiyama
  • Publication number: 20130270523
    Abstract: A boron or boron containing dusting layer such as CoB or FeB is formed along one or both of top and bottom surfaces of a free layer at interfaces with a tunnel barrier layer and capping layer to improve thermal stability while maintaining other magnetic properties of a MTJ stack. Each dusting layer has a thickness from 0.2 to 20 Angstroms and may be used as deposited, or at temperatures up to 400° C. or higher, or following a subsequent anneal at 400° C. or higher. The free layer may be a single layer of CoFe, Co, CoFeB or CoFeNiB, or may include a non-magnetic insertion layer. The resulting MTJ is suitable for STT-MRAM memory elements or spintronic devices. Perpendicular magnetic anisotropy is maintained in the free layer at temperatures up to 400° C. or higher. Ku enhancement is achieved and the retention time of a memory cell for STT-MRAM designs is increased.
    Type: Application
    Filed: April 17, 2012
    Publication date: October 17, 2013
    Applicant: HEADWAY TECHNOLOGIES, INC.
    Inventors: Yu-Jen Wang, Witold Kula, Ru-Ying Tong, Guenole Jan
  • Publication number: 20130249028
    Abstract: A method of fabricating a magnetic memory according to an embodiment includes: forming a separation layer on a first substrate; sequentially forming a first ferromagnetic layer, a first nonmagnetic layer, and a second ferromagnetic layer on the separation layer, at least one of the first and the second ferromagnetic layers having a single crystal structure; forming a first conductive bonding layer on the second ferromagnetic layer; forming a second conductive bonding layer on a second substrate, on which a transistor and a wiring are formed, the second conductive bonding layer electrically connecting to the transistor; arranging the first and second substrate so that the first conductive bonding layer and the second conductive bonding layer are opposed to each other, and bonding the first and the second conductive bonding layers to each other; and separating the first substrate from the first ferromagnetic layer by using the separation layer.
    Type: Application
    Filed: September 20, 2012
    Publication date: September 26, 2013
    Inventors: Chikayoshi KAMATA, Minoru Amano, Tadaomi Daibou, Junichi Ito
  • Publication number: 20130241014
    Abstract: A magnetoresistive random access memory (MRAM) package may include an MRAM die, a package defining a cavity and an exterior surface, and a magnetic security structure disposed within the cavity or on the exterior surface of the package. The MRAM die may be disposed in the cavity of the package, and the magnetic security structure may include at least three layers including a permanent magnetic layer and a soft magnetic layer.
    Type: Application
    Filed: March 13, 2012
    Publication date: September 19, 2013
    Applicant: HONEYWELL INTERNATIONAL INC.
    Inventors: Romney R. Katti, James L. Tucker, Anuj Kohli
  • Publication number: 20130244343
    Abstract: One aspect of the present invention provides a method for preparing a thin film device with an insulation layer from a dry polyimide film and a method for preparing a common mode filter using the same. A method for preparing a thin film device according to this aspect of the present invention includes the steps of forming at least one first conductive pattern on a substrate; placing a dry polyimide film on the first conductive pattern; applying a force to the dry polyimide film such that the dry polyimide film fills spaces in the first conductive pattern; and forming at least one second conductive pattern on the dry polyimide film.
    Type: Application
    Filed: March 19, 2012
    Publication date: September 19, 2013
    Applicant: INPAQ TECHNOLOGY CO., LTD.
    Inventors: HUAI LUH CHANG, YU CHIA CHANG, MING FUNG HSIEH, HSIU MEI HSU, KUO JUNG FU
  • Patent number: 8530887
    Abstract: A magnetoresistive element according to an embodiment includes: a first magnetic layer; a tunnel barrier layer on the first magnetic layer; a second magnetic layer placed on the tunnel barrier layer and containing CoFe; and a nonmagnetic layer placed on the second magnetic layer, and containing nitrogen and at least one element selected from the group consisting of B, Ta, Zr, Al, and Ce.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: September 10, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Eiji Kitagawa, Tadashi Kai, Tadaomi Daibou, Yutaka Hashimoto, Hiroaki Yoda
  • Publication number: 20130224887
    Abstract: A laminated magnetic core, which has a number of magnetic layers and a number of insulation layers which are arranged so that an insulation layer lies between each vertically adjacent pair of magnetic layers, is formed in a method that forms the magnetic layers with an electroplating process, and the insulation layers with a sputter depositing process.
    Type: Application
    Filed: February 28, 2012
    Publication date: August 29, 2013
    Inventors: Dok Won Lee, Andrei Papou, William French, Peter J. Hopper
  • Publication number: 20130221195
    Abstract: Apparatus and methods of manufacturing an image sensor and inertial navigation sensors encapsulated within a single package. The single package may encapsulate one integrated circuit die comprising the imaging sensor and the inertial navigation sensors. Alternatively, the single package may encapsulate a plurality of integrated circuit dice comprising the imaging sensor and the inertial navigation sensors.
    Type: Application
    Filed: February 29, 2012
    Publication date: August 29, 2013
    Applicant: RESEARCH IN MOTION LIMITED
    Inventor: Marc Adam Kennedy
  • Patent number: 8518718
    Abstract: A method for forming a memory device includes forming a cavity having an inner surface with an undulating profile in a substrate, depositing a ferromagnetic material in the cavity, forming a reading element on the substrate proximate to a portion of the ferromagnetic material, and forming a writing element on the substrate proximate to a second portion of the ferromagnetic material.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: August 27, 2013
    Assignee: International Business Machines Corporation
    Inventors: Eric A. Joseph, Stuart S. P. Parkin, Mary B. Rothwell
  • Publication number: 20130168808
    Abstract: Magnetic laminations are formed in the openings of a first non-conductive structure, which is formed in the opening of a second non-conductive structure that has a maximum aspect ratio that is less than the maximum aspect ratio of the first non-conductive structure. The second non-conductive structure is more crack resistant than the first non-conductive structure, and thereby protects the first non-conductive structure and the magnetic laminations from environmental contaminants.
    Type: Application
    Filed: December 30, 2011
    Publication date: July 4, 2013
    Inventors: Andrei Papou, William French, Peter J. Hopper
  • Publication number: 20130171741
    Abstract: A method for fabricating a variable resistance memory device in accordance with an embodiment of the present invention includes: sequentially forming a first conductive layer and a variable resistance layer on a substrate; forming stacked structures in which first conductive lines and variable resistance lines are sequentially stacked by selectively etching the variable resistance layer and the first conductive layer; forming an insulating layer to fill a space between the stacked structures; forming a second conductive layer on the insulating layer and the stacked structures; and forming a second conductive line and a variable resistance pattern by etching the second conductive layer and the variable resistance line using mask patterns in a line type extending in a direction intersecting the stacked structures.
    Type: Application
    Filed: August 27, 2012
    Publication date: July 4, 2013
    Inventor: Sang-Min HWANG
  • Publication number: 20130157385
    Abstract: A method for fabricating a semiconductor device includes forming a bottom-electrode metal layer over a substrate, planarizing the bottom-electrode metal layer by a first thickness through a chemical mechanical polishing (CMP) process, etching the bottom-electrode metal layer by a second thickness through a wet etching process, forming a plurality of layers of a magnetic tunneling junction (MTJ) element over the bottom-electrode metal layer, forming a top electrode over the plurality of layers, and forming the MTJ element and a bottom electrode by etching the plurality of layers and the bottom-electrode metal layer using the top electrode as an etch mask.
    Type: Application
    Filed: June 21, 2012
    Publication date: June 20, 2013
    Inventors: Bo Kyoung JUNG, Min Suk Lee
  • Publication number: 20130157383
    Abstract: A method for fabricating a semiconductor device includes forming a metal layer on a substrate, forming a plurality of layers of a magnetic tunnel junction (MTJ) element on the metal layer, forming a carbon layer including a hole, wherein the hole penetrates through the carbon layer, forming a metal pattern in the hole of the carbon layer, removing the carbon layer; and patterning the plurality of layers of the MTJ element using the metal pattern as an etching mask.
    Type: Application
    Filed: June 21, 2012
    Publication date: June 20, 2013
    Inventor: Sang Hoon CHO
  • Publication number: 20130157382
    Abstract: A method according to one embodiment includes depositing a dielectric hard mask layer above a polymer mask under-layer; forming a photoresist mask above the hard mask layer; transferring the image of the photoresist mask onto the hard mask layer using reactive ion etching, thereby defining a hard mask; determining that a critical dimension bias of the hard mask is within or outside a specification; and changing a level of an input source power used during a subsequent reactive ion etching step to move the critical dimension bias towards a target critical dimension bias when the critical dimension bias of the hard mask is outside the specification. Additional embodiments are also disclosed.
    Type: Application
    Filed: December 16, 2011
    Publication date: June 20, 2013
    Applicant: Hitachi Global Storage Technologies Netherlands B.V.
    Inventor: Guomin Mao
  • Publication number: 20130155759
    Abstract: Test structures, methods of manufacturing thereof, test methods, and magnetic random access memory (MRAM) arrays are disclosed. In one embodiment, a test structure is disclosed. The test structure includes an MRAM cell having a magnetic tunnel junction (MTJ) and a transistor coupled to the MTJ. The test structure includes a test node coupled between the MTJ and the transistor, and a contact pad coupled to the test node.
    Type: Application
    Filed: December 16, 2011
    Publication date: June 20, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ya-Chen Kao, Tien-Wei Chiang, Chun-Jung Lin
  • Publication number: 20130154036
    Abstract: A method and system provide a magnetic junction usable in a magnetic device. The magnetic junction includes a pinned layer, a nonmagnetic spacer layer, a free layer, at least one insulating layer, and at least one magnetic insertion layer adjoining the at least one insulating layer. The nonmagnetic spacer layer is between the pinned layer and the free layer. The at least one insulating layer is adjacent to at least one of the free layer and the pinned layer. The at least one magnetic insertion layer adjoins the at least one insulating layer. In some aspects, the insulating layer(s) include at least one of magnesium oxide, aluminum oxide, tantalum oxide, ruthenium oxide, titanium oxide, and nickel oxide The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.
    Type: Application
    Filed: December 20, 2011
    Publication date: June 20, 2013
    Applicant: Samsung Electronics Co., LTD.
    Inventors: Xueti Tang, Dmytro Apalkov, Steven M. Watts, Kiseok Moon, Vladimir Nikitin
  • Publication number: 20130157384
    Abstract: A method for fabricating a semiconductor device includes forming a first insulation layer over a bottom layer, selectively removing a portion the first insulation layer to form a first trench that exposes the bottom layer, forming spacers on inner sidewalls of the first trench; forming a pillar-shaped second insulation layer in the first trench between the spacers, removing the spacers to form a second trench between the pillar-shaped second insulation layer and the first insulation layer, and burying a conductive layer in the second trench.
    Type: Application
    Filed: June 21, 2012
    Publication date: June 20, 2013
    Inventor: Jung Woo PARK
  • Patent number: 8466526
    Abstract: A Hall sensor has a P-type semiconductor substrate and a Hall sensing portion having a square shape and an N-type conductivity disposed on a surface of the semiconductor substrate. The Hall sensor includes Hall voltage output terminals having the same shape with each other, and control current input terminals having the same shape with each other. The Hall voltage output terminals are disposed at respective ones of four vertices of the Hall sensing portion. The control current input terminals include pairs of control current input terminals disposed at respective ones of the four vertices of the Hall sensing portion and arranged on both sides of respective ones of the Hall voltage output terminals in spaced apart relation from the Hall voltage output terminals so as to prevent electrical connection between the control current input terminals and the Hall voltage output terminals.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: June 18, 2013
    Assignee: Seiko Instruments Inc.
    Inventors: Takaaki Hioka, Toshihiko Omi
  • Publication number: 20130146997
    Abstract: A method of manufacturing a magnetic device includes forming a stack structure, the stack structure including a magnetic layer, and etching the stack structure by using an etching gas, the etching gas including at least 80% by volume of H2 gas.
    Type: Application
    Filed: August 31, 2012
    Publication date: June 13, 2013
    Inventors: Woo-cheol LEE, Tokashiki KEN, Hyung-joon KWON, Myung-hoon JUNG
  • Publication number: 20130119494
    Abstract: A memory device may comprise a magnetic tunnel junction (MTJ) stack, a bottom electrode (BE) layer, and a contact layer. The MTJ stack may include a free layer, a barrier, and a pinned layer. The BE layer may be coupled to the MTJ stack, and encapsulated in a planarized layer. The BE layer may also have a substantial common axis with the MTJ stack. The contact layer may be embedded in the BE layer, and form an interface between the BE layer and the MTJ stack.
    Type: Application
    Filed: November 10, 2011
    Publication date: May 16, 2013
    Applicant: QUALCOMM Incorporated
    Inventors: Xia Li, Seung H. Kang, Matthew M. Nowak