Processes Or Apparatus Peculiar To Manufacture Or Treatment Of These Devices Or Of Parts Thereof (epo) Patents (Class 257/E43.006)
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Publication number: 20120139019Abstract: A method of manufacturing a magnetoresistive effect element includes forming a first electrode above a substrate, forming a metal layer of a metal material above the first electrode, forming a first magnetic layer above the metal layer, forming a tunnel insulating film above the first magnetic layer, forming a second magnetic layer above the tunnel insulating film, forming a second electrode layer above the second magnetic layer, patterning the second electrode layer, patterning the second magnetic layer, the tunnel insulating film, the first magnetic layer and the metal layer, while depositing sputtered particles of the metal film on side walls of the second magnetic layer, the tunnel insulating film, the first magnetic layer and the metal layer to form a sidewall metal layer, and oxidizing the sidewall metal layer to form an insulative sidewall metal oxide layer.Type: ApplicationFiled: November 7, 2011Publication date: June 7, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Yoshihisa IBA
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Publication number: 20120135543Abstract: A method of fabricating a magnetic tunnel junction structure includes forming a magnetic tunnel junction layer on a substrate. A mask pattern is formed on a region of the second magnetic layer. A magnetic tunnel junction layer pattern and a sidewall dielectric layer pattern on at least one sidewall of the magnetic tunnel junction layer pattern are formed by performing at least one etch process and at least one oxidation process multiple times. The at least one etch process may include a first etch process to etch a portion of the magnetic tunnel junction layer using an inert gas and the mask pattern to form a first etch product. The at least one oxidation process may include a first oxidation process to oxidize the first etch product attached on an etched side of the magnetic tunnel junction layer.Type: ApplicationFiled: November 1, 2011Publication date: May 31, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hee-Ju SHIN, Jun-Ho JEONG, Jang-Eun LEE, Se-Chung OH
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Patent number: 8188558Abstract: In order to increase an efficiency of spin transfer and thereby reduce the required switching current, a current perpendicular to plane (CPP) magnetic element for a memory device includes either one or both of a free magnetic layer, which has an electronically reflective surface, and a permanent magnet layer, which has perpendicular anisotropy to bias the free magnetic layer.Type: GrantFiled: June 27, 2011Date of Patent: May 29, 2012Assignee: Seagate Technology LLCInventors: Dexin Wang, Dimitar V. Dimitrov, Song S. Xue, Insik Jin
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Publication number: 20120115253Abstract: A method for manufacturing a semiconductor apparatus includes forming a semiconductor device on a principal surface of a substrate, in which the semiconductor device includes an interconnect layer, forming a buffer film which covers the semiconductor device and prevents diffusion of a magnetic material, and forming a magnetic shielding film which covers the buffer film and includes the magnetic material.Type: ApplicationFiled: November 4, 2011Publication date: May 10, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Kishou Kaneko, Naoya Inoue, Yoshihiro Hayashi
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Publication number: 20120106233Abstract: A system includes a continuous thin-film ferromagnetic layer, N magnetic tunnel junction (MTJ) devices, and N write structures. The continuous thin-film ferromagnetic layer includes N modified regions. Each of the N modified regions is configured to stabilize a magnetic domain wall located in the continuous thin-film ferromagnetic layer. Each of the N MTJ devices includes one of N portions of the continuous thin-film ferromagnetic layer. Adjacent MTJ devices of the N MTJ devices are separated by one of the N modified regions. Each of the N write structures is configured to receive current and generate a magnetic field that magnetizes a different one of the N portions of the continuous thin-film ferromagnetic layer. N is an integer greater than 2.Type: ApplicationFiled: October 29, 2010Publication date: May 3, 2012Applicant: Honeywell International Inc.Inventor: Romney R. Katti
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Patent number: 8163569Abstract: Provided are a magnetic memory device and a method of forming the same. The method may include forming a pinning pattern on a substrate; forming a first interlayer insulating layer that exposes the pinning pattern on the substrate; forming a pinned layer, a tunneling barrier layer and a second magnetic conductive layer on the pinning pattern; and forming a pinned pattern, a tunnel barrier pattern and a second magnetic conductive pattern by performing a patterning process on the pinned layer, the tunnel barrier layer and the second magnetic conductive layer.Type: GrantFiled: March 17, 2011Date of Patent: April 24, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: KyungTae Nam, Byeungchul Kim, Seung-Yeol Lee
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Patent number: 8153449Abstract: A method for packaging a semiconductor device. The method includes: providing a dielectric layer over the semiconductor device; determining patterns and placement of material on the dielectric layer to provide a predetermined magnetic or electric effect for the device, such effects being provided on the device from such patterned and placed material solely by electrical or magnetic waves coupled between such material and the device; and forming the material in the determined patterns and placement to provide the predetermined effects.Type: GrantFiled: May 23, 2011Date of Patent: April 10, 2012Assignee: Raytheon CompanyInventors: Michael G. Adlerstein, Francois Y. Colomb
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Publication number: 20120074511Abstract: A magnetic memory according to an embodiment includes: at least one memory cell comprising a magnetoresistive element as a memory element, and first and second electrodes that energize the magnetoresistive element. The magnetoresistive element includes: a first magnetic layer having a variable magnetization direction perpendicular to a film plane; a tunnel barrier layer on the first magnetic layer; and a second magnetic layer on the tunnel barrier layer, and having a fixed magnetization direction perpendicular to the film plane. The first magnetic layer including: a first region; and a second region outside the first region so as to surround the first region, and having a smaller perpendicular magnetic anisotropy energy than that of the first region. The second magnetic layer including: a third region; and a fourth region outside the third region, and having a smaller perpendicular magnetic anisotropy energy than that of the third region.Type: ApplicationFiled: September 13, 2011Publication date: March 29, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Shigeki TAKAHASHI, Yuichi OHSAWA, Junichi ITO, Chikayoshi KAMATA, Saori KASHIWADA, Minoru AMANO, Hiroaki YODA
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Publication number: 20120077288Abstract: According to the present invention, a method of fabricating a semiconductor device is provided including forming a first interlayer insulating film 11, a crystalline conductive film 21, a first conductive film 23, a ferroelectric film 24 and a second conductive film 25 on a silicon substrate I in sequence, forming a conductive cover film 18 on the second conductive film 25, forming a hard mask 26a on the conductive cover film 18, forming a capacitor upon etching the conductive cover film 18, the second conductive film 25, the ferroelectric film 24 and the first conductive film 23 using the hard mask 26a as an etching mask in areas exposed from the hard mask 26a, and etching the hard mask 26a and the crystalline conductive film 21 exposed from the lower electrode 23a using an etching condition under which the hard mask 26a is etched.Type: ApplicationFiled: December 7, 2011Publication date: March 29, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Wensheng Wang
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Publication number: 20120068236Abstract: A non-uniform switching based non-volatile magnetic memory element includes a fixed layer, a barrier layer formed on top of the fixed layer, a first free layer formed on top of the barrier layer, a non-uniform switching layer (NSL) formed on top of the first free layer, and a second free layer formed on top of the non-uniform switching layer. Switching current is applied, in a direction that is substantially perpendicular to the fixed layer, barrier layer, first free layer, non-uniform switching layer and the second free layer causing switching between states of the first free layer, second free layer and non-uniform switching layer with substantially reduced switching current.Type: ApplicationFiled: November 28, 2011Publication date: March 22, 2012Applicant: AVALANCHE TECHNOLOGY, INC.Inventors: Rajiv Yadav Ranjan, Petro Estakhri, Mahmud Assar, Parviz Keshtbod
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Publication number: 20120068779Abstract: Oscillators and methods of manufacturing and operating the same are provided, the oscillators include a pinned layer, a free layer and a barrier layer having at least one filament between the pinned layer and the free layer. The pinned layer may have a fixed magnetization direction. The free layer corresponding to the pinned layer. The at least one filament in the barrier layer may be formed by applying a voltage between the pinned layer and the free layer. The oscillators may be operated by inducing precession of a magnetic moment of at least one region of the free layer that corresponds to the at least one filament, and detecting a resistance change of the oscillator due to the precession.Type: ApplicationFiled: February 25, 2011Publication date: March 22, 2012Applicant: Samsung Electronics Co., Ltd.Inventors: Sung-chul Lee, Sun-ae Seo, Un-hwan Pi, Kee-won Kim, Kwang-seok Kim
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Publication number: 20120068698Abstract: A structure of TMR includes two magnetic tunneling junction (MTJ) devices with the same pattern and same magnetic film stack on a same conducting bottom electrode and a parallel connection of conducting top electrode. Each MTJ device includes a pinned layer on the bottom electrode, having a pinned magnetization; a non-magnetic tunneling on the pinned layer; and a free layer on the tunneling layer, having a free magnetization. These two MTJ devices have a collinear of easy-axis and their pinned magnetizations all are parallel to a same pinned direction which has an angle of 45 degree to easy-axis; their free magnetizations initially are parallel to the easy-axis but directions are mutual anti-parallel by applying a current generated ampere field. The magnetic field sensing direction is perpendicular to the easy-axis on the substrate.Type: ApplicationFiled: April 29, 2011Publication date: March 22, 2012Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Young-Shying Chen, Cheng-Tyng Yen
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Publication number: 20120068283Abstract: A semiconductor storage device according to the present embodiment includes a selection element formed on a surface of a semiconductor substrate. A lower electrode is connected to the selection element. A magnetic tunnel junction element is provided on the lower electrode. An upper electrode is provided on the magnetic tunnel junction element. A growth layer is provided on the upper electrode and is composed of a conductive material and has a larger area than the upper electrode when viewed from above the surface of the semiconductor substrate. A wiring line is provided on the growth layer.Type: ApplicationFiled: September 12, 2011Publication date: March 22, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Keiji HOSOTANI, Hiroyuki Kanaya
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Publication number: 20120064640Abstract: A method of forming a CPP MTJ MRAM element that utilizes transfer of spin angular momentum as a mechanism for changing the magnetic moment direction of a free layer. The device includes a tunneling barrier layer of MgO and a non-magnetic CPP layer of Cu or Cr and utilizes a novel synthetic free layer having three ferromagnetic layers mutually exchange coupled in pairwise configurations. The free layer comprises an inner ferromagnetic and two outer ferromagnetic layers, with the inner layer being ferromagnetically exchange coupled to one outer layer and anti-ferromagnetically exchange coupled to the other outer layer. The ferromagnetic coupling is very strong across an ultra-thin layer of Ta, Hf or Zr of thickness preferably less than 0.4 nm.Type: ApplicationFiled: November 7, 2011Publication date: March 15, 2012Inventors: Yimin Guo, Cheng Horng, Ru-Ying Tong
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Publication number: 20120058575Abstract: A dual spin filter that minimizes spin-transfer magnetization switching current (Jc) while achieving a high dR/R in STT-RAM devices is disclosed. The bottom spin valve has a MgO tunnel barrier layer formed with a natural oxidation process to achieve low RA, a CoFe/Ru/CoFeB—CoFe pinned layer, and a CoFeB/FeSiO/CoFeB composite free layer with a middle nanocurrent channel (NCC) layer to minimize Jc0. The NCC layer may have be a composite wherein conductive M(Si) grains are magnetically coupled with adjacent ferromagnetic layers and are formed in an oxide, nitride, or oxynitride insulator matrix. The upper spin valve has a Cu spacer to lower the free layer damping constant. A high annealing temperature of 360° C. is used to increase the MR ratio above 100%. A Jc0 of less than 1×106 A/cm2 is expected based on quasistatic measurements of a MTJ with a similar MgO tunnel barrier and composite free layer.Type: ApplicationFiled: November 4, 2011Publication date: March 8, 2012Inventors: Cheng T. Horng, Ru-Ying Tong
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Publication number: 20120049302Abstract: A magneto-resistance effect element includes: a first magnetization layer of which a magnetization is substantially fixed in one direction; a second magnetization layer of which a magnetization is rotated in accordance with an external magnetic field; an intermediate layer which contains insulating portions and magnetic metallic portions and which is provided between the first magnetic layer and the second magnetic layer; and a pair of electrodes to flow current in a direction perpendicular to a film surface of a multilayered film made of the first magnetic layer, the intermediate layer and the second magnetic layer; wherein the magnetic metallic portions of the intermediate layer contain non-ferromagnetic metal.Type: ApplicationFiled: November 8, 2011Publication date: March 1, 2012Applicants: TDK CORPORATION, KABUSHIKI KAISHA TOSHIBAInventors: Hiromi FUKE, Susumu HASHIMOTO, Masayuki TAKAGISHI, Hitoshi IWASAKI
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Publication number: 20120033478Abstract: A non-volatile memory device and a method for forming the same are disclosed, which relate to a ferroelectric memory device having non-volatile characteristics. The non-volatile memory device includes a control gate configured to receive a read voltage, an insulation film formed over the control gate, a metal layer formed over the insulation film, configured to include a channel region, and a drain region and source region at both ends of the channel region, a ferroelectric layer formed over the channel region of the metal layer, and a program and read gate formed over the ferroelectric layer. A write operation of data corresponding to a resistance state of the channel region is performed by changing polarity of the ferroelectric layer in response to a voltage applied to the program and read gate, the drain and source regions, and the control gate.Type: ApplicationFiled: August 5, 2011Publication date: February 9, 2012Applicant: Hynix Semiconductor Inc.Inventor: Hee Bok KANG
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Publication number: 20120034712Abstract: A method for manufacturing a semiconductor device including a ferroelectric capacitor formed over a semiconductor substrate, wherein the ferroelectric capacitor including a lower electrode, a ferroelectric film formed on the lower electrode, and an upper electrode formed on the ferroelectric film, and the upper electrode including a first conductive film formed of a first conductive noble metal oxide, and a second conductive film formed of a metal nitride compound formed on the first conductive film.Type: ApplicationFiled: October 25, 2011Publication date: February 9, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Wensheng Wang
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Publication number: 20120028373Abstract: A composite hard mask is disclosed that prevents build up of metal etch residue in a MRAM device during etch processes that define an MTJ shape. As a result, MTJ shape integrity is substantially improved. The hard mask has a lower non-magnetic spacer, a middle conductive layer, and an upper sacrificial dielectric layer. The non-magnetic spacer serves as an etch stop during a pattern transfer with fluorocarbon plasma through the conductive layer. A photoresist pattern is transferred through the dielectric layer with a first fluorocarbon etch. Then the photoresist is removed and a second fluorocarbon etch transfers the pattern through the conductive layer. The dielectric layer protects the top surface of the conductive layer during the second fluorocarbon etch and during a substantial portion of a third RIE step with a gas comprised of C, H, and O that transfers the pattern through the underlying MTJ layers.Type: ApplicationFiled: July 30, 2010Publication date: February 2, 2012Inventors: Rodolfo Belen, Rongfu Xiao, Tom Zhong, Witold Kula, Chyu-Jiuh Torng
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Patent number: 8089112Abstract: The present invention makes it possible to obtain: a semiconductor device capable of forming a highly reliable upper wire without a harmful influence on the properties of the magnetic material for an MTJ device; and the manufacturing method thereof. Plasma treatment is applied with reducible NH3 or H2 as pretreatment. Thereafter, a tensile stress silicon nitride film to impose tensile stress on an MTJ device is formed over a clad layer and over an interlayer dielectric film where the clad layer is not formed. Successively, a compressive stress silicon nitride film to impose compressive stress on the MTJ device is formed over the tensile stress silicon nitride film. The conditions for forming the tensile stress silicon nitride film and the compressive stress silicon nitride film are as follows: a parallel plate type plasma CVD apparatus is used; the RF power is set in the range of 0.03 to 0.4 W/cm2; and the film forming temperature is set in the range of 200° C. to 350° C.Type: GrantFiled: March 22, 2011Date of Patent: January 3, 2012Assignee: Renesas Electronics CorporationInventors: Tatsunori Murata, Mikio Tsujiuchi
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Publication number: 20110316103Abstract: Disclosed herein is a storage element, including: a storage layer configured to retain information based on a magnetization state of a magnetic material; and a magnetization pinned layer configured to be provided for the storage layer with intermediary of a tunnel barrier layer, wherein the tunnel barrier layer has a thickness not less than or equal to 0.1 nm to not more than or equal to 0.6 nm and interface roughness less than 0.5 nm, and information is stored in the storage layer through change in direction of magnetization of the storage layer by applying a current in a stacking direction and injecting a spin-polarized electron.Type: ApplicationFiled: June 17, 2011Publication date: December 29, 2011Applicant: SONY CORPORATIONInventors: Hiroyuki Uchida, Masanori Hosomi, Hiroyuki Ohmori, Kazuhiro Bessho, Yutaka Higo, Kazutaka Yamane
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Publication number: 20110275163Abstract: The use of a monolayer or partial monolayer sequencing process, such as atomic layer deposition (ALD), to form a zirconium substituted layer of barium titanium oxide (BaTiO3), produces a reliable ferroelectric structure for use in a variety of electronic devices such as a dielectric in nonvolatile random access memories (NVRAM), tunable dielectrics for multi layer ceramic capacitors (MLCC), infrared sensors and electro-optic modulators. In various embodiments, structures can be formed by depositing alternating layers of barium titanate and barium zirconate by ALD on a substrate surface using precursor chemicals, and repeating to form a sequentially deposited interleaved structure of desired thickness and composition. Such a layer may be used as the gate insulator of a MOSFET, or as a capacitor dielectric.Type: ApplicationFiled: July 21, 2011Publication date: November 10, 2011Inventors: Kie Y. Ahn, Leonard Forbes
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Publication number: 20110260270Abstract: The performance of an MR device has been improved by inserting one or more Magneto-Resistance Enhancing Layers (MRELs) into approximately the center of one or more of the active layers (such as API, SIL, FGL, and Free layers). An MREL is a layer of a low band gap, high electron mobility semiconductor such as ZnO or a semimetal such as Bi.Type: ApplicationFiled: April 26, 2010Publication date: October 27, 2011Inventors: Kunliang Zhang, Min Li, Yuchen Zhou
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Publication number: 20110244599Abstract: A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane.Type: ApplicationFiled: March 31, 2010Publication date: October 6, 2011Applicant: EVERSPIN TECHNOLOGIES, INC.Inventors: Renu WHIG, Phillip MATHER, Kenneth SMITH, Sanjeev AGGARWAL, Jon SLAUGHTER, Nicholas RIZZO
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Publication number: 20110229986Abstract: Provided are a magnetic memory device and a method of forming the same. The method may include forming a pinning pattern on a substrate; forming a first interlayer insulating layer that exposes the pinning pattern on the substrate; forming a pinned layer, a tunneling barrier layer and a second magnetic conductive layer on the pinning pattern; and forming a pinned pattern, a tunnel barrier pattern and a second magnetic conductive pattern by performing a patterning process on the pinned layer, the tunnel barrier layer and the second magnetic conductive layer.Type: ApplicationFiled: March 17, 2011Publication date: September 22, 2011Inventors: KyungTae Nam, Byeungchul Kim, Seung-Yeol Lee
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Publication number: 20110204458Abstract: The semiconductor device which has a memory cell including the TMR film with which memory accuracy does not deteriorate, and its manufacturing method are obtained. A TMR element (a TMR film, a TMR upper electrode) is selectively formed in the region which corresponds in plan view on a TMR lower electrode in a part of formation area of a digit line. A TMR upper electrode is formed by 30-100 nm thickness of Ta, and functions also as a hard mask at the time of a manufacturing process. The interlayer insulation film formed from LT-SiN on the whole surface of a TMR element and the upper surface of a TMR lower electrode is formed, and the interlayer insulation film which covers the whole surface comprising the side surface of a TMR lower electrode, and includes LT-SiN is formed. The interlayer insulation film which covers the whole surface and includes SiO2 is formed.Type: ApplicationFiled: May 3, 2011Publication date: August 25, 2011Inventors: Haruo FURUTA, Ryoji Matsuda, Shuichi Ueno, Takeharu Kuroiwa
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Patent number: 7999336Abstract: In order to increase an efficiency of spin transfer and thereby reduce the required switching current, a current perpendicular to plane (CPP) magnetic element for a memory device includes either one or both of a free magnetic layer, which has an electronically reflective surface, and a permanent magnet layer, which has perpendicular anisotropy to bias the free magnetic layer.Type: GrantFiled: April 24, 2008Date of Patent: August 16, 2011Assignee: Seagate Technology LLCInventors: Dexin Wang, Dimitar V. Dimitrov, Song S. Xue, Insik Jin
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Publication number: 20110189796Abstract: A method of forming an integrated circuit structure includes forming a bottom electrode layer over a substrate; forming magnetic tunnel junction (MTJ) layers over the bottom electrode layer; patterning the MTJ layers to form a MTJ stack; forming a dielectric layer covering the MTJ stack; forming an opening in the dielectric layer to expose a portion of the MTJ stack; filling the opening with a top electrode material; and performing a planarization to the top electrode material. After the step of performing the planarization, the top electrode material and the dielectric layer are patterned, wherein a first portion of the top electrode material in the opening forms a top electrode, and a second portion of the top electrode material forms a metal strip over the dielectric layer and connected to the top electrode.Type: ApplicationFiled: January 29, 2010Publication date: August 4, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jiech-Fun Lu, Shih-Chang Liu, Chia-Shiung Tsai
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Publication number: 20110177621Abstract: A magnetic tunnel junction cell having a free layer, a ferromagnetic pinned layer, and a barrier layer therebetween. The free layer has a central ferromagnetic portion and a stabilizing portion radially proximate the central ferromagnetic portion. The construction can be used for both in-plane magnetic memory cells where the magnetization orientation of the magnetic layer is in the stack film plane and out-of-plane magnetic memory cells where the magnetization orientation of the magnetic layer is out of the stack film plane, e.g., perpendicular to the stack plane.Type: ApplicationFiled: March 28, 2011Publication date: July 21, 2011Applicant: SEAGATE TECHNOLOGY LLCInventors: Kaizhong Gao, Haiwen Xi
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Publication number: 20110169114Abstract: Electronic devices that include (i) a magnetization controlling structure; (ii) a tunnel barrier structure; and (iii) a magnetization controllable structure including: a first polarizing layer; and a first stabilizing layer, wherein the tunnel barrier structure is between the magnetization controlling structure and the magnetization controlling structure and the first polarizing layer is between the first stabilizing layer and the tunnel barrier structure, wherein the electronic device has two stable overall magnetic configurations, and wherein a first unipolar current applied to the electronic device will cause the orientation of the magnetization controlling structure to reverse its orientation and a second unipolar current applied to the electronic device will cause the magnetization controllable structure to switch its magnetization in order to obtain one of the two stable overall magnetic configurations, wherein the second unipolar current has an amplitude that is less than the first unipolar current.Type: ApplicationFiled: March 24, 2011Publication date: July 14, 2011Applicant: SEAGATE TECHNOLOGY LLCInventors: Dimitar V. Dimitrov, Olle Gunnar Heinonen, Yiran Chen, Haiwen Xi, Xiaohua Lou
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Publication number: 20110151589Abstract: The invention relates to a method for producing a device comprising magnetic blocks magnetized in different directions, comprising steps of: a) forming, in a stack of one or more layers of at least one antiferromagnetic material and one or more layers of at least one ferromagnetic material resting on a substrate, at least one first block and at least one second block, said blocks being longilineal and separate and extending respectively in a first main direction and in a second main direction, the first and the second main direction forming between them a first non-zero angle ?, b) annealing said blocks at a temperature greater than the ordering temperature of said antiferromagnetic material or than the blocking temperature or than the Néel temperature of said antiferromagnetic material.Type: ApplicationFiled: December 17, 2010Publication date: June 23, 2011Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventor: Olivier REDON
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Publication number: 20110151587Abstract: A method of integrating a permanent bias magnet within a magnetoresistance sensor comprising depositing an alternating pattern of a metal material and a semiconductor material on or within a surface of an insulating substrate; depositing a mask on the surface of the insulating substrate to create an opening above the alternating pattern of metal material and semiconductor material; applying a magnetic paste within the opening above the alternating pattern of metal material and semiconductor material; curing the magnetic paste to form a hardened bias magnet; removing the mask; and magnetizing the hardened bias magnet by applying a strong magnetic field to the hardened bias magnet at a desired orientation.Type: ApplicationFiled: December 21, 2009Publication date: June 23, 2011Applicant: GENERAL ELECTRIC COMPANYInventor: William Hullinger Huber
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Publication number: 20110141792Abstract: Read/write structures for three-dimensional memories are disclosed. In one embodiment, a three-dimensional memory includes a plurality of data storage layers fabricated in parallel on top of one another to form a three-dimensional structure. Each data storage layer is able to store bits of data in the form of magnetic domains. The memory further includes a column of write elements that is operable to write a column of magnetic domains to the first data storage layer representing a column of bits. The first data storage layer is patterned into a plurality of magnetic conductors aligned transverse to the column of write elements. A control system may inject spin-polarized current pulses in the magnetic conductors to transfer the column of magnetic domains laterally within the first data storage layer. The control system may transfer of the column of magnetic domains perpendicularly from the first data storage layer to another data storage layer.Type: ApplicationFiled: December 15, 2009Publication date: June 16, 2011Inventors: Ozhan Ozatay, Bruce D. Terris
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Publication number: 20110133298Abstract: A system and method for forming a magnetic tunnel junction (MTJ) storage element utilizes a composite free layer structure. The MTJ element includes a stack comprising a pinned layer, a barrier layer, and a composite free layer. The composite free layer includes a first free layer, a superparamagnetic layer and a nonmagnetic spacer layer interspersed between the first free layer and the superparamagnetic layer. A thickness of the spacer layer controls a manner of magnetic coupling between the first free layer and the superparamagnetic layer.Type: ApplicationFiled: December 8, 2009Publication date: June 9, 2011Applicant: QUALCOMM INCORPORATEDInventors: Wei-Chuan Chen, Seung H. Kang
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Patent number: 7955868Abstract: A method of forming a micromagnetic device on a substrate including forming a first insulating layer above the substrate, a first seed layer above the first insulating layer, a first conductive winding layer above the first seed layer, and a second insulating layer above the first conductive winding layer. The method also includes forming a first magnetic core layer above the second insulating layer, a third insulating layer above the first magnetic core layer, and a second magnetic core layer above the third insulating layer. The method still further includes forming a fourth insulating layer above the second magnetic core layer, a second seed layer above the fourth insulating layer, and a second conductive winding layer above the second seed layer and in vias to the first conductive winding layer. The first and second conductive winding layers form a winding for the micromagnetic device.Type: GrantFiled: September 10, 2007Date of Patent: June 7, 2011Assignee: Enpirion, Inc.Inventors: Ashraf W. Lotfi, Trifon M. Liakopoulos, Robert W. Filas, Amrit Panda
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Publication number: 20110127998Abstract: An integrated circuit includes a leadframe, and a die having a top surface, a bottom surface, and a plurality of perimeter sides and including at least one magnetic field sensor element disposed proximate to the top surface, wherein the bottom surface is bonded to the leadframe. A molded magnetic material encapsulates the die and at least a portion of the leadframe, and provides a magnetic field substantially perpendicular to the top surface of the die. A non-magnetic material is disposed between the die and the molded magnetic material at least along perimeter sides of the die intersecting a lateral magnetic field component which is parallel to the top surface of the die.Type: ApplicationFiled: November 30, 2009Publication date: June 2, 2011Applicant: INFINEON TECHNOLOGIES AGInventors: Klaus Elian, Martin Petz, Uwe Schindler, Horst Theuss, Adolf Koller
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Publication number: 20110117677Abstract: Methods are presented for fabricating an MTJ element having a uniform vertical distance between its free layer and a bit line and, in addition, having a protective spacer layer formed abutting the lateral sides of the MTJ element to eliminate leakage currents between MTJ layers and the bit line. Each method forms a dielectric spacer layer on the lateral sides of the MTJ element and, depending on the method, includes an additional layer that protects the spacer layer during etching processes used to form a Cu damascene bit line. At various stages in the process, a dielectric layer is also formed to act as a CMP stop layer so that the capping layer on the MTJ element is not thinned by the CMP process that planarizes the surrounding insulation. Subsequent to planarization, the stop layer is removed by an anisotropic etch of such precision that the MTJ element capping layer is not reduced in thickness and serves to maintain uniform vertical distance between the bit line and the MTJ free layer.Type: ApplicationFiled: January 20, 2011Publication date: May 19, 2011Inventors: Jun Yuan, Liubo Hong, Mao-Min Chen
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Publication number: 20110111532Abstract: Methods of forming pattern structures and methods of manufacturing memory devices using the same are provided, the methods of forming pattern structures include forming an etching object layer on a substrate and performing a plasma reactive etching process on the etching object layer using an etching gas including at least ammonia (NH3) gas. The etching object layer includes a magnetic material or a phase change material.Type: ApplicationFiled: November 5, 2010Publication date: May 12, 2011Inventors: Yong-Hwan RYU, Jae-Seung HWANG, Sung-Un KWON, Kyoung-Ha EOM
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Publication number: 20110101432Abstract: A semiconductor device includes a capacitor, the capacitor includes a lower electrode, which includes platinum, provided above a semiconductor substrate; a first ferroelectric film, which includes lead zirconate titanate added with La, provided on the lower electrode; a second ferroelectric film, which includes lead zirconate titanate added with La, Ca, and Sr, provided directly on the first ferroelectric film, the second ferroelectric film having a thickness smaller than that of the first ferroelectric film and includes amounts of Ca and Sr greater than amounts of Ca and Sr that may be present in the first ferroelectric film; and an upper electrode, which includes a conductive oxide, provided on the second ferroelectric film.Type: ApplicationFiled: October 26, 2010Publication date: May 5, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Wensheng WANG
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Publication number: 20110104829Abstract: A method of carrying out a transfer of one or more first components or of a first layer onto a second substrate including: a) application and maintaining, by electrostatic effect, of the one or more first components or of the first layer, on a first substrate, made of a ferroelectric material, electrically charged, b) placing in contact, direct or by molecular adhesion, and transfer of the components or the layer onto a second substrate, and c) dismantling of the first substrate, leaving at least one part of the components or the layer on the second substrate.Type: ApplicationFiled: April 3, 2009Publication date: May 5, 2011Applicant: Commiss. A L'Energie Atom. ET Aux Energ. Alterna.Inventors: Jean-Sebastien Moulet, Lea Di Cioccio, Marion Migette
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Publication number: 20110104827Abstract: A method for fabricating a magnetoresistive random access memory (MRAM) includes forming a mask over a magnetic layer; forming a template on the mask; applying a diblock copolymer to the template; curing the diblock copolymer to form a first plurality of uniform shapes registered to the template; etching the mask to form a second plurality of uniform shapes; and etching the magnetic layer to form a third plurality of uniform shapes, the third plurality of uniform shapes comprising a plurality of magnetic tunnel junctions (MTJs). A diblock copolymer mask for fabricating a magnetoresistive random access memory (MRAM) includes a magnetic layer; a mask formed on the magnetic layer; a template formed on the mask; and a diblock copolymer mask comprising a plurality of uniform shapes formed on and registered to the template.Type: ApplicationFiled: November 4, 2009Publication date: May 5, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Michael C. Gaidis
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Publication number: 20110101477Abstract: A method for manufacturing magnetic field detection devices comprises the operations of manufacturing a magneto-resistive element comprising regions with metallic conduction and regions with semi-conductive conduction. The method comprises the following operations: forming metallic nano-particles to obtain regions with metallic conduction; providing a semiconductor substrate; and applying metallic nano-particles to the porous semiconductor substrate to obtain a disordered mesoscopic structure. A magnetic device comprises a spin valve, which comprises a plurality of layers arranged in a stack which in turn comprises at least one free magnetic layer able to be associated to a temporary magnetisation (MT), a spacer layer and a permanent magnetic layer associated to a permanent magnetisation (MP). The spacer element is obtained by means of a mesoscopic structure of nanoparticles in a metallic matrix produced in accordance with the inventive method for manufacturing magneto-resistive elements.Type: ApplicationFiled: November 8, 2010Publication date: May 5, 2011Applicant: C.R.F. Societa Consortile per AzioniInventors: Daniele Pullini, Brunetto Martorana, Piero Perlo
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Publication number: 20110084347Abstract: The present invention relates to a magnetic tunnel junction device and a manufacturing method thereof. The magnetic tunnel junction device includes i) a first magnetic layer having an switchable magnetization direction, ii) a nonmagnetic layer provided on the first magnetic layer, iii) a second magnetic layer provided on the nonmagnetic layer and having a fixed magnetization direction, iv) an oxidation-preventing layer provided on the second magnetic layer, v) a third magnetic layer provided on the oxidation-preventing layer and fixing the magnetization direction of the second magnetic layer through magnetic coupling with the second magnetic layer, and vi) an antiferromagnetic layer provided on the third magnetic layer and fixing a magnetization direction of the third magnetic layer.Type: ApplicationFiled: February 17, 2010Publication date: April 14, 2011Applicant: Korea Institute of Science and TechnologyInventors: Il-Jae Shin, Byoung-Chul Min, Kyung-Ho Shin
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Publication number: 20110086439Abstract: A method of manufacturing a magnetoresistive element includes a tunnel barrier forming step. The tunnel barrier forming step comprises a metal layer forming step of forming a metal layer to have a first thickness, a plasma processing step of performing a plasma treatment which exposes the metal layer to a plasma of an inert gas to etch the metal layer to have a second thickness smaller than the first thickness, and an oxidation step of oxidizing the metal layer having undergone the plasma treatment to form a metal oxide which forms a tunnel barrier.Type: ApplicationFiled: August 31, 2010Publication date: April 14, 2011Applicant: CANON ANELVA CORPORATIONInventor: Young-suk CHOI
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Publication number: 20110049655Abstract: A semiconductor device includes a substrate including an M2 patterned area. A VA pillar structure is formed over the M2 patterned area. The VA pillar structure includes a substractively patterned metal layer. The VA pillar structure is a sub-lithographic contact. An MTJ stack is formed over the oxide layer and the metal layer of the VA pillar. A size of the MTJ stack and a shape anisotropy of the MTJ stack are independent of a size and a shape anisotropy of the sub-lithographic contact.Type: ApplicationFiled: August 28, 2009Publication date: March 3, 2011Applicant: International Business Machines CorporationInventors: Solomon Assefa, Michael C. Gaidis, Eric A. Joseph, Eugene J. O'Sullivan
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Patent number: 7893511Abstract: An integrated circuit includes a plurality of magnetic tunneling junction stacks, each magnetic tunneling junction stack including a reference layer, a barrier layer and a free layer, wherein the plurality of magnetic tunneling junction stacks share a continuous common reference layer.Type: GrantFiled: July 17, 2008Date of Patent: February 22, 2011Assignee: Qimonda AGInventors: Manfred Ruehrig, Ulrich Klostermann, Michael Vieth
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Patent number: 7867788Abstract: A Spin-Dependent Tunnelling cell comprises a first barrier layer of a first material and a second barrier layer of a second material sandwiched between a first ferromagnetic layer and a second ferromagnetic layer. The first and second barrier layers are formed to a combined thicknesses so that a Tunnelling Magnetoresistance versus voltage characteristic of the cell has a maximum at a non-zero bias voltage.Type: GrantFiled: September 20, 2005Date of Patent: January 11, 2011Assignees: Freescale Semiconductor, Inc., Centre National de la Recherché Scientifique (CNRS), STMicroelectronics (Crolles 2) SASInventors: De Come Buttet, Michel Hehn, Stephane Zoll
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Publication number: 20100330707Abstract: A method for fabricating a device includes forming a first insulation layer to cover a removable mask and a device structure that has been defined by the mask. The device structure is below the mask. The mask is lifted off to expose a top portion of the device structure. A conductive island structure is formed over the first insulation layer and the exposed top portion of the device structure. The first insulation layer and the conductive island structure are covered with a second insulation layer. A contact is formed through the second insulation layer to the conductive island structure.Type: ApplicationFiled: January 26, 2007Publication date: December 30, 2010Inventors: Xin Jiang, Stuart Stephen Papworth Parkin, Jonathan Sun
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Publication number: 20100289098Abstract: A magnetic tunnel junction (MTJ) device and fabrication method is disclosed. In a particular embodiment, a method is disclosed that includes forming a magnetic tunnel junction (MTJ) device on a structure that includes a bottom cap layer and a bottom metal-filled trench having a normal axis, the magnetic tunnel junction device including a bottom electrode, magnetic tunnel junction layers, a magnetic tunnel junction seal layer, a top electrode, and a logic cap layer, the magnetic tunnel junction device having an MTJ axis that is offset from the normal axis.Type: ApplicationFiled: May 14, 2009Publication date: November 18, 2010Applicant: QUALCOMM IncorporatedInventors: Xia Li, Seung H. Kang, Xiaochun Zhu
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Publication number: 20100276768Abstract: A magnetic tunnel junction device comprises a substrate including a patterned wiring layer. A magnetic tunnel junction (MTJ) stack is formed over the wiring layer. A low-conductivity layer is formed over the MTJ stack and a conductive hard mask is formed thereon. A spacer material is then deposited that includes a different electrical conductivity than the low conductivity layer. The spacer material is etched from horizontal surfaces so that the spacer material remains only on sidewalls of the hard mask and a stud. A further etch process leaves behind the sidewall-spacer material as a conductive link between a free magnetic layer and the conductive hard mask, around the low-conductivity layer. A difference in electrical conductivity between the stud and the spacer material enhances current flow along the edges of the free layer within the MTJ stack and through the spacer material formed on the sidewalls.Type: ApplicationFiled: April 30, 2009Publication date: November 4, 2010Applicant: International Business Machines CorporationInventor: MICHAEL C. GAIDIS