Abstract: A memory device includes an array of memory structures disposed in rows and columns and constructed over a substrate, each memory structure comprising a first signal electrode, a second signal electrode, and a resistive layer coupled to the first signal electrode and the second signal electrode; a plurality of word lines connected to the first signal electrodes of a row of memory cells; and a plurality of bit lines connected to the second signal electrodes of a column of memory cells.

Abstract: Methods of forming a phase change material are disclosed. The method includes forming a chalcogenide compound on a substrate and simultaneously applying a bias voltage to the substrate to alter the stoichiometry of the chalcogenide compound. In another embodiment, the method includes positioning a substrate and a deposition target having a first stoichiometry in a deposition chamber. A plasma is generated in the deposition chamber to form a phase change material on the substrate. The phase change material has a stoichiometry similar to the first stoichiometry. A bias voltage is applied to the substrate to convert the stoichiometry of the phase change material to a second stoichiometry. A phase change material, a phase change random access memory device, and a semiconductor structure are also disclosed.

Abstract: Provided is a nonvolatile memory element which has a small variation in operation and allow stable operation. The nonvolatile memory element includes: a first electrode (102); a second electrode (106); a variable resistance layer (105) which is formed between the electrodes (102 and 106) and is connected to the electrodes (102 and 106), and which reversibly changes between a high resistance state and a low resistance state according to a polarity of a voltage applied between the electrodes (102 and 106); and a fixed resistance layer (104) which has a resistance value that is 0.1 and 10 times as large as a resistance value of the variable resistance layer in the high resistance state, the fixed resistance layer (104) being formed between the electrodes (102 and 106) and being electrically connected to at least a part of the variable resistance layer (105).

Abstract: A method of manufacturing a memory cell array in which first conductive layers (2) and second conductive layers (14) extend above a semiconductor substrate (1) and three-dimensionally cross with each other, and memory cells each of which includes a current steering element (10) and a variable resistance element (23) electrically connected in series to each other is provided at a corresponding one of three-dimensional cross points between the first conductive layers (2) and the second conductive layers (14).

Abstract: Provided are a nonvolatile memory element which is capable of effectively preventing an event that when a failure occurs in a certain nonvolatile memory element, data cannot be written to and read from another nonvolatile memory element belonging to the same column or row as that to which the nonvolatile memory element in a failed state belongs, and a semiconductor memory device including the nonvolatile memory element.

Abstract: A semiconductor device and a method of manufacturing the same with easy formation of a phase change film is realized, realizing high integration at the time of using a phase change film as a memory element. Between MISFET of the region which forms one memory cell, and MISFET which adjoined it, each source of MISFET adjoins in the front surface of a semiconductor substrate, insulating. And the multi-layer structure of a phase change film, and the electric conduction film of specific resistance lower than the specific resistance is formed in the plan view of the front surface of a semiconductor substrate ranging over each source of both MISFET, and a plug and a plug stacked on it. The multi-layer structure functions as a wiring extending and existing in parallel on the surface of a semiconductor substrate, and an electric conduction film sends the current of a parallel direction on the surface of a semiconductor substrate.

Abstract: Memory cells, and methods of forming such memory cells, are provided that include a steering element coupled to a carbon-based reversible resistivity switching material that has an increased resistivity, and a switching current that is less than a maximum current capability of the steering element used to control current flow through the carbon-based reversible resistivity switching material. In particular embodiments, methods and apparatus in accordance with this invention form a steering element, such as a diode, having a first width, coupled to a reversible resistivity switching material, such as aC, having a second width smaller than the first width.

Abstract: A semiconductor device includes a first insulating film over a semiconductor substrate. The first insulating film includes a first opening, a first electrode in the first opening, and a second insulating film over the first insulating film. The second insulating film includes a second opening that is positioned over the first electrode. The second opening includes a first conductive film. The first conductive film is electrically coupled to the first electrode. The first conductive film includes a top surface that is lower than a top surface of the second opening. The second opening includes a phase change material film. The phase change material film includes first and second portions. The first portion is surrounded by the first electrode and the first conductive film.

Abstract: The present invention is a phase change device with a heater and a selector (e.g., diode) separated by a phase-change alloy. The present invention will find applicability in electronic memory devices.

Abstract: A phase-change memory device, including a lower electrode, a phase-change material pattern electrically connected to the lower electrode, and an upper electrode electrically connected to the phase-change material pattern. The lower electrode may include a first structure including a metal semiconductor compound, a second structure on the first structure, the second structure including a metal nitride material, and including a lower part having a greater width than an upper part, and a third structure including a metal nitride material containing an element X, the third structure being on the second structure, the element X including at least one selected from the group of silicon, boron, aluminum, oxygen, and carbon.

Abstract: A memory device 10 having an arrangement in which a memory thin film is sandwiched between first and second electrodes, the memory thin film contains at least rare earth elements, the memory thin film 4 or a layer in contact with the memory thin film contains any one of elements selected from Cu, Ag, Zn and the memory thin film or the layer in contact with the memory thin film contains any one of elements selected from Te, S, Se.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate, an upper-layer wire provided on the substrate, a lower-layer wire provided on the substrate, a memory cell located at an intersection of the upper-layer wire and the lower-layer wire and includes a diode and a storage layer, a conductive layer located between the upper-layer wire and the memory cell in a direction perpendicular to the substrate surface, and an interlayer insulating film provided between memory cells. The position of an interface between the upper-layer wire and the interlayer insulating film is lower than a top surface of the conductive layer.

Abstract: A phase change memory device includes a switching device and a storage node connected to the switching device. The storage node includes a bottom stack, a phase change layer disposed on the bottom stack and a top stack disposed on the phase change layer. The phase change layer includes a unit for increasing a path of current flowing through the phase change layer and reducing a volume of a phase change memory region. The area of a surface of the unit disposed opposite to the bottom stack is greater than or equal to the area of a surface of the bottom stack in contact with the phase change layer.

Abstract: A semiconductor memory device includes first lines and second lines and a memory cell array. The first lines and second lines are formed to intersect each other. The memory cell array includes memory cells arranged at intersections of the first lines and the second lines and each formed by connecting a rectification element and a variable-resistance element in series. The rectification element includes a first semiconductor region having an n-type and a second semiconductor region having a p-type. At least a portion of the first semiconductor region is made of a silicon-carbide mixture (Si1-xCx (0<x<1)), and the second semiconductor region is made of silicon (Si).

Abstract: A semiconductor memory device of an embodiment includes: a cathode electrode formed of a p-type semiconductor material; a resistance change film being in contact with the cathode electrode; and an anode electrode being contact with the resistance change film.

Abstract: A memory cell (and method of fabricating the memory cell) includes a stencil layer having a first opening, a phase-change material layer formed on a first electrode layer, and an electrically conductive layer formed on the first electrode layer, the electrically conductive layer having a pillar-shaped portion which is formed on the phase-change material layer and fills the first opening.

Abstract: A semiconductor device includes at least one phase-change pattern disposed on a semiconductor substrate. A planarized capping layer, a planarized protecting layer, and a planarized insulating layer are sequentially stacked to surround sidewalls of the at least one phase-change pattern. An interconnection layer pattern is disposed on the planarized capping layer, the planarized protecting layer, and the planarized insulating layer. The interconnection layer pattern is in contact with the phase-change pattern.

Abstract: A phase change memory device includes a semiconductor substrate having a plurality of phase change cell regions; a lower electrode formed in each of the phase change cell regions on the semiconductor substrate; an insulation layer formed on the semiconductor substrate to cover the lower electrode and defined with a contact hole which exposes the lower electrode; a heater formed in the contact hole; a conductive pattern formed on the insulation layer to be spaced apart from the heater; a phase change layer formed on the heater, the conductive pattern, and portions of the insulation layer between the heater and the conductive pattern; and an upper electrode formed on the phase change layer. This phase change memory device allows the phase change layer to be stably formed and prevents the phase change layer from lifting.

Abstract: A method for manufacturing a memory cell device includes forming a bottom electrode comprising a pipe-shaped member, a top, a bottom and sidewalls having thickness in a dimension orthogonal to the axis of the pipe-shaped member, and having a ring-shaped top surface. A disc shaped member is formed on the bottom of the pipe-shaped member having a thickness in a dimension coaxial with the pipe-shaped member that is not dependent on the thickness of the sidewalls of the pipe-shaped member. A layer of phase change material is deposited in contact with the top surface of the pipe-shaped member. A top electrode in contact with the layer of programmable resistive material. An integrated circuit including an array of such memory cells is described.

Abstract: A microelectronic programmable structure suitable for storing information and array including the structure and methods of forming and programming the structure are disclosed. The programmable structure generally includes an ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered by applying energy to the structure, and thus information may be stored using the structure.

Abstract: A method of fabricating a phase-change memory cell is described. The cross-sectional area of a contact with a phase-change memory element within the cell is controlled by a width and an exposed length of a bottom electrode. The method allows the formation of very small phase-change memory cells.

Abstract: A non-volatile memory device includes a lower electrode, a phase-change material layer formed on the lower electrode so as to be electrically connected to the lower electrode, and an upper electrode formed on the phase-change material layer so as to be electrically connected to the phase-change material layer. The phase-change material layer includes a phase-change material including a composition represented by the formula (I)A(IIXIIYIVZ)(1-A), where I is at least one of As and Se, II is at least one of Ge, Si and Sn, III is at least one of Sb and Bi, and IV is at least one of Te and Se, and where 0.001?A?0.3, 0.001?X?0.3, 0.001?Y?0.8, 0.1?Z?0.8, and X+Y+Z=1.

Abstract: A nonvolatile memory device includes: a substrate; a first electrode formed on the substrate; a resistance change layer formed on the first electrode, the resistance change layer containing conductive nano-material; a second electrode formed on the resistance change layer; and an insulating buffer layer disposed between the first electrode and the resistance change layer, the insulating buffer layer containing conductive material dispersed therein for assuring the electric conductivity between the first electrode and the resistance change layer.

Abstract: A resistive random access memory (RRAM) includes a resistive memory layer of a transition metal oxide, such as Ni oxide, and is doped with a metal material. The RRAM may include at least one first electrode, a resistive memory layer on the at least one first electrode, the resistive memory layer including a Ni oxide layer doped with at least one element selected from a group consisting of Fe, Co, and Sn, and at least one second electrode on the resistive memory layer. The RRAM device may include a plurality of first electrodes and a plurality of second electrodes, and the resistive memory layer may be between the plurality of first electrodes and the plurality of second electrodes.

Abstract: A non-volatile memory device including a phase-change material, which has a low operating voltage and low power consumption, includes a lower electrode; a phase-change material layer formed on the lower electrode so as to be electrically connected to the lower electrode, wherein the phase-change material layer includes a phase-change material having a composition represented by SnXSbYTeZ or, alternatively with substitutions, in whole or in part, of silicon and/or indium for tin, arsenic and/or bismuth for antimony, and selenium for tellurium; and an upper electrode formed on the phase-change material layer so as to be electrically connected to the phase-change material layer. Here, 0.001?X?0.3, 0.001?Y?0.8, 0.1?Z?0.8, and X+Y+Z=1.

Abstract: According to one embodiment, a resistance-change memory includes a laminated structure in which a lower electrode, an insulating film and an upper electrode are stacked, and a resistance-change film provided on a side surface of the laminated structure, and configured to store data in accordance with an electric resistance change.

Abstract: According to one embodiment, a nonvolatile memory device includes a first wire, a second wire and a nonvolatile memory cell. The first wire is formed to extend in a first direction, and the second wire is formed at height different from height of the first wire and to extend in a second direction. The nonvolatile memory cell is arranged to be held between the first wire and the second wire in a poison where the first wire and the second wire cross. The nonvolatile memory cell includes a nonvolatile storage layer and a current limiting resistance layer connected in series to the nonvolatile storage layer and having resistance of 1 kilo-ohm to 1 mega-ohm.

Abstract: This disclosure provides an information recording device for use in a non-volatile information recording/reproduction system having a high recording density, the device including a resistive material having less phase separation or the like during switching. This disclosure also provides an information recording/reproduction system including the device. This disclosure provides an information recording device including: a pair of electrodes; and a recording layer between the electrodes, the recording layer recording information by its resistance change, the recording layer including at least one of (a) M3Oz and (b) AxM3—x0z as a main component, in (a) and (b), z being a value representing oxygen deficiency from z=4.5, and in (b), x satisfying 0.00<x?0.03. This disclosure also provides an information recording/reproduction system including the device.

Abstract: A programmable metallization cell (PMC) that includes an active electrode; a nanoporous layer disposed on the active electrode, the nanoporous layer comprising a plurality of nanopores and a dielectric material; and an inert electrode disposed on the nanoporous layer. Other embodiments include forming the active electrode from silver iodide, copper iodide, silver sulfide, copper sulfide, silver selenide, or copper selenide and applying a positive bias to the active electrode that causes silver or copper to migrate into the nanopores. Methods of formation are also disclosed.

Abstract: Various embodiments are directed to an apparatus comprising a semiconductor memory array with non-volatile memory unit cells arranged into a NAND block. Each of the unit cells comprises a resistive sense element connected in parallel with a switching element. The resistive sense elements are connected in series to form a first serial path, and the switching elements are connected in series to form a second serial path parallel to the first serial path. Each resistive sense element is serially connected to an adjacent resistive sense element in the block by a tortuous conductive path having a portion that extends substantially vertically between said elements to provide operational isolation therefor.

Abstract: An information recording and reproducing apparatus according to an embodiment has a memory cell including a recording layer operative to change in a reversible manner between a first state having a certain resistance value upon application of a voltage pulse and a second state having a resistance value higher than that of the first state. The recording layer includes a first compound layer represented by a composition formula of AxMyX4 (0.1?x?1.2, 2<y?2.9). The A is at least one element selected from a group of Mn (manganese), Fe (iron), Co (cobalt), Ni (nickel), and Cu (copper). The M is at least one element selected from a group of Al (aluminum), Ga (gallium), Ti (titanium), Ge (germanium), and Sn (tin). The X is O (oxygen).

Abstract: Colloidal-processed Si particle devices, device fabrication, and device uses have been presented. The generic device includes a substrate, a first electrode overlying the substrate, a second electrode overlying the substrate, laterally adjacent the first electrode, and separated from the first electrode by a spacing. A colloidal-processed Si particle layer overlies the first electrode, the second electrode, and the spacing between the electrodes. The Si particle layer includes a first plurality of nano-sized Si particles and a second plurality of micro-sized Si particles.

Abstract: According to one embodiment, a resistance-change memory includes a variable resistance element having a laminated structure in which a first electrode, a resistance-change film and a second electrode are laminated, and set to a low-resistance state and a high-resistance state according to stored data, an insulating film provided on a side surface of the variable resistance element, and a fixed resistance element provided on a side surface of the insulating film, and includes a conductive film, the fixed resistance element being connected in parallel with the variable resistance element.

Abstract: A nano-ionic memory device is provided. The memory device includes a substrate, a chemically inactive lower electrode provided on the substrate, a solid electrolyte layer provided on the lower electrode and including a silver (Ag)-doped telluride (Te)-based nano-material, and an oxidizable upper electrode provided on the electrolyte layer.

Abstract: According to one embodiment, a nonvolatile memory device includes a stacked body including a first layer, a second layer and a recording layer. The recording layer is provided between the first layer and the second layer. The recording layer is capable of reversibly changing between a first state and a second state having a resistance higher than a resistance in the first state by a current supplied via the first layer and the second layer. The recording layer includes a first portion and a second portion provided in a plane of a major surface of the recording layer. The second portion has a nitrogen amount higher than a nitrogen amount in the first portion.

Abstract: According to one embodiment, an information recording and reproducing device includes a first layer, a second layer and a recording layer. The recording layer is provided between the first and second layers and is capable of reversibly transitioning between a first state and a second state with a resistance higher than in the first state. One of the first and second layers includes a resistivity distribution layer perpendicular to a stacking direction of the first and second layers, and the recording layer. The resistivity distribution layer includes a low and a high resistivity portion. Resistivity of the high resistivity portion is higher than resistivity of the low resistivity portion. The low resistivity portion contains a transition element identical to a transition element contained in the high resistivity portion.

Abstract: A semiconductor memory device includes a first conductive line, a second conductive line crossing over the first conductive line, a resistance variation part disposed at a position in which the second conductive line intersects with the first conductive line and electrically connected to the first conductive line and the second conductive line and a mechanical switch disposed between the resistance variation part and the second conductive line. The mechanical switch includes a nanotube.

Abstract: Formulations for voltage switchable dielectric materials include two or more different types of semiconductive materials uniformly dispersed within a dielectric matrix material. The semiconductive materials are selected to have different bandgap energies in order to provide the voltage switchable dielectric material with a stepped voltage response. The semiconductive materials can comprise inorganic particles, organic particles, or an organic material that is soluble in, or miscible with, the dielectric matrix material. Formulations optionally can also include electrically conductive materials. At least one of the conductive or semiconductive materials in a formulation can comprise particles characterized by an aspect ratio of at least 3 or greater.

Abstract: According to one embodiment, an information recording and reproducing device includes a first layer, a second layer and a recording layer. The recording layer is provided between the first layer and the second layer and being capable of reversibly changing between a first state having a first resistance and a second state having a second resistance higher than the first resistance by a current supplied via the first layer and the second layer. The recording layer includes a first compound layer and an insulating layer. The first compound layer contains a first compound. The first compound includes a first cation element and a second cation element of a type different from the first cation element. The insulating layer contains a third compound, and the third compound includes an element selected from group 1 to 4 elements and group 12 to 17 elements in the periodic table.

Abstract: To provide a resistance change element which can reduce the current required to switch the state to the high resistance state from the low resistance state. The resistance change element according to the exemplary embodiment includes three or more electrodes, none of the electrodes supplying ion to a resistance change material (205). It includes a material (206) which does not show resistance change arranged between an electrode (207) and the resistance change material (205), and current pathways formed at two electrodes (204) other than the electrode (207).

Abstract: A semiconductor device that includes a phase change material for protecting the device from failure caused by overheating. The semiconductor device is adapted to detect a rapid increase in current due to heat and also adapted to break a circuit in the detected rapid increase in current by depositing a phase change material inside or outside a cell actually operated in the semiconductor device.

Abstract: A phase change memory and method for fabricating the same are provided. The phase change memory element includes: a substrate; rectangle-shaped dielectric patterns formed on the substrate and parallel with each other; electric conductive patterns partially covering a first sidewall and the top surface of the dielectric pattern and the substrate to expose the first sidewall and a second sidewall of the dielectric pattern, wherein the electric conductive patterns covering the same dielectric pattern are apart from each other; a phase change spacer formed on the substrate and directly in contact with the exposed first and second sidewalls of the dielectric patterns, wherein the two adjacent electric conductive patterns covering the same dielectric pattern are electrically connected by the phase change spacer; and a dielectric layer formed on the substrate.

Abstract: A nonvolatile memory element of the present invention comprises a first electrode (103), a second electrode (108); a resistance variable layer (107) which is interposed between the first electrode (103) and the second electrode (107) and is configured to switch a resistance value reversibly in response to an electric signal applied between the electrodes (103) and (108), and the resistance variable layer (107) has at least a multi-layer structure in which a first hafnium-containing layer having a composition expressed as HfOx (0.9?x?1.6), and a second hafnium-containing layer having a composition expressed as HfOy (1.8<y<2.0) are stacked together.

Abstract: A memory cell structure, including a substrate having a via therein bound at first and second ends thereof by electrodes. The via is coated on side surfaces thereof with GST material defining a core that is hollow or at least partially filled with material, e.g., germanium or dielectric material. One or more of such memory cell structures may be integrated in a phase change memory device. The memory cell structure can be fabricated in a substrate containing a via closed at one end thereof with a bottom electrode, by conformally coating GST material on sidewall surface of the via and surface of the bottom electrode enclosing the via, to form an open core volume bounded by the GST material, optionally at least partially filling the open core volume with germanium or dielectric material, annealing the GST material film, and forming a top electrode at an upper portion of the via.

Abstract: A resistive random access memory device formed on a semiconductor substrate comprises an interlayer dielectric having a via formed therethrough. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A barrier metal liner lines walls of the via. A conductive plug is formed in the via. A first barrier metal layer is formed over the chemical-mechanical-polishing stop layer and in electrical contact with the conductive plug. A dielectric layer is formed over the first barrier metal layer. An ion source layer is formed over the dielectric layer. A dielectric barrier layer is formed over the ion source layer, and includes a via formed therethrough communicating with the ion source layer. A second barrier metal layer is formed over the dielectric barrier layer and in electrical contact with the ion source layer. A metal interconnect layer is formed over the barrier metal layer.

Abstract: Methods and systems of using nanotube elements as joule heating elements for memories and other applications. Under one aspect, a method includes providing an electrical stimulus, regulated by a drive circuit, through a nanotube element in order to heat an adjacent article. Further, a detection circuit electrically gauges the state of the article. The article heated by the nanotube element is, in preferred embodiments, a phase changing material, hi memory applications, the invention may be used as a small-scale CRAM capable of employing small amounts of current to induce rapid, large temperature changes in a chalcogenide material. Under various embodiments of the disclosed invention, the nanotube element is composed of a non-woven nanotube fabric which is either suspended from supports and positioned adjacent to the phase change material or is disposed on a substrate and in direct contact with the phase change material.

Abstract: A phase change memory device with a memory element including a basis phase change material, such as a chalcogenide, and one or more additives, where the additive or additives have a non-constant concentration profile along an inter-electrode current path through a memory element. The use of “non-constant” concentration profiles for additives enables doping the different zones with different materials and concentrations, according to the different crystallographic, thermal and electrical conditions, and different phase transition conditions.

Abstract: A metal ion transistor and related methods are disclosed. In one embodiment, the metal ion transistor includes a cell positioned in at least one isolation layer, the cell including a metal ion doped low dielectric constant (low-k) dielectric material sealed from each adjacent isolation layer; a first electrode contacting the cell on a first side; a second electrode contacting the cell on a second side; and a third electrode contacting the cell on a third side, wherein each electrode is isolated from each other electrode.

Abstract: A variable resistance memory device includes a substrate, a plurality of active lines formed on the substrate, are uniformly separated, and extend in a first direction, a plurality of switching devices formed on the active lines and are separated from one another, a plurality of variable resistance devices respectively formed on and connected to the switching devices, a plurality of local bit lines formed on the variable resistance devices, are uniformly separated, extend in a second direction, and are connected to the variable resistance devices, a plurality of local word lines formed on the local bit lines, are uniformly separated, and extend in the first direction, a plurality of global bit lines formed on the local word lines, are uniformly separated, and extend in the second direction, and a plurality of global word lines formed on the global bit lines, are uniformly separated, and extend in the first direction.

Abstract: A resistance change memory includes a first conductive line extending in a first direction, a second conductive line extending in a second direction which is crossed to the first direction, a cell unit including a memory element and a rectification connected in series between the first and second conductive lines, and a control circuit which is connected to both of the first and second conductive lines. The control circuit controls a value of voltage which is applied to the memory element to change a resistance of the memory element reversibly between first and second values. The rectification includes a p-type semiconductor layer, an n-type semiconductor layer and an intrinsic semiconductor layer therebetween. The rectification has a first diffusion prevention area in the intrinsic semiconductor layer.