Switching Materials Being Oxides Or Nitrides (epo) Patents (Class 257/E45.003)
  • Patent number: 9040950
    Abstract: According to one embodiment, a nonvolatile memory device includes a first interconnect, an insulating layer, a needle-like metal oxide, and a second interconnect. The insulating layer is provided on the first interconnect. The needle-like metal oxide pierces the insulating layer in a vertical direction. The second interconnect is provided on the insulating layer.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: May 26, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kouji Matsuo
  • Patent number: 9029829
    Abstract: A memory cell includes a first resistive switching device having a first terminal and a second terminal, a switching device having a first terminal and a second terminal, and an access device having a first access terminal and a second access terminal. The first access terminal is coupled to the first terminal of the first resistive switching device and the first terminal of the switching device.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: May 12, 2015
    Assignee: Adesto Technologies Corporation
    Inventors: Juan Pablo Saenz Echeverry, Deepak Kamalanathan
  • Patent number: 9024285
    Abstract: A nanoscale switching device is provided. The device comprises: a first electrode of a nanoscale width; a second electrode of a nanoscale width; an active region disposed between the first and second electrodes, the active region having a non-conducting portion comprising an electronically semiconducting or nominally insulating and a weak ionic conductor switching material capable of carrying a species of dopants and transporting the dopants under an electric field and a source portion that acts as a source or sink for the dopants; and an oxide layer either formed on the first electrode, between the first electrode and the active region or formed on the second electrode, between the second electrode and the active region. A crossbar array comprising a plurality of the nanoscale switching devices is also provided. A process for making at least one nanoscale switching device is further provided.
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: May 5, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jianhua Yang, Gilberto Ribeiro, R. Stanley Williams
  • Patent number: 9024287
    Abstract: According to one embodiment, a memory device includes a first electrode, a second electrode and an insulating portion. The first electrode includes an ionizable metal. The second electrode includes a conductive material. The conductive material is more difficult to ionize than the metal. The insulating portion is provided between the first electrode and the second electrode. The insulating portion is made of an insulating material. A space is adjacent to a side surface of the insulating portion between the first electrode and the second electrode.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: May 5, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takayuki Ishikawa, Hiroki Tanaka, Shosuke Fujii
  • Patent number: 9018611
    Abstract: A semiconductor storage device according to an embodiment includes a first conductive layer, a variable resistance layer, an electrode layer, a first liner layer, a stopper layer, and a second conductive layer. The variable resistance layer is provided above the first conductive layer. The electrode layer contacts an upper surface of the variable resistance layer. The first liner layer contacts the upper surface of the electrode layer. The stopper layer contacts the upper surface of the first liner layer. The second conductive layer is provided above the stopper layer. The first liner layer is made of a material having a property for canceling an influence of an orientation of a lower layer of the first liner layer, the property of the first liner layer being superior compared with that of the stopper layer.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: April 28, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Murato Kawai
  • Patent number: 9012881
    Abstract: Resistive-switching memory elements having improved switching characteristics are described, including a memory element having a first electrode and a second electrode, a switching layer between the first electrode and the second electrode comprising hafnium oxide and having a first thickness, and a coupling layer between the switching layer and the second electrode, the coupling layer comprising a material including metal titanium and having a second thickness that is less than 25 percent of the first thickness.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: April 21, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Ronald J. Kuse, Tony P. Chiang, Imran Hashim
  • Patent number: 9000410
    Abstract: According to one embodiment, a nonvolatile memory device includes a first conductive unit, a second conductive unit, and a memory layer. The memory layer is provided between the first conductive unit and the second conductive unit. The memory layer is capable of reversibly transitioning between a first state with a low resistance and a second state with a higher resistance than the first state due to a current supplied via the first conductive unit and the second conductive unit. The memory layer has a chalcopyrite structure.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: April 7, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Koichi Kubo
  • Patent number: 9000411
    Abstract: Various embodiments of the present invention are direct to nanoscale, reconfigurable, two-terminal memristor devices. In one aspect, a device (400) includes an active region (402) for controlling the flow of charge carriers between a first electrode (104) and a second electrode (106). The active region is disposed between the first electrode and the second electrode and includes a storage material. Excess mobile oxygen ions formed within the active region are stored in the storage material by applying a first voltage.
    Type: Grant
    Filed: January 6, 2009
    Date of Patent: April 7, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Zhiyong Li, Alexandre M. Bratkovski, Jianhua Yang
  • Patent number: 8987693
    Abstract: A method of operating a memory device having a dielectric material layer, a transition metal oxide layer and a set of electrodes each formed over a substrate, includes applying a voltage across the set of electrodes producing an electric field across the transition metal oxide layer enabling the transition metal oxide layer to undergo a metal-insulation transition (MIT) to perform a read or write operation on memory device.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: March 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Tymon Barwicz, Keith A. Jenkins, Supratik Guha
  • Patent number: 8981333
    Abstract: Provided is a nonvolatile semiconductor memory device including a variable resistance element in which a parasitic resistance between the lower electrode and the variable resistance layer included in the variable resistance element is reduced. The nonvolatile semiconductor memory device includes: a substrate; and a variable resistance elementformed on the substrate, wherein the variable resistance elementincludes a lower electrode layer formed on the substrate, a variable resistance layer formed on the lower electrode layer, and an upper electrode layer formed on the variable resistance layer, the lower electrode layer includes at least a first conductive layer and a second conductive layer which is formed on the first conductive layer and is in contact with the variable resistance layer, and the first conductive layer includes an oxidatively degraded layer which is formed on an upper surface of the first conductive layer due to oxidization of the first conductive layer.
    Type: Grant
    Filed: October 10, 2012
    Date of Patent: March 17, 2015
    Assignee: Panasonic Intellectual Property Management, Co., Ltd.
    Inventors: Satoru Fujii, Satoru Ito, Takumi Mikawa
  • Patent number: 8982601
    Abstract: A switchable junction (600) having an intrinsic diode (634) formed with a voltage dependent resistor (640) is disclosed. The switchable junction comprises a first electrode (618), a second electrode (622), and a memristive matrix (620) configured to form an electrical interface (626) with the first electrode (618). The electrical interface has a programmable conductance. The voltage dependent resistor (640) is in electrical contact with the memristive matrix (620). The voltage dependent resistor is configured to form a rectifying diode interface (628) with the second electrode (622).
    Type: Grant
    Filed: September 4, 2009
    Date of Patent: March 17, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jianhua Yang, John Paul Strachan, Julien Borghetti, Matthew D. Pickett
  • Patent number: 8976565
    Abstract: MIMCAP diodes are provided that can be suitable for memory device applications, such as current selector devices for cross point memory array. The MIMCAP diodes can have lower thermal budget as compared to Schottky diodes and controllable lower barrier height and lower series resistance as compared to MIMCAP tunneling diodes. The MIMCAP diode can include a barrier height modification layer, a low leakage dielectric layer and a high leakage dielectric layer. The layers can be sandwiched between two electrodes.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: March 10, 2015
    Assignee: Intermolecular, Inc.
    Inventor: Prashant B Phatak
  • Patent number: 8969843
    Abstract: According to one embodiment, a memory device includes first and second conductive layers, a variable resistance portion, and a multiple tunnel junction portion. The variable resistance portion is provided between the first and second conductive layers. The multiple tunnel junction portion is provided between the first conductive layer and the variable resistance portion, and includes first, second, and third tunnel insulating films, and first and second nanocrystal layers. The first nanocrystal layer between the first and second tunnel insulating films includes first conductive minute particles. The second nanocrystal layer between the second and third tunnel insulating films includes second conductive minute particles.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: March 3, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Ryuji Ohba
  • Patent number: 8962387
    Abstract: Some embodiments include methods of forming memory cells in which a metal oxide material is formed over a first electrode material, an oxygen-sink material is formed over and directly against the metal oxide material, and a second electrode material is formed over the oxygen-sink material. The second electrode material is of a different composition than the oxygen-sink material. The metal oxide material is treated to transfer oxygen from a region of the metal oxide material to the oxygen-sink material and thereby subdivide the metal oxide material into at least two regions, with one of the regions nearest the oxygen-sink material being relatively oxygen depleted relative to another of the regions.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: February 24, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Bhaskar Srinivasan
  • Patent number: 8963117
    Abstract: This disclosure provides a nonvolatile memory device and related methods of manufacture and operation. The device may include one or more resistive random access memory (ReRAM) approaches to provide a memory device with more predictable operation. In particular, the forming voltage required by particular designs may be reduced through the use of a barrier layer, a reverse polarity forming voltage pulse, a forming voltage pulse where electrons are injected from a lower work function electrode, or an anneal in a reducing environment. One or more of these techniques may be applied, depending on the desired application and results.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: February 24, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Pragati Kumar, Tony P. Chiang, Prashant B Phatak, Yun Wang
  • Patent number: 8957399
    Abstract: A variable resistance nonvolatile memory element includes a first electrode, a second electrode, and a variable resistance layer including: a first oxide layer including a metal oxide having non-stoichiometric composition and including p-type carriers; a second oxide layer located between and in contact with the first oxide layer and a second electrode and including a metal oxide having non-stoichiometric composition and including n-type carriers; an oxygen reservoir region located in the first oxide layer, having no contact with the first electrode, and having an oxygen content atomic percentage higher than that of the first oxide layer; and a local region located in the second oxide layer, having contact with the oxygen reservoir region, and having an oxygen content atomic percentage lower than that of the second oxide layer.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: February 17, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Zhiqiang Wei, Takeshi Takagi, Koji Katayama
  • Patent number: 8941089
    Abstract: In accordance with an embodiment of the present invention, a resistive switching device includes an opening disposed within a first dielectric layer, a conductive barrier layer disposed on sidewalls of the opening, a fill material including an inert material filling the opening. A solid electrolyte layer is disposed over the opening. The solid electrolyte contacts the fill material but not the conductive barrier layer. A top electrode is disposed over the solid electrolyte.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: January 27, 2015
    Assignee: Adesto Technologies Corporation
    Inventors: Chakravarthy Gopalan, Jeffrey Shields, Venkatesh Gopinath, Janet Siao-Yian Wang, Kuei-Chang Tsai
  • Patent number: 8941088
    Abstract: A nonvolatile memory device includes: a first conductive layer; a second conductive layer; a first resistance change layer provided between the first conductive layer and the second conductive layer and having an electrical resistance changing with at least one of an applied electric field and a passed current; and a first lateral layer provided on a lateral surface of the first resistance change layer and having an oxygen concentration higher than an oxygen concentration in the first resistance change layer.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: January 27, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kensuke Takano, Yoshio Ozawa, Katsuyuki Sekine, Junichi Wada
  • Patent number: 8937292
    Abstract: An ultra-high-density vertical cross-point array comprises a plurality of horizontal line layers having horizontal lines interleaved with a plurality of vertical lines arranged in rows and columns. The vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each consecutive pair of horizontal lines in each horizontal line layer. Each vertical line comprises a center conductor surrounded by a single or multi-layered memory film. Accordingly, when interleaved with the horizontal lines, two-terminal memory cells are integrally formed between the center conductor of each vertical line and each crossing horizontal line. By configuring the vertical and horizontal lines so that a row of vertical lines is positioned between each consecutive pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.
    Type: Grant
    Filed: August 15, 2011
    Date of Patent: January 20, 2015
    Assignee: Unity Semiconductor Corporation
    Inventor: Bruce Bateman
  • Patent number: 8927956
    Abstract: A resistance type memory device is provided. The resistance type memory device includes a first and a second conductors and a metal oxide layer. The metal oxide layer is disposed between the first and the second conductors, and the resistance type memory device is defined in a first resistivity. The resistance type memory device is defined in a second resistivity after a first pulse voltage is applied to the metal oxide layer. The resistance type memory device is defined in a third resistivity after a second pulse voltage is applied to the metal oxide layer. The second resistivity is greater than the first resistivity, and the first resistivity is greater than the third resistivity.
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: January 6, 2015
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Ming-Daou Lee, Chia-Hua Ho, Erh-Kun Lai, Kuang-Yeu Hsieh
  • Patent number: 8921821
    Abstract: Some embodiments include a method of forming a memory cell. A first portion of a switching region is formed over a first electrode. A second portion of the switching region is formed over the first portion using atomic layer deposition. The second portion is a different composition than the first portion. An ion source region is formed over the switching region. A second electrode is formed over the ion source region. Some embodiments include a memory cell having a switching region between a pair of electrodes. The switching region is configured to be reversibly transitioned between a low resistive state and a high resistive state. The switching region includes two or more discrete portions, with one of the portions not having a non-oxygen component in common with any composition directly against it in the high resistive state.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: December 30, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Shuichiro Yasuda, Noel Rocklein, Scott E. Sills, D. V. Nirmal Ramaswamy, Qian Tao
  • Patent number: 8912520
    Abstract: A nanoscale switching device has an active region disposed between two electrodes of nanoscale widths. The active region contains a switching material that carries mobile ionic dopants capable of being transported over the active region under an electric field to change a resistive state of the device. The switching material further carries immobile ionic dopants for inhibiting clustering of the mobile ionic dopants caused by switching cycles of the device. The immobile ionic dopants have a charge opposite in polarity to the charge of the mobile ionic dopants, and are less mobile under the electric field than the mobile ion dopants.
    Type: Grant
    Filed: July 21, 2010
    Date of Patent: December 16, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jianhua Yang, Matthew Pickett, Gilberto Ribeiro
  • Patent number: 8912524
    Abstract: Embodiments of the present invention generally relate to a resistive switching nonvolatile memory element that is formed in a resistive switching memory device that may be used in a memory array to store digital data. The memory element is generally constructed as a metal-insulator-metal stack. The resistive switching portion of the memory element includes a getter and/or a defect portion. In general, the getter portion is an area of the memory element that is used to help form, during the resistive switching memory device's fabrication process, a region of the resistive switching layer that has a greater number of vacancies or defects compared to the remainder of resistive switching layer. The defect portion is an area of the memory element that has a greater number of vacancies or defects compared to the remainder of the resistive switching layer, and is formed during the resistive switching memory device's fabrication process.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: December 16, 2014
    Assignees: SanDisk 3D LLC, Kabushiki Kaisha Toshiba
    Inventors: Yun Wang, Tony Chiang, Imran Hashim
  • Patent number: 8895951
    Abstract: This disclosure provides a method of fabricating a semiconductor device layer and an associated memory cell. Empirical data may be used to generate a hysteresis curve associated with deposition for a metal-insulator-metal structure, with curve measurements reflecting variance of an electrical property as a function of cathode voltage used during a sputtering process. By generating at least one voltage level to be used during the sputtering process, where the voltage reflects a suitable value for the electrical property from among the values obtainable in mixed-mode deposition, a semiconductor device layer may be produced with improved characteristics and durability. A multistable memory cell or array of such cells manufactured according to this process can, for a set of given materials, be fabricated to have minimal leakage or “off” current characteristics (Ileak or Ioff, respectively) or a maximum ratio of “on” current to “off” current (Ion/Ioff).
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: November 25, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Wayne R French, Tony P. Chiang, Pragati Kumar, Prashant B Phatak
  • Patent number: 8891284
    Abstract: A memristor based on mixed-metal-valence compounds comprises: a first electrode; a second electrode; a layer of a mixed-metal-valence phase in physical contact with at least one layer of a fully oxidized phase. The mixed-metal-valence phase is essentially a condensed phase of dopants for the fully oxidized phase that drift into and out of the fully oxidized phase in response to an applied electric field. One of the first and second electrodes is in electrical contact with either the layer of the mixed-metal-valence phase or a layer of a fully oxidized phase and the other is in electrical contact with the layer (or other layer) of the fully oxidized phase. The memristor is prepared by forming in either order the layer of the mixed-metal-valence phase and the layer of the fully oxidized phase, one on the other. A reversible diode and an ON-switched diode are also provided. A method of operating the memristor is further provided.
    Type: Grant
    Filed: September 4, 2009
    Date of Patent: November 18, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: R. Stanley Williams, Jianhua Yang, Matthew Pickett, Gilberto Ribeiro, John Paul Strachan
  • Patent number: 8884262
    Abstract: A non-volatile memory device is provided wherein a lower molding layer is formed on a substrate; a first horizontal interconnection is formed on the lower molding layer; an upper molding layer is formed on the first horizontal interconnection; a pillar is formed connected to the substrate by vertically passing through the upper molding layer, the first horizontal interconnection and the lower molding layer. The pillar has a lower part and an upper part, wherein the lower part is disposed on the same level as the first horizontal interconnection and has a first width and the upper part is disposed on a higher level than the first horizontal interconnection and has a second width different from the first width.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: November 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Su Ju, Sun-Jung Kim, Soo-Doo Chae
  • Patent number: 8866122
    Abstract: In one embodiment, a resistive switching device includes a bottom electrode, a switching layer, a buffer layer, and a top electrode. The switching layer is disposed over the bottom electrode. The buffer layer is disposed over the switching layer and provides a buffer of ions of a memory metal. The buffer layer includes an alloy of the memory metal with an alloying element, which includes antimony, tin, bismuth, aluminum, germanium, silicon, or arsenic. The top electrode is disposed over the buffer layer and provides a source of the memory metal.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: October 21, 2014
    Assignee: Adesto Technologies Corporation
    Inventors: Wei Ti Lee, Chakravarthy Gopalan, Yi Ma, Kuei-Chang Tsai, Jeffrey Shields, Janet Wang
  • Patent number: 8860001
    Abstract: A resistive random access memory (ReRAM) includes a first metal layer having a first metal and a metal-oxide layer on the first metal layer. The metal-oxide layer inlcudes the first metal. The ReRAM further includes a second metal layer over the metal-oxide layer and a first continuous conductive barrier layer in physical contact with sidewalls of the first metal layer and of the metal-oxide layer.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: October 14, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Cheong Min Hong, Ko-Min Chang, Feng Zhou
  • Patent number: 8846484
    Abstract: Systems and methods for preparing resistive switching memory devices such as resistive random access memory (ReRAM) devices wherein both oxide and nitride layers are deposited in a single chamber are provided. Various oxide and nitride based layers in the ReRAM device such as the switching layer, current-limiting layer, and the top electrode (and optionally the bottom electrode) are deposited in the single chamber. By fabricating the ReRAM device in a single chamber, throughput is increased and cost is decreased. Moreover, processing in a single chamber reduces device exposure to air and to particulates, thereby minimizing device defects.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: September 30, 2014
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Albert Sanghyup Lee, Chien-Lan Hsueh, Tim Minvielle, Takeshi Yamaguchi
  • Patent number: 8847194
    Abstract: A memory component having a first electrode; a second electrode; and a memory layer between the first and second electrodes. The memory layer includes (a) on a first electrode side thereof, a high resistance layer that is composed of a plurality of layers, at least one of the plurality of layers including tellurium (Te) as the chief component among anion components, and (b) on a second electrode side thereof, an ion source layer with at least one kind of metal element and at least one kind of chalcogen element selected from the group consisting of tellurium (Te), sulfur (S) and selenium (Se). The memory component is configured to change a resistance of the high resistance layer in accordance with a voltage or current pulse stress applied between the first and second electrodes.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: September 30, 2014
    Assignee: Sony Corporation
    Inventors: Shuichiro Yasuda, Katsuhisa Aratani, Kazuhiro Ohba, Hiroaki Sei
  • Patent number: 8841645
    Abstract: Some embodiments include a memory device and methods of forming the same. The memory device can include an electrode coupled to a memory element. The electrode can include different materials located at different portions of the electrode. The materials can create different dielectrics contacting the memory elements at different locations. Various states of the materials in the memory device can be used to represent stored information. Other embodiments are described.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: September 23, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Durai Vishak Nirmal Ramaswamy, Kirk D. Prall
  • Patent number: 8835272
    Abstract: A resistive switching device and methods for making the same are disclosed. In the above said device, a resistive switching layer is interposed between opposing electrodes. The resistive switching layer comprises at least two sub-layers of switchable insulative material characterized by different ionic mobilities.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: September 16, 2014
    Assignee: Sandia Corporation
    Inventors: Patrick R. Mickel, Conrad D. James
  • Patent number: 8829484
    Abstract: Some embodiments include methods of forming memory structures. An electrically insulative line is formed over a base. Electrode material is deposited over the line and patterned to form a pair of bottom electrodes along the sidewalls of the line. Programmable material is formed over the bottom electrodes, and a top electrode is formed over the programmable material. The bottom electrodes may each contain at least one segment which extends at angle of from greater than 0° to less than or equal to about 90° relative to a planar topography of the base. Some embodiments include memory structures having a bottom electrode extending upwardly from a conductive contact to a programmable material, with the bottom electrode having a thickness of less than or equal to about 10 nanometers. Some embodiments include memory arrays and methods of forming memory arrays.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: September 9, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Scott E. Sills
  • Patent number: 8822969
    Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a variable resistive pattern, a lower electrode structure, a heating electrode. The heating electrode includes first, second and plate portions. The first portion is extended in a first direction. The second portion is upwardly protruded from a central region of a top surface of the first portion and is in contact with the variable resistive pattern. The plate portion is extended from a lower end of the first portion in a second direction perpendicular to the first direction. The plate portion is in contact with the lower electrode structure.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: September 2, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Youngnam Hwang
  • Patent number: 8816317
    Abstract: Non-volatile resistive-switching memories formed using anodization are described. A method for forming a resistive-switching memory element using anodization includes forming a metal containing layer, anodizing the metal containing layer at least partially to form a resistive switching metal oxide, and forming a first electrode over the resistive switching metal oxide. In some examples, an unanodized portion of the metal containing layer may be a second electrode of the memory element.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: August 26, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Alexander Gorer, Tony P. Chiang, Igor Ivanov, Prashant B. Phatak
  • Patent number: 8811063
    Abstract: Some embodiments include methods of programming a memory cell. A plurality of charge carriers may be moved within the memory cell, with an average charge across the moving charge carriers having an absolute value greater than 2. Some embodiments include methods of forming and programming an ionic-transport-based memory cell. A stack is formed to have programmable material between first and second electrodes. The programmable material has mobile ions which are moved within the programmable material to transform the programmable material from one memory state to another. An average charge across the moving mobile ions has an absolute value greater than 2. Some embodiments include memory cells with programmable material between first and second electrodes. The programmable material includes an aluminum nitride first layer, and includes a second layer containing a mobile ion species in common with the first layer.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: August 19, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Roy E. Meade, Bhaskar Srinivasan, Gurtej S. Sandhu
  • Patent number: 8796659
    Abstract: A variable resistance element includes a first electrode, a second electrode and an ion conduction layer interposed between the first and second electrodes. The ion conduction layer contains an organic oxide containing at least oxygen and carbon. The carbon concentration distribution in the ion conduction layer is such that the carbon concentration in an area closer to the first electrode is greater than that in an area closer to the second electrode.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: August 5, 2014
    Assignee: NEC Corporation
    Inventors: Munehiro Tada, Koichiro Okamoto, Toshitsugu Sakamoto, Hiromitsu Hada
  • Patent number: 8796103
    Abstract: Provided are methods of forming nonvolatile memory elements including resistance switching layers. A method involves diffusing oxygen from a precursor layer to one or more reactive electrodes by annealing. At least one electrode in a memory element is reactive, while another may be inert. The precursor layer is converted into a resistance switching layer as a result of this diffusion. The precursor layer may initially include a stoichiometric oxide that generally does not exhibit resistance switching characteristics until oxygen vacancies are created. Metals forming such oxides may be more electronegative than metals forming a reactive electrode. The reactive electrode may have substantially no oxygen at least prior to annealing. Annealing may be performed at 250-400° C. in the presence of hydrogen. These methods simplify process control and may be used to form nonvolatile memory elements including resistance switching layers less than 20 Angstroms thick.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: August 5, 2014
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Mihir Tendulkar, Tim Minvielle, Yun Wang, Takeshi Yamaguchi
  • Patent number: 8796662
    Abstract: A semiconductor device includes a first horizontal molding pattern, a horizontal electrode pattern disposed on the first horizontal molding pattern, and a second horizontal molding pattern disposed on the horizontal electrode pattern. A vertical structure extends through the horizontal patterns. The vertical structure includes a vertical electrode pattern, a data storage pattern interposed between the vertical electrode pattern and the horizontal patterns, a first buffer pattern interposed between the data storage pattern and the first molding pattern, and a second buffer pattern interposed between the data storage pattern and the second molding pattern and spaced apart from the first buffer pattern.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: August 5, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seong-Ho Song, Chan-Jin Park, In-Gyu Baek
  • Patent number: 8796819
    Abstract: A non-volatile memory device including a variable resistance material is provided. The non-volatile memory device may include a buffer layer, a variable resistance material layer and/or an upper electrode, for example, sequentially formed on a lower electrode. A schottky barrier may be formed on an interface between the buffer layer and the lower electrode. The variable resistance material layer may be formed with a variable resistance property.
    Type: Grant
    Filed: July 6, 2007
    Date of Patent: August 5, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-hong Lee, Choong-rae Cho, Stefanovich Genrikh
  • Patent number: 8791445
    Abstract: A nonvolatile resistive memory element includes a host oxide formed from an interfacial oxide layer. The interfacial oxide layer is formed on the surface of a deposited electrode layer via in situ or post-deposition surface oxidation treatments.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: July 29, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Randall Higuchi, Tony P. Chiang, Ryan Clarke, Vidyut Gopal, Imran Hashim, Robert Huertas, Yun Wang
  • Patent number: 8791444
    Abstract: Resistive random access memory (RRAM) using stacked dielectrics and a method for manufacturing the same are disclosed, where a setting power of only 4 ?W, an ultra-low reset power of 2 nW, good switching uniformity and excellent cycling endurance up to 5×109 cycles were achieved simultaneously. Such record high performances were reached in a Ni/GeOx/nano-crystal-TiO2/TaON/TaN RRAM device, where the excellent endurance is 4˜6 orders of magnitude larger than existing Flash memory. The very long endurance and low switching energy RRAM is not only satisfactory for portable SSD in a computer, but may also create new applications such as being used for a Data Center to replace high power consumption hard discs.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: July 29, 2014
    Assignee: National Chiao Tung University
    Inventors: Albert Chin, Chun-Hu Cheng
  • Patent number: 8785901
    Abstract: Methods of fabricating semiconductor devices are provided including forming a dielectric interlayer on a substrate, the dielectric interlayer defining an opening therein. A metal pattern is formed in the opening. An oxidization process is performed on the metal pattern to form a conductive metal oxide pattern, and the conductive metal oxide pattern is planarized. Related semiconductor devices are also provided.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: July 22, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Junho Jeong, Sukhun Choi, Jangeun Lee, Kyunghyun Kim, Sechung Oh, Kyungtae Nam
  • Patent number: 8772750
    Abstract: A non-volatile memory element includes: a memory layer disposed between a first electrode and a second electrode; and a buffer layer disposed between the memory layer and the first electrode. The memory layer includes a first material layer and a second material layer. The first material layer and the second material layer are configured to exchange ionic species to change a resistance state of the memory layer.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: July 8, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-bum Lee, Chang-jung Kim, Young-bae Kim, Myoung-jae Lee, Ji-hyun Hur, Dong-soo Lee, Man Chang, Seung-ryul Lee
  • Patent number: 8772749
    Abstract: In a first aspect, a metal-insulator-metal (MIM) stack is provided that includes (1) a first conductive layer comprising a silicon-germanium (SiGe) alloy; (2) a resistivity-switching layer comprising a metal oxide layer formed above the first conductive layer; and (3) a second conductive layer formed above the resistivity-switching layer. A memory cell may be formed from the MIM stack. Numerous other aspects are provided.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: July 8, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Deepak Chandra Sekar, Franz Kreupl, Raghuveer S. Makala
  • Patent number: 8766224
    Abstract: An electrically actuated switch comprises a first electrode, a second electrode, and an active region disposed therebetween. The active region comprises at least one primary active region comprising at least one material that can be doped or undoped to change its electrical conductivity, and a secondary active region comprising at least one material for providing a source/sink of ionic species that act as dopants for the primary active region(s). Methods of operating the switch are also provided.
    Type: Grant
    Filed: October 3, 2006
    Date of Patent: July 1, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: R. Stanley Williams
  • Patent number: 8766234
    Abstract: Selector devices that can be suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. In some embodiments, the selector device can include a first electrode, a tri-layer dielectric layer, and a second electrode. The tri-layer dielectric layer can include a high leakage dielectric layer sandwiched between two lower leakage dielectric layers. The low leakage layers can function to restrict the current flow across the selector device at low voltages. The high leakage dielectric layer can function to enhance the current flow across the selector device at high voltages.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: July 1, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Imran Hashim, Venkat Ananthan, Tony P. Chiang, Prashant B. Phatak
  • Patent number: 8767441
    Abstract: Method for a memory including a first, second, third and fourth cells include applying a read, program, or erase voltage, the first and second cells coupled to a first top interconnect, the third and fourth cells coupled to a second top interconnect, the first and third cells coupled to a first bottom interconnect, the second and fourth cells are to a second bottom interconnect, each cell includes a switching material overlying a non-linear element (NLE), the resistive switching material is associated with a first conductive threshold voltage, the NLE is associated with a lower, second conductive threshold voltage, comprising applying the read voltage between the first top and the first bottom electrode to switch the NLE of the first cell to conductive, while the NLEs of the second, third, and the fourth cells remain non-conductive, and detecting a read current across the first cell in response to the read voltage.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: July 1, 2014
    Assignee: Crossbar, Inc.
    Inventors: Wei Lu, Sung Hyun Jo, Hagop Nazarian
  • Patent number: 8742387
    Abstract: An integrated circuit includes a memory cell with a resistance changing memory element. The resistance changing memory element includes a first electrode, a second electrode, and a resistivity changing material disposed between the first and second electrodes, where the resistivity changing material is configured to change resistive states in response to application of a voltage or current to the first and second electrodes. In addition, at least one of the first electrode and the second electrode comprises an insulator material including a self-assembled electrically conductive element formed within the insulator material. The self-assembled electrically conductive element formed within the insulator material remains stable throughout the operation of switching the resistivity changing material to different resistive states.
    Type: Grant
    Filed: June 25, 2008
    Date of Patent: June 3, 2014
    Assignee: Qimonda AG
    Inventors: Thomas Happ, Franz Kreupl, Jan Boris Philipp, Petra Majewski
  • Patent number: 8729558
    Abstract: According to one embodiment, a nitride semiconductor device includes a semiconductor layer, a source electrode, a drain electrode, a first and a second gate electrode. The semiconductor layer includes a nitride semiconductor. The source electrode provided on a major surface of the layer forms ohmic contact with the layer. The drain electrode provided on the major surface forms ohmic contact with the layer and is separated from the source electrode. The first gate electrode is provided on the major surface between the source and drain electrodes. The second gate electrode is provided on the major surface between the source and first gate electrodes. When a potential difference between the source and first gate electrodes is 0 volts, a portion of the layer under the first gate electrode is conductive. The first gate electrode is configured to switch a constant current according to a voltage applied to the second gate electrode.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: May 20, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masahiko Kuraguchi