Solid-state Devices With At Least One Potential-jump Barrier Or Surface Barrier Using Active Layer Of Lower Electrical Conductivity Than Material Adjacent Thereto And Through Which Carrier Tunneling Occurs, Processes Or Apparatus Peculiar To Manufacture Or Treatment Of Such Devices, Or Of Parts Thereof (epo) Patents (Class 257/E49.001)
  • Patent number: 7420203
    Abstract: By introducing new concepts into a structure of a conventional organic semiconductor element and without using a conventional ultra thin film, an organic semiconductor element is provided which is more reliable and has higher yield. Further, efficiency is improved particularly in a photoelectronic device using an organic semiconductor. Between an anode and a cathode, there is provided an organic structure including alternately laminated organic thin film layer (functional organic thin film layer) realizing various functions by making an SCLC flow, and a conductive thin film layer (ohmic conductive thin film layer) imbued with a dark conductivity by doping it with an acceptor and a donor, or by the like method.
    Type: Grant
    Filed: February 18, 2005
    Date of Patent: September 2, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuo Tsutsui, Hiroko Yamazaki, Satoshi Seo
  • Publication number: 20080203589
    Abstract: A method of designing features on a semiconductor wafer. A design of active or functional features is provided for chiplets separated by kerf areas on the wafer. The method then includes determining pattern density of the chiplet features, and applying a pattern of spaced dummy features on chiplet area not covered by active or functional features, as well as in the kerf areas. The dummy features are uniformly expanded or reduced in size until a desired dummy feature pattern density is reached.
    Type: Application
    Filed: February 23, 2007
    Publication date: August 28, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Todd C. Bailey, Ryan P. Deschner, Wai-Kin Li, Roger A. Quon
  • Patent number: 7402833
    Abstract: A multilayer dielectric tunnel barrier structure and a method for its formation which may be used in non-volatile magnetic memory elements comprises an ALD deposited first nitride junction layer formed from one or more nitride monolayers i.e., AlN, an ALD deposited intermediate oxide junction layer formed from one or more oxide monolayers i.e., AlxOy, disposed on the first nitride junction layer, and an ALD deposited second nitride junction layer formed from one or more nitride monolayers i.e., AlN, disposed on top of the intermediate oxide junction layer. The multilayer tunnel barrier structure is formed by using atomic layer deposition techniques to provide improved tunneling characteristics while also providing anatomically smooth barrier interfaces.
    Type: Grant
    Filed: April 15, 2005
    Date of Patent: July 22, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Joel A. Drewes
  • Publication number: 20080083962
    Abstract: Method of fabricating 3-dimensional force input control device are disclosed.
    Type: Application
    Filed: May 15, 2007
    Publication date: April 10, 2008
    Inventor: Vladimir Vaganov
  • Patent number: 7282731
    Abstract: A quantum supermemory is based on the cells of nanostructured material. The nanostructured material includes consists of clusters with tunnel-transparent coatings. The clusters have sizes at which resonant electron features are manifested. The size is determined by the circular radius of the electronic wave, according to the formula r0=/(me?2c)=7.2517 nm, where is the Plank contstant, me is the electron mass, ?=1/137,036 is the fine structure constant, c is the speed of light. The cluster size is set within the range r0=4r0, and the width of the tunnel-transparent gap is less than r0=7.2517 nm. The nanostructured material stores energy (charge) uniformly along its whole volume with the specific density of 1.66*103 J/cm3. Based on this material energy-independent rewritable memory is obtained with the writing density up to 28 Gbyte/cm2, the maximum working temperature being 878° C. and the maximum timing frequency being 175 Ghz.
    Type: Grant
    Filed: July 1, 2002
    Date of Patent: October 16, 2007
    Inventor: Alexandr Mikhailovich Ilyanok
  • Patent number: 7115898
    Abstract: A pair of electrodes are provided to sandwich an organic semiconductor layer. A lead-out electrode is provided to each of the organic semiconductor layer and the two electrodes constituting the pair of electrodes. Consequently, there is provided an organic semiconductor device having a simple configuration.
    Type: Grant
    Filed: April 24, 2003
    Date of Patent: October 3, 2006
    Assignee: Canon Kabushiki Kaisha
    Inventor: Tadahiko Hirai