Abstract: A stress liner for use within a semiconductor structure that includes a field effect device has a dielectric constant less than about 7 and a compressive stress greater than about 5 GPa. The stress liner may be formed of a carbon based material, preferably a tetrahedral amorphous carbon (ta-C) material including at least about 60 atomic percent carbon and no greater than C about 40 atomic percent hydrogen. The carbon based material may be either a dielectric material, or given appropriate additional dielectric isolation structures, a semiconductor material. In particular, a ta-C stress liner may be formed using a filtered cathodic vacuum arc (FCVA) physical vapor deposition (PVD) method.

Abstract: The organic TFT includes: a gate electrode; source and drain electrodes insulated from the gate electrode; an organic semiconductor layer insulated from the gate electrode and electrically connected to the source and drain electrodes; an insulating layer insulating the gate electrode from the source and drain electrodes and the organic semiconductor layer; and a self-assembly monolayer (SAM) included between the insulating layer and the organic semiconductor layer. A compound forming the SAM has at least one terminal group selected from the group consisting of an unsubstituted or substituted C6-C30 aryl group and an unsubstituted or substituted C2-C30 heteroaryl group. The organic TFT is formed by forming the above-described layers and forming the SAM on the insulating layer before the organic semiconductor layer and source and drain electrodes are formed.

Abstract: An apparatus is described for converting infrared radiation into electric current with a photodiode which comprises two semiconductor layers (1, 2) with a heterojunction which are each connected to an electrode (3, 4) and of which one consists of a doped inorganic semiconductor. In order to ensure advantageous detection it is proposed that the inorganic semiconductor layer (1) forms the heterojunction with an organic semiconductor layer (2) and a cooling device is associated with the two semiconductor layers (1, 2).

Abstract: A halogenated aromatic monomer-metal complex useful for preparing a polymer for electronic devices such as a light-emitting diode (LED) device is described. The aromatic monomer-metal complex is designed to include a linking group that disrupts conjugation, thereby advantageously reducing or preventing electron delocalization between the aromatic monomer fragment and the metal complex fragment. Disruption of conjugation is often desirable to preserve the phosphorescent emission properties of the metal complex in a polymer formed from the aromatic monomer-metal complex. The resultant conjugated electroluminescent polymer has precisely controlled metal complexation and electronic properties that are substantially or completely independent of those of the polymer backbone.

Abstract: A method for fabricating an organic electroluminescent device (OLED) includes the following steps. First, a substrate is provided. Next, an anode layer is formed on the substrate. Next, a buffer layer is formed on the anode layer, wherein the buffer layer include a CFx film (fluorinated carbon films) containing carbon-fluoride bonded molecules. Next, a treatment process is performed on the CFx film to convert the carbon-fluoride bonded molecules into carbon-carbon bonded molecules. A plurality of organic layers is formed on the buffer layer. A cathode layer is formed on the organic layer. Because the buffer layer has a better conductivity, the organic electroluminescent device (OLED) of the present invention has a better luminous efficiency.

Abstract: A step wall is formed over a substrate. Catalytic material of different composition than the step wall is provided proximate thereto. A carbon nanotube is grown from the catalytic material along the step wall generally parallel to the substrate. A method of fabricating integrated circuitry includes forming a step wall over a semiconductor substrate. Catalytic material is provided proximate the step wall. An elevationally outer surface of the catalytic material is masked with a masking material. The catalytic material and the masking material are patterned to form an exposed end sidewall of the catalytic material proximate the step wall, with remaining of the elevationally outer surface of the catalytic material being masked. A carbon nanotube is grown from the exposed end sidewall of the catalytic material along the step wall generally parallel to the semiconductor substrate. The carbon nanotube is incorporated into a circuit component of an integrated circuit.

Abstract: A solar cell is prepared. The solar cell is photo-sensitized. The solar cell has a semiconductor layer. And carbon nanotubes are deposited on the semiconductor layer with an arrangement. The solar cell is prepared with a reduced amount of fabrication material, a lowered fabrication cost and a prolonged lifetime.

Abstract: A multilayer insulating structure including a first stop layer, a first insulating layer and a second stop layer is formed on the first conductive structure. A second conductive structure and a second insulating layer are formed on the first conductive structure. The second insulating layer and the second conductive structure are etched to form a first hole and a second hole having a first radius. A spacer is formed on sidewalls of the first and second holes. The second stop layer and the first insulating layer are etched using the spacer as an etch mask to form a third hole having a second radius smaller than the first radius. A sacrificial filler is formed on the first stop layer to fill the third hole. After removing the spacer, the sacrificial filler is removed. The first stop layer is etched. A carbon nano-tube is grown from the first conductive structure.

Abstract: A semiconductor chip 100 includes a semiconductor substrate (not shown), and a stacked film 150 formed over the semiconductor substrate, which includes carbon-containing insulating films such as a first interlayer insulating film 106, and carbon-free insulating films such as an underlying layer 102 and a top cover film 124. The end faces of the carbon-free insulating films herein are located on the outer side of the end faces of the carbon-containing insulating films. The carbon composition of the carbon-containing insulating films is lowered in the end portions thereof than in the inner portions. The film density of the carbon-containing insulating films is raised in the end portions thereof than in the inner portions.

Abstract: The present invention provides processes for producing horizontal nanowires that are separate and oriented and allow for processing directly on a substrate material. The nanowires grow horizontally by suppressing vertical growth from a nucleating particle, such as a metal film. The present invention also provides for horizontal nanowire growth from nucleating particles on the edges of nanometer-sized steps. Following processing, the nanowires can be removed from the substrate and transferred to other substrates. The present invention also provides for nanowires produced by these processes and electronic devices comprising these nanowires. The present invention also provides for nanowire growth apparatus that provide horizontal nanowires, and processes for producing nanowire devices.

Abstract: A method of batch fabrication using established photolithographic techniques allowing nanoparticles or nanodevices to be fabricated and mounted into a macroscopic device in a repeatable, reliable manner suitable for large-scale mass production. Nanoparticles can be grown on macroscopic “modules” which can be easily manipulated and shaped to fit standard mounts in various devices.

Abstract: A hosting structure of nanometric components is described comprising a substrate, a first multi-spacer level comprising a first plurality of spacers including first conductive spacers parallel to each other, and at least a second multi-spacer level realized above said first multi-spacer level and comprising a second plurality of spacers arranged transversally to said first plurality of spacers and including at least a lower discontinuous insulating layer and an upper layer, including in turn second conductive spacers. In particular, each pair of spacers of the second multi-spacer level defines with a spacer of the first multi-spacer level a plurality of nanometric hosting seats having at least a first and a second conduction terminal realized by portions of the first conductive spacers and of the second conductive spacers faced in the hosting seats. A method for manufacturing such a structure is also described.

Abstract: The invention includes a two terminal switching device having two stable resistivity values for each applied voltage, which when a voltage of not more than a first threshold voltage (Vth1) is applied, becomes in a first state having a higher resistivity, whereas when a larger second threshold voltage (Vth2) or more is applied, becomes in a second state having a lower resistivity; a resistance connected in series to the switching device; a terminal for applying a bias voltage (Vt) to both ends of a series circuit of the switching device and the resistance; a first pulse inputting terminal; and a second pulse inputting terminal. The invention provides a simple realization of a flip-flop circuit for a sequential logic circuit.

Abstract: In a method of achieving uniform lengths of Carbon NanoTubes (CNTs) and a method of manufacturing a Field Emission Device (FED) using such CNTs, an organic film is coated to cover CNTs formed on a predetermined material layer. The organic film is etched to a predetermined depth to remove projected portions of the CNTs. After that, the organic film is removed.

Abstract: A structure to form an energy well within a Carbon nanotube is described. The structure includes a doped semiconductor region and an undoped semiconductor region. The Carbon nanotube is between the doped semiconductor region and the undoped semiconductor region. The structure also includes a delta doped semiconductor region. The undoped semiconductor region is between the Carbon nanotube and the delta doped region. The delta doped semiconductor region is doped opposite that of the doped semiconductor region.

Abstract: Fibers having an electrically conductive outer surface and having an average diameter of less than about 5 millimeters; and a dielectric polymeric layer comprising a polymer having a main polymer chain on the outer surface, the dielectric polymeric layer having a thickness of less than about 50 microns, the main polymer chain comprising carbon. Fiber transistors having an on/off ratio of at least about 10. Techniques for making fibers and fiber transistors.

Abstract: An organic electroluminescence device capable of solving the problem of realization of low-voltage driving and high luminance which is important for the prolongation of the life thereof, the organic electroluminescence device comprising a luminous layer composed of a single or a plurality of organic compound thin films interposed between a positive electrode and a negative electrode, characterized in that at least one layer containing a compound having carbenium ion is arranged therein; and a charge transport material (e.g., hole transport material for the organic electroluminescence device) characterized in that a compound having carbenium ion is contained therein.

Abstract: Phase change memories may exhibit improved properties and lower cost in some cases by forming the phase change material layers in a planar configuration. A heater may be provided below the phase change material layers to appropriately heat the material to induce the phase changes. The heater may be coupled to an appropriate conductor.

Abstract: Nanotube on gate FET structures and applications of such, including n2 crossbars requiring only 2n control lines. A non-volatile transistor device includes a source region and a drain region of a first semiconductor type of material and a channel region of a second semiconductor type of material disposed between the source and drain region. A gate structure is made of at least one of semiconductive or conductive material and is disposed over an insulator over the channel region. A control gate is made of at least one of semiconductive or conductive material. An electromechanically-deflectable nanotube switching element is in fixed contact with one of the gate structure and the control gate structure and is not in fixed contact with the other of the gate structure and the control gate structure. The device has a network of inherent capacitances, including an inherent capacitance of an undeflected nanotube switching element in relation to the gate structure.

Abstract: A stacked organic light emitting device that includes an anode connected to an external power source, a cathode connected to the external power source, at least two light emitting sections aligned between the anode and the cathode, including a light emitting layer, and an internal electrode aligned between the light emitting sections. The internal electrode is a single-layered internal electrode which is made from one selected from the group consisting of a metal, alloys of the metal, and metal oxides thereof, having a work function below 4.5 eV, each light emitting section includes an organic material layer containing an organic material having an electron affinity above 4 eV, and the organic material layer is formed between the light emitting layer of the light emitting section and the electrode facing the anode connected to the external power source in two electrodes which make contact with the light emitting section.

Abstract: The present invention is directed to systems and methods for nanowire growth and harvesting. In an embodiment, methods for nanowire growth and doping are provided, including methods for epitaxial oriented nanowire growth using a combination of silicon precursors. In a further aspect of the invention, methods to improve nanowire quality through the use of sacrifical growth layers are provided. In another aspect of the invention, methods for transferring nanowires from one substrate to another substrate are provided.

Abstract: A structure to form an energy well within a Carbon nanotube is described. The structure includes a doped semiconductor region and an undoped semiconductor region. The Carbon nanotube is between the doped semiconductor region and the undoped semiconductor region. The structure also includes a delta doped semiconductor region. The undoped semiconductor region is between the Carbon nanotube and the delta doped region. The delta doped semiconductor region is doped opposite that of the doped semiconductor region.

Abstract: A conductive layer in an integrated circuit is formed as a sandwich having multiple sublayers, including at least one sublayer of oriented carbon nanotubes. The conductive layer sandwich preferably contains two sublayers of carbon nanotubes, in which the carbon nanotube orientation in one sublayer is substantially perpendicular to that of the other layer. The conductive layer sandwich preferably contains one or more additional sublayers of a conductive material, such as a metal. In one embodiment, oriented carbon nanotubes are created by forming a series of parallel surface ridges, covering the top and one side of the ridges with a catalyst inhibitor, and growing carbon nanotubes horizontally from the uncovered vertical sides of the ridges. In another embodiment, oriented carbon nanotubes are grown on the surface of a conductive material in the presence of a directional flow of reactant gases and a catalyst.

Abstract: A pixel structure and an edge-emitter field-emission display device having a first substrate or backplate including a cathode disposed thereon and a second substrate or faceplate including an anode disposed thereon, wherein the anode on the second substrate or faceplate has a light emitting film. The cathode may define a first bus of an X-Y bus array and the anode may define a second bus of the X-Y bus array. Alternatively, the first substrate may further include a control gate disposed thereon, wherein the cathode defines a first bus of an X-Y bus array and the control gate defines a second bus of the X-Y bus array.