Carbon Nanotubes (epo) Patents (Class 257/E51.04)
  • Patent number: 9997461
    Abstract: Some embodiments include electrical interconnects. The interconnects may contain laminate structures having a graphene region sandwiched between non-graphene regions. In some embodiments the graphene and non-graphene regions may be nested within one another. In some embodiments an electrically insulative material may be over an upper surface of the laminate structure, and an opening may extend through the insulative material to a portion of the laminate structure. Electrically conductive material may be within the opening and in electrical contact with at least one of the non-graphene regions of the laminate structure. Some embodiments include methods of forming electrical interconnects in which non-graphene material and graphene are alternately formed within a trench to form nested non-graphene and graphene regions.
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: June 12, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Gurtej S. Sandhu
  • Patent number: 9443662
    Abstract: A method of forming an ordered nanorods array in a confined space is used to form a high surface area device where an ensemble of parallel trenches has micrometer dimensions for the width and depth of the trenches, which are decorated with crystalline nanowires radiating from the sidewalls and bases of the trenches. The high surface area device is formed by depositing a conformal crystalline seed coating in the trenches, forming microchannels from these trenches by placing a barrier layer on the open surface of the trenches, contacting the conformal coating with a crystal precursor solution that is caused to flow through the microchannels. In an embodiment, a very high surface area electrode is constructed with ZnO nanowires radiating from the sidewalls and base of trenches formed on a silicon substrate. The device can be a dye-sensitized solar cell.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: September 13, 2016
    Assignee: UNIVERSITY OF SOUTH FLORIDA
    Inventors: Mikhail Ladanov, Paula C. Algarin Amaris, Garrett Matthews, Manoj Kumar Ram, Sylvia W. Thomas, Ashok Kumar, Jing Wang, Arash Takshi
  • Patent number: 9040364
    Abstract: A method of creating a semiconductor device is disclosed. An end of a carbon nanotube is unzipped to provide a substantially flat surface. A contact of the semiconductor device is formed. The substantially flat surface of the carbon nanotube is coupled to the contact to create the semiconductor device. An energy gap in the unzipped end of the carbon nanotube may be less than an energy gap in a region of the carbon nanotube outside of the unzipped end region.
    Type: Grant
    Filed: October 30, 2012
    Date of Patent: May 26, 2015
    Assignee: International Business Machines Corporation
    Inventors: Damon B. Farmer, Aaron D. Franklin, Joshua T. Smith, George S. Tulevski
  • Patent number: 9029860
    Abstract: A structure includes a silicon substrate, a plurality of silicon rods on the silicon substrate, a silicon layer on the plurality of silicon rods, and a GaN substrate on the silicon layer.
    Type: Grant
    Filed: March 21, 2013
    Date of Patent: May 12, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Xianyu Wenxu, Yeon-hee Kim, Chang-youl Moon, Yong-young Park
  • Patent number: 9024436
    Abstract: In an embodiment, a thermal interface material (TIM) is provided. The TIM includes first and a second layers of a first transition metal, and a third layer including a plurality of carbon nanotubes supported in a flexible polymer matrix and a second transition metal coupled to sidewalls of carbon nanotubes. The first and second metal layers are in contact with first and second ends of carbon nanotube. The TIM further includes fourth and fifth layers of an alloy material coupled to the first and second metal layers, respectively. The carbon nanotube based TIM including the layers with transition metal allow improved heat transfer from an integrated circuit die to a heat spreader.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: May 5, 2015
    Assignee: Broadcom Corporation
    Inventors: Sam Ziqun Zhao, Arpit Mittal, Rezaur Rahman Khan
  • Patent number: 8993448
    Abstract: A method of forming a plurality of nanotubes is disclosed. Particularly, a substrate may be provided and a plurality of recesses may be formed therein. Further, a plurality of nanotubes may be formed generally within each of the plurality of recesses and the plurality of nanotubes may be substantially surrounded with a supporting material. Additionally, at least some of the plurality of nanotubes may be selectively shortened and at least a portion of the at least some of the plurality of nanotubes may be functionalized. Methods for forming semiconductor structures intermediate structures, and semiconductor devices are disclosed. An intermediate structure, intermediate semiconductor structure, and a system including nanotube structures are also disclosed.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: March 31, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Terry L. Gilton
  • Patent number: 8987707
    Abstract: Thin-film transistors comprising buckled films comprising carbon nanotubes as the conductive channel are provided. Also provided are methods of fabricating the transistors. The transistors, which are highly stretchable and bendable, exhibit stable performance even when operated under high tensile strains.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: March 24, 2015
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Michael S. Arnold, Feng Xu
  • Patent number: 8957406
    Abstract: Various methods and apparatuses involve the provision of graphitic material. As consistent with one or more aspects herein, an organic material template is used to restrict growth, in a width dimension, of graphitic material grown from the organic material template. Graphitic material is therein provided, having a set of characteristics including electrical behavior and shape, with a representative width defined by the width dimension, based on the organic material template.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: February 17, 2015
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Anatoliy N. Sokolov, Fung Ling Yap, Zhenan Bao, Nan Liu
  • Patent number: 8946683
    Abstract: The present invention provides device components geometries and fabrication strategies for enhancing the electronic performance of electronic devices based on thin films of randomly oriented or partially aligned semiconducting nanotubes. In certain aspects, devices and methods of the present invention incorporate a patterned layer of randomly oriented or partially aligned carbon nanotubes, such as one or more interconnected SWNT networks, providing a semiconductor channel exhibiting improved electronic properties relative to conventional nanotubes-based electronic systems.
    Type: Grant
    Filed: June 16, 2009
    Date of Patent: February 3, 2015
    Assignees: The Board of Trustees of the University of Illinois, Purdue Research Foundation
    Inventors: John A. Rogers, Qing Cao, Muhammad Alam, Ninad Pimparkar
  • Patent number: 8921835
    Abstract: An organic light emitting diode display includes: a base film made of plastic; a thin film transistor and an organic light emitting diode formed on the base film; and a carbon nanotube thin film disposed among the base film, the thin film transistor, and the organic light emitting diode.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: December 30, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jae-Seob Lee, Chang-Yong Jung, Yong-Hwan Park, Kyung-Mi Kwon
  • Patent number: 8895958
    Abstract: Disclosed is a light emitting element, which emits light with small power consumption and high luminance. The light emitting element has: a IV semiconductor substrate; two or more core multi-shell nanowires disposed on the IV semiconductor substrate; a first electrode connected to the IV semiconductor substrate; and a second electrode, which covers the side surfaces of the core multi-shell nanowires, and which is connected to the side surfaces of the core multi-shell nanowires. Each of the core multi-shell nanowires has: a center nanowire composed of a first conductivity type III-V compound semiconductor; a first barrier layer composed of the first conductivity type III-V compound semiconductor; a quantum well layer composed of a III-V compound semiconductor; a second barrier layer composed of a second conductivity type III-V compound semiconductor; and a capping layer composed of a second conductivity type III-V compound semiconductor.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: November 25, 2014
    Assignees: National University Corporation Hokkaido University, Sharp Kabushiki Kaisha
    Inventors: Takashi Fukui, Katsuhiro Tomioka
  • Patent number: 8884273
    Abstract: Methods for producing nanostructures, particularly Group III-V semiconductor nanostructures, are provided. The methods include use of novel Group III and/or Group V precursors, novel surfactants, oxide acceptors, high temperature, and/or stable co-products. Related compositions are also described. Methods and compositions for producing Group III inorganic compounds that can be used as precursors for nanostructure synthesis are provided. Methods for increasing the yield of nanostructures from a synthesis reaction by removal of a vaporous by-product are also described.
    Type: Grant
    Filed: October 7, 2011
    Date of Patent: November 11, 2014
    Assignee: Nanosys, Inc.
    Inventors: Erik C. Scher, Mihai A. Buretea, William P. Freeman, Joel Gamoras, Baixin Qian, Jeffery A. Whiteford
  • Patent number: 8872154
    Abstract: Methods and apparatus for an electronic device such as a field effect transistor. One embodiment includes fabrication of an FET utilizing single walled carbon nanotubes as the semiconducting material. In one embodiment, the FETs are vertical arrangements of SWCNTs, and in some embodiments prepared within porous anodic alumina (PAA). Various embodiments pertain to different methods for fabricating the drains, sources, and gates.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: October 28, 2014
    Assignee: Purdue Research Foundation
    Inventors: Aaron D. Franklin, Timothy D. Sands, Timothy S. Fisher, David B. Janes
  • Patent number: 8872162
    Abstract: A field-effect transistor includes a semiconductor layer containing carbon nanomaterials; a first electrode and a second electrode formed in contact with the semiconductor layer; a third electrode for controlling current flowing between the first electrode and the second electrode; and an insulating layer formed between the semiconductor layer and the third electrode. The insulating layer contains an aromatic polyamide comprising a substituent containing 1 to 20 carbon atoms.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: October 28, 2014
    Assignee: NEC Corporation
    Inventor: Hiroyuki Endoh
  • Patent number: 8859316
    Abstract: A Schottky junction silicon nanowire field-effect biosensor/molecule detector with a nanowire thickness of 10 nanometer or less and an aligned source/drain workfunction for increased sensitivity. The nanowire channel is coated with a surface treatment to which a molecule of interest absorbs, which modulates the conductivity of the channel between the Schottky junctions sufficiently to qualitatively and quantitatively measure the presence and amount of the molecule.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: October 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Dechao Guo, Christian Lavoie, Christine Ouyang Qiqing, Yanning Sun, Zhen Zhang
  • Patent number: 8853061
    Abstract: A method for forming a graphite-based device on a substrate having a plurality of zones is provided where the substrate is carbon doped in zones. Each such zone comprises a plurality of dopant profiles. One or more graphene stacks are generated in the doped zones. A graphene stack so generated comprises a non-planar graphene layer characterized by a bending angle, curvature, characteristic dimension, graphene orientation, graphene type, or combinations thereof. A method for forming a graphite-based device on a substrate is provided, the substrate comprising a graphene foundation material and a plurality of zones. The substrate is patterned to form features in the zones. One feature comprises a non-planar surface or at least two adjacent surfaces that are not coplanar. One or more graphene stacks are concurrently generated, at least one of which comprises a non-planar graphene layer overlaying the non-planar surface or the at least two adjacent surfaces.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: October 7, 2014
    Assignee: Solan, LLC
    Inventor: Mark Alan Davis
  • Patent number: 8847395
    Abstract: A microelectronic device, including: a substrate and a plurality of metal interconnection levels stacked on the substrate; a first metal line of a given metal interconnection level; a second metal line of another metal interconnection level located above the given metal interconnection level, the first and second lines are interconnected via at least one semiconductor connection element extending in a direction forming a nonzero angle with the first metal lines and the second metal line; and a gate electrode capable of controlling conduction of the semiconductor connection element.
    Type: Grant
    Filed: July 5, 2011
    Date of Patent: September 30, 2014
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventors: Thomas Ernst, Paul-Henry Morel, Sylvain Maitrejean
  • Patent number: 8828256
    Abstract: A method for making a carbon nanotube film includes the steps of providing an array of carbon nanotubes, treating the array of carbon nanotubes by plasma, and pulling out a carbon nanotube film from the array of carbon nanotubes treated by the plasma.
    Type: Grant
    Filed: January 8, 2009
    Date of Patent: September 9, 2014
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Chen Feng, Kai Liu, Yong-Chao Zhai, Kai-Li Jiang, Shou-Shan Fan
  • Patent number: 8815625
    Abstract: A pressure sensor having a structure, which includes a supporting body, a circuit arrangement and at least one circuit support. The circuit arrangement includes circuit components, amongst which detection means for generating electrical signals representing a quantity to be detected. The at least one circuit support is connected to the supporting body and has a surface, formed on which is a plurality of said circuit components, amongst which electrically conductive paths, where the circuit support is laminated on the first face of the supporting body.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: August 26, 2014
    Assignee: Metallux SA
    Inventor: Massimo Monichino
  • Patent number: 8816328
    Abstract: A method to fabricate a carbon nanotube (CNT)-based transistor includes providing a substrate having a CNT disposed over a surface; forming a protective electrically insulating layer over the CNT and forming a first multi-layer resist stack (MLRS) over the protective electrically insulating layer. The first MLRS includes a bottom layer, an intermediate layer and a top layer of resist. The method further includes patterning and selectively removing a portion of the first MLRS to define an opening for a gate stack while leaving the bottom layer; selectively removing a portion of the protective electrically insulating layer within the opening to expose a first portion of the CNT; forming the gate stack within the opening and upon the exposed first portion of the carbon nanotube, followed by formation of source and drain contacts also in accordance with the inventive method so as to expose second and third portions of the CNT.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: August 26, 2014
    Assignee: International Business Machines Corporation
    Inventors: Josephine B Chang, Martin Glodde, Michael A. Guillorn
  • Patent number: 8803129
    Abstract: A structure includes a substrate having a carbon nanotube (CNT) disposed over a surface. The CNT is partially disposed within a protective electrically insulating layer. The structure further includes a gate stack disposed over the substrate. A first portion of a length of the CNT not covered by the protective electrically insulating layer passes through the gate stack. Source and drain contacts are disposed adjacent to the gate stack, where second and third portions of the length of CNT not covered by the protective electrically insulating layer are conductively electrically coupled to the source and drain contacts. The gate stack and the source and drain contacts are contained within the protective electrically insulating layer and within an electrically insulating organic planarization layer that is disposed over the protective electrically insulating layer. A method to fabricate a CNT-based transistor is also described.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: August 12, 2014
    Assignee: International Business Machines Corporation
    Inventors: Josephine B Chang, Martin Glodde, Michael A. Guillorn
  • Patent number: 8785763
    Abstract: Nanostructures are joined using one or more of a variety of materials and approaches. As consistent with various example embodiments, two or more nanostructures are joined at a junction between the nanostructures. The nanostructures may touch or be nearly touching at the junction, and a joining material is deposited and nucleates at the junction to couple the nanostructures together. In various applications, the nucleated joining material facilitates conductivity (thermal and/or electric) between the nanostructures. In some embodiments, the joining material further enhances conductivity of the nanostructures themselves, such as by growing along the nanostructures and/or doping the nanostructures.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: July 22, 2014
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Melburne C. LeMieux, Ajay Virkar, Zhenan Bao
  • Patent number: 8754403
    Abstract: A method of forming a self-aligned device is provided and includes depositing carbon nanotubes (CNTs) onto a crystalline dielectric substrate, isolating a portion of the crystalline dielectric substrate encompassing a location of the CNTs, forming gate dielectric and gate electrode gate stacks on the CNTs while maintaining a structural integrity thereof and forming epitaxial source and drain regions in contact with portions of the CNTs on the crystalline dielectric substrate that are exposed from the gate dielectric and gate electrode gate stacks.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: June 17, 2014
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Paul Chang, Vijay Narayanan, Jeffrey W. Sleight
  • Patent number: 8741756
    Abstract: A method of fabricating a semiconducting device is disclosed. A carbon nanotube is deposited on a substrate of the semiconducting device. A first contact on the substrate over the carbon nanotube. A second contact on the substrate over the carbon nanotube, wherein the second contact is separated from the first contact by a gap. A portion of the substrate in the gap between the first contact and the second contact is removed.
    Type: Grant
    Filed: August 13, 2012
    Date of Patent: June 3, 2014
    Assignee: International Business Machines Corporation
    Inventors: Aaron D. Franklin, Shu-jen Han, Joshua T. Smith, Paul M. Solomon
  • Patent number: 8674412
    Abstract: A method of fabricating a semiconducting device is disclosed. A carbon nanotube is deposited on a substrate of the semiconducting device. A first contact on the substrate over the carbon nanotube. A second contact on the substrate over the carbon nanotube, wherein the second contact is separated from the first contact by a gap. A portion of the substrate in the gap between the first contact and the second contact is removed.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: March 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Aaron D. Franklin, Shu-jen Han, Joshua T. Smith, Paul M. Solomon
  • Patent number: 8664091
    Abstract: A method for removing a metallic nanotube, which is formed on a substrate in a first direction, includes forming a plurality of conductors in a second direction crossing the first direction, electrically contacting the plurality of conductors with metallic nanotube, respectively, forming at least two voltage-applying electrodes on the conductors, each of which electrically contacting at least one of the conductors, and applying voltages to at least some of the conductors through the voltage-applying electrodes, respectively. Among the conductors to which the voltages are respectively applied, every two adjacent conductors have an electrical potential difference created therebetween, so as to burn out the metallic nanotube.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: March 4, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Zhijiong Luo, Haizhou Yin
  • Patent number: 8652874
    Abstract: A method of making nanostructures using a self-assembled monolayer of organic spheres is disclosed. The nanostructures include bowl-shaped structures and patterned elongated nanostructures. A bowl-shaped nanostructure with a nanorod grown from a conductive substrate through the bowl-shaped nanostructure may be configured as a field emitter or a vertical field effect transistor. A method of separating nanoparticles of a desired size employs an array of bowl-shaped structures.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: February 18, 2014
    Assignee: Georgia Tech Research Corporation
    Inventors: Zhong L. Wang, Christopher J. Summers, Xudong Wang, Elton D Graugnard, Jeffrey King
  • Patent number: 8647894
    Abstract: A method for depositing graphene is provided. The method includes depositing a layer of non-conducting amorphous carbon over a surface of a substrate and depositing a transition metal in a pattern over the amorphous carbon. The substrate is annealed at a temperature below 500° C., where the annealing converts the non-conducting amorphous carbon disposed under the transition metal to conducting amorphous carbon. A portion of the pattern of the transition metal is removed from the surface of the substrate to expose the conducting amorphous carbon.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: February 11, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Sandip Niyogi, Sean Barstow
  • Patent number: 8647922
    Abstract: The present invention relates to a method of forming a wire bond-free conductive interconnect area on a semiconductor substrate. A semiconductor substrate with an electrically conductive protrusion, defining a bond pad, is provided as well as a plurality of carbon nanotubes. The plurality of carbon nanotubes is immobilized on the bond pad by allowing at least one random portion along the length of the carbon nanotubes to attach to the surface of the bond pad. Thus an aggregate of loops of carbon nanotubes is formed on the surface of the bond pad. Thereby a conductive interconnect area is formed on the electrically conductive protrusion without heat treatment.
    Type: Grant
    Filed: November 8, 2007
    Date of Patent: February 11, 2014
    Assignee: Nanyang Technological University
    Inventors: Jijie Zhou, Zhong Chen
  • Patent number: 8637356
    Abstract: A non-volatile bistable nano-electromechanical switch is provided for use in memory devices and microprocessors. The switch employs carbon nanotubes as the actuation element. A method has been developed for fabricating nanoswitches having one single-walled carbon nanotube as the actuator. The actuation of two different states can be achieved using the same low voltage for each state.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: January 28, 2014
    Assignee: Northeastern University
    Inventors: Sivasubramanian Somu, Ahmed Busnaina, Nicol McGruer, Peter Ryan, George G. Adams, Xugang Xiong, Taehoon Kim
  • Patent number: 8629010
    Abstract: Carbon nanotubes can be aligned with compatibility with semiconductor manufacturing processes, with scalability for forming smaller devices, and without performance degradation related to structural damages. A planar structure including a buried gate electrode and two embedded electrodes are formed. After forming a gate dielectric, carbon nanotubes are assembled in a solution on a surface of the gate dielectric along the direction of an alternating current (AC) electrical field generated by applying a voltage between the two embedded electrodes. A source contact electrode and a drain contact electrode are formed by depositing a conductive material on both ends of the carbon nanotubes. Each of the source and drain contact electrodes can be electrically shorted to an underlying embedded electrode to reduce parasitic capacitance.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: January 14, 2014
    Assignees: International Business Machines Corporation, Karlsruher Institut Fuer Technologie (KIT)
    Inventors: Phaedon Avouris, Yu-Ming Lin, Mathias B. Steiner, Michael W. Engel, Ralph Krupke
  • Patent number: 8618611
    Abstract: Embodiments of the invention integrate carbon nanotubes on a CMOS substrate using localized heating. An embodiment can allow the CMOS substrate to be in a room-temperature environment during the carbon nanotube growth process. Specific embodiments utilize a maskless post-CMOS microelectromechanical systems (MEMS) process. The post-CMOS MEMS process according to an embodiment of the present invention provides a carbon nanotube growth process that is foundry CMOS compatible. The maskless process, according to an embodiment, eliminates the need for photomasks after the CMOS fabrication and can preserve whatever feature sizes are available in the foundry CMOS process. Embodiments integrate single-walled carbon nanotube devices into a CMOS platform.
    Type: Grant
    Filed: June 16, 2008
    Date of Patent: December 31, 2013
    Assignee: University of Florida Research Foundation, Inc.
    Inventors: Huikai Xie, Ant Ural
  • Patent number: 8604459
    Abstract: Electrical devices containing carbon nanotubes can be passivated to protect the carbon nanotubes from degradation while substantially preserving the carbon nanotubes' electrical conductivity and switching characteristics. Such electrical devices can include a first metal contact, a switching layer containing a plurality of carbon nanotubes disposed on the first metal contact, a passivation layer containing amorphous carbon, a metal carbide, or any combination thereof that is disposed on at least a top surface of the switching layer, and a second metal contact disposed upon the passivation layer. Methods for forming the electrical devices can include disposing a passivation layer containing amorphous carbon on at least a top surface of the switching layer, and optionally heating to at least partially convert the amorphous carbon within the passivation layer into a metal carbide.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: December 10, 2013
    Assignee: Lockheed Martin Corporation
    Inventors: Jonathan W. Ward, Garo J. Derderian
  • Patent number: 8603836
    Abstract: Disclosed is a transparent carbon nanotube (CNT) electrode using a conductive dispersant. The transparent CNT electrode comprises a transparent substrate and a CNT thin film formed on a surface the transparent substrate wherein the CNT thin film is formed of a CNT composition comprising CNTs and a doped dispersant. Further disclosed is a method for producing the transparent CNT electrode. The transparent CNT electrode exhibits excellent conductive properties, can be produced in an economical and simple manner by a room temperature wet process, and can be applied to flexible displays. The transparent CNT electrode can be used to fabricate a variety of devices, including image sensors, solar cells, liquid crystal displays, organic electroluminescence (EL) displays and touch screen panels, that are required to have both light transmission properties and conductive properties.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: December 10, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seon Mi Yoon, Jae Young Choi, Dong Kee Yi, Seong Jae Choi, Hyeon Jin Shin
  • Patent number: 8598689
    Abstract: A method of forming a plurality of nanotubes is disclosed. Particularly, a substrate may be provided and a plurality of recesses may be formed therein. Further, a plurality of nanotubes may be formed generally within each of the plurality of recesses and the plurality of nanotubes may be substantially surrounded with a supporting material. Additionally, at least some of the plurality of nanotubes may be selectively shortened and at least a portion of the at least some of the plurality of nanotubes may be functionalized. Methods for forming semiconductor structures intermediate structures, and semiconductor devices are disclosed. An intermediate structure, intermediate semiconductor structure, and a system including nanotube structures are also disclosed.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: December 3, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Terry L. Gilton
  • Patent number: 8586458
    Abstract: Provided are a method of doping carbon nanotubes, p-doped carbon nanotubes prepared using the method, and an electrode, a display device or a solar cell including the carbon nanotubes. Particularly, a method of doping carbon nanotubes having improved conductivity by reforming the carbon nanotubes using an oxidizer, doped carbon nanotubes prepared using the method, and an electrode, a display device or a solar cell including the carbon nanotubes are provided.
    Type: Grant
    Filed: March 6, 2008
    Date of Patent: November 19, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seon-mi Yoon, Seong-jae Choi, Hyeon-jin Shin, Jae-young Choi, Sung-jin Kim, Young-hee Lee
  • Patent number: 8558256
    Abstract: Provided are a light emitting diode (LED) using a Si nanowire as an emission device and a method of fabricating the same. The LED includes: a semiconductor substrate; first and second semiconductor protrusions disposed on the semiconductor substrate to face each other; a semiconductor nanowire suspended between the first and second semiconductor protrusions; and first and second electrodes disposed on the first and second protrusions, respectively.
    Type: Grant
    Filed: October 19, 2007
    Date of Patent: October 15, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-ha Hong, Young-gu Jin, Jai-kwang Shin, Sung-Il Park, Jong-seob Kim
  • Patent number: 8558220
    Abstract: In some aspects, a method of fabricating a memory cell is provided that includes (1) fabricating a first conductor above a substrate; (2) selectively fabricating a carbon nano-tube (CNT) material above the first conductor; (3) fabricating a diode above the CNT material; and (4) fabricating a second conductor above the diode. Numerous other aspects are provided.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: October 15, 2013
    Assignee: SanDisk 3D LLC
    Inventors: April Schricker, Mark Clark, Brad Herner
  • Patent number: 8535753
    Abstract: Methods of forming carbon nanotubes include forming a catalytic metal layer on a sidewall of an electrically conductive region, such as a metal or metal nitride pattern. A plurality of carbon nanotubes are grown from the catalytic metal layer. These carbon nanotubes can be grown from a sidewall of the catalytic metal layer. The plurality of carbon nanotubes are then exposed to an organic solvent. This step of exposing the carbon nanotubes to the organic solvent may be preceded by a step of applying centrifugal forces to the plurality of carbon nanotubes. Alternatively, the exposing step may include applying a centrifugal force to the plurality of carbon nanotubes while simultaneously exposing the plurality of carbon nanotubes to an organic solvent.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: September 17, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Xianfeng Wang, Hong-Sik Yoon, In-Seok Yeo
  • Patent number: 8530271
    Abstract: Nanostructures are doped to set conductivity characteristics. In accordance with various example embodiments, nanostructures such as carbon nanotubes are doped with a halogenated fullerene type of dopant material. In some implementations, the dopant material is deposited from solution or by vapor deposition, and used to dope the nanotubes to increase the thermal and/or electrical conductivity of the nanotubes.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: September 10, 2013
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Ajay Virkar, Melburne C. Lemieux, Zhenan Bao
  • Patent number: 8530889
    Abstract: A carbon nanotube composite in which a conjugated polymer containing repeating units containing a fused heteroaryl unit having a nitrogen-containing double bond in the ring, and a thiophene unit is attached to at least a part of the surface of a carbon nanotube. The present invention reduces the hysteresis of a field-effect transistor having a semiconductor layer containing a carbon nanotube.
    Type: Grant
    Filed: May 11, 2009
    Date of Patent: September 10, 2013
    Assignee: Toray Industries, Inc.
    Inventors: Yukari Jo, Seiichiro Murase, Daisuke Kitazawa, Jun Tsukamoto
  • Patent number: 8524525
    Abstract: Nanostructures are joined using one or more of a variety of materials and approaches. As consistent with various example embodiments, two or more nanostructures are joined at a junction between the nanostructures. The nanostructures may touch or be nearly touching at the junction, and a joining material is deposited and nucleates at the junction to couple the nanostructures together. In various applications, the nucleated joining material facilitates conductivity (thermal and/or electric) between the nanostructures. In some embodiments, the joining material further enhances conductivity of the nanostructures themselves, such as by growing along the nanostructures and/or doping the nanostructures.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: September 3, 2013
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Melburne C. LeMieux, Ajay Virkar, Zhenan Bao
  • Patent number: 8519379
    Abstract: An embodiment relates to a device comprising a substrate, a nanowire and a doped epitaxial layer surrounding the nanowire, wherein the nanowire is configured to be both a channel to transmit wavelengths up to a selective wavelength and an active element to detect the wavelengths up to the selective wavelength transmitted through the nanowire. Another embodiment relates to a device comprising a substrate, a nanowire and one or more photogates surrounding the nanowire, wherein the nanowire is configured to be both a channel to transmit wavelengths up to a selective wavelength and an active element to detect the wavelengths up to the selective wavelength transmitted through the nanowire, and wherein the one or more photogates comprise an epitaxial layer.
    Type: Grant
    Filed: December 8, 2009
    Date of Patent: August 27, 2013
    Assignee: Zena Technologies, Inc.
    Inventors: Young-June Yu, Munib Wober
  • Patent number: 8513099
    Abstract: A method of forming a self-aligned device is provided and includes depositing carbon nanotubes (CNTs) onto a crystalline dielectric substrate, isolating a portion of the crystalline dielectric substrate encompassing a location of the CNTs, forming gate dielectric and gate electrode gate stacks on the CNTs while maintaining a structural integrity thereof and forming epitaxial source and drain regions in contact with portions of the CNTs on the crystalline dielectric substrate that are exposed from the gate dielectric and gate electrode gate stacks.
    Type: Grant
    Filed: June 17, 2010
    Date of Patent: August 20, 2013
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Paul Chang, Vijay Narayanan, Jeffrey W. Sleight
  • Patent number: 8501529
    Abstract: Provided are a method of doping carbon nanotubes, p-doped carbon nanotubes prepared using the method, and an electrode, a display device or a solar cell including the carbon nanotubes. Particularly, a method of doping carbon nanotubes having improved conductivity by reforming the carbon nanotubes using an oxidizer, doped carbon nanotubes prepared using the method, and an electrode, a display device or a solar cell including the carbon nanotubes are provided.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: August 6, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seon-mi Yoon, Seong-jae Choi, Hyeon-jin Shin, Jae-young Choi, Sung-jin Kim, Young-hee Lee
  • Patent number: 8466044
    Abstract: Memory cells, and methods of forming such memory cells, are provided that include a carbon-based reversible resistivity switching material. In particular embodiments, methods in accordance with this invention form a memory cell by forming a carbon-based reversible resistance-switching material above a substrate, forming a carbon nitride layer above the carbon-based reversible resistance-switching material, and forming a barrier material above the carbon nitride layer using an atomic layer deposition process. Other aspects are also provided.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: June 18, 2013
    Assignee: SanDisk 3D LLC
    Inventor: Huiwen Xu
  • Patent number: 8455311
    Abstract: A solid state Klystron structure is fabricated by forming a source contact and a drain contact to both ends of a conducting wire and by forming a bias gate and a signal gate on the conducting wire. The conducting wire may be at least one carbon nanotube or at least one semiconductor wire with long ballistic mean free paths. By applying a signal at a frequency that corresponds to an integer multiple of the transit time of the ballistic carriers between adjacent fingers of the signal gate, the carriers are bunched within the conducting wire, thus amplifying the current through the solid state Klystron at a frequency of the signal to the signal gate, thus achieving a power gain.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: June 4, 2013
    Assignee: International Business Machines Corporation
    Inventor: Paul M. Solomon
  • Patent number: 8440994
    Abstract: Carbon nanotube (CNT)-based devices and technology for their fabrication are disclosed. The discussed electronic and photonic devices and circuits rely on the nanotube arrays grown on a variety of substrates, such as glass or Si wafer. The planar, multiple layer deposition technique and simple methods of change of the nanotube conductivity type during the device processing are utilized to provide a simple and cost effective technology for a large scale circuit integration. Such devices as p-n diode, CMOS-like circuit, bipolar transistor, light emitting diode and laser are disclosed, all of them are expected to have superior performance then their semiconductor-based counterparts due to excellent CNT electrical and optical properties. When fabricated on Si-wafers, the CNT-based devices can be combined with the Si circuit elements, thus producing hybrid Si-CNT devices and circuits.
    Type: Grant
    Filed: January 24, 2008
    Date of Patent: May 14, 2013
    Assignee: Nano-Electronic and Photonic Devices and Circuits, LLC
    Inventor: Alexander Kastalsky
  • Patent number: 8421129
    Abstract: A CNT channel layer of a transistor is cut along a direction perpendicular to the channel to form a plurality of CNT patches, which are used to connect between a source and a drain. The arrangement of the CNT channel layer formed of a plurality of CNT patches can increase the probability that part of CNT patches becomes a semiconductive CNT patch. Since part of a plurality of CNT patches forming the channel layer is formed of a semiconductive CNT patch, a transistor having a good on/off ratio can be provided.
    Type: Grant
    Filed: April 9, 2008
    Date of Patent: April 16, 2013
    Assignee: NEC Corporation
    Inventor: Masahiko Ishida
  • Patent number: 8415787
    Abstract: The present invention relates to a heat dissipator that includes a conductive substrate and a plurality of nanostructures supported by the conductive substrate. The nanostructures are at least partly embedded in an insulator. Each of the nanostructures includes a plurality of intermediate layers on the conductive substrate. At least two of the plurality of intermediate layers are interdiffused, and material of the at least two of the plurality of intermediate layers that are interdiffused is present in the nanostructure.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: April 9, 2013
    Assignee: Smoltek AB
    Inventor: Mohammad Shafiqul Kabir