Electric Condenser Making Patents (Class 29/25.41)
  • Patent number: 6568054
    Abstract: A method of producing a multilayer electronic part having the shape of a substantially rectangular parallelopiped is constituted which has a multilayer body formed by superposing coil conductors and green sheets of a magnetic or nonmagnetic material. Terminal electrodes are formed respectively on both ends of the multilayer body along the direction of the magnetic flux generated when current is caused to flow through the coil conductors in the multilayer body. The terminal electrodes each has a conductive substrate formed within the area of the end of the multilayer body and including a lamination body as a component of the multilayer body.
    Type: Grant
    Filed: February 24, 2000
    Date of Patent: May 27, 2003
    Assignee: TKD Corporation
    Inventors: Shuumi Kumagai, Kouzou Sasaki, Makoto Kobayashi, Noriyuki Saito, Hisayuki Abe, Toru Takahashi, Kenji Shibata
  • Patent number: 6568053
    Abstract: A method for manufacturing a ceramic resonator is disclosed. The method comprises the steps of forming a ceramic piezoelectric device, a capacitor chip and a lead frame, assembling the piezoelectric device and the capacitor chip into the lead frame, and molding the assembled chip by using epoxy resin. A process for making the capacitor includes the steps of cutting a ceramic wafer into a plurality of sub-wafers, printing electrodes on one face of the sub-wafer in a dual-striped form, drying the sub-wafer thus printed, printing another electrode on a central part of another face of the sub-wafer so as to be overlapped with the electrodes of the one face of the sub-wafer, drying the sub-wafer thus printed, baking the sub-wafer thus dried; and cutting the sub-wafer thus baked into a plurality of capacitors.
    Type: Grant
    Filed: October 5, 2000
    Date of Patent: May 27, 2003
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Nak Cheol Sung, Min Soo Kim, Jeong Ho Cho
  • Publication number: 20030084561
    Abstract: The electrostatic capacitance of piezoelectric elements constituting a Langevin oscillator is measured, and a bolt is tightened so that the measurement value becomes optimum.
    Type: Application
    Filed: October 31, 2002
    Publication date: May 8, 2003
    Applicant: Olympus Optical Co. Ltd.
    Inventor: Norihiro Yamada
  • Patent number: 6558737
    Abstract: A method for producing an electrode for a capacitor, particularly an electrolyte capacitor, proceeding from an alloy with a component A and a component B, wherein the surface energy of the component A is greater than the surface energy of the component B and wherein a layer containing the component B arises at the surface of a body containing the component A by oxidation-induced segregation and tempering of the alloy. A method for producing a capacitor with such an electrode is also disclosed. The long-time stability of the electrode or, respectively, of the capacitor can be improved by the production of an intermediate layer which impedes the diffusion of oxygen and which dissolves less oxygen than the electrode body.
    Type: Grant
    Filed: November 28, 2000
    Date of Patent: May 6, 2003
    Assignee: EPCOS AG
    Inventors: Melanie Stenzel, Holger Zillgen, Janos Giber
  • Patent number: 6550117
    Abstract: Internal electrode layers of a multilayer ceramic electronic element are structured such that spaces, which are formed between adjacent internal electrodes, are eliminated so as to substantially flatten the internal electrode layers. Moreover, the thickness of each green dielectric layer is reduced. To achieve this, a laminating process is performed by a thermal transfer printing method such that a thermal transfer conductor material and a thermal transfer dielectric material are used so as to form internal electrode portions and green dielectric portions. Thus, the internal electrode layers are formed.
    Type: Grant
    Filed: June 20, 2000
    Date of Patent: April 22, 2003
    Assignee: TDK Corporation
    Inventors: Yasumichi Tokuoka, Takeshi Nomura
  • Patent number: 6546607
    Abstract: A method for forming a crater-style sampling capacitor. The capacitor includes a dielectric having a smooth crater shaped input electrode on a first surface and output and guard electrodes on a second surface. A sampling capacitor is defined by the input and output electrodes, and a guard capacitor is defined by the input and guard electrodes. The edge of input electrode is positioned below the first surface to increase surface flash over voltage, further, the input electrode is curved to eliminate corona discharge at edges of the input electrode and to reduce self-heating to negligible levels. The apparatus is suitable for high-voltage radio-frequency applications, such as a mass spectrometer, or other high-voltage applications that require an accurate sampling capacitor for amplitude control and accurate sampling of radio-frequency wave-forms.
    Type: Grant
    Filed: April 3, 2000
    Date of Patent: April 15, 2003
    Assignee: Agilent Technologies, Inc.
    Inventors: Robert K. Crawford, J. Gerson Goldberg
  • Publication number: 20030061694
    Abstract: A method of processing a ceramic capacitor includes a first step of applying a DC voltage to a ceramic capacitor by a first DC voltage source, and a second step of applying a DC voltage by a second DC voltage source to generate in the ceramic capacitor a polarization in a direction opposite to a direction of a polarization generated by the application of the DC voltage in the first step, thereby reducing electric charge remaining in the ceramic capacitor.
    Type: Application
    Filed: August 15, 2002
    Publication date: April 3, 2003
    Inventor: Gaku Kamitani
  • Publication number: 20030051324
    Abstract: According to the present invention, a method of manufacturing a ferroelectric capacitor using a ferroelectric thin film, includes steps of: forming a lower conductive layer on a semiconductor substrate; coating solution of ferroelectric coking including organic solvent and organometallic complex on the lower conductive layer; performing a heating process for coated solution at temperature, to decompose said organometallic complex in solution of ferroelectric coking, or more and ferroelectric crystallization temperature or below to form said metal compound thin film; forming an upper conductive layer on said metal compound thin film; and performing a heating process for said metal compound thin film at ferroelectric crystallization temperature or more to form said ferroelectric thin film.
    Type: Application
    Filed: December 13, 2001
    Publication date: March 20, 2003
    Inventor: Daisuke Inomata
  • Publication number: 20030041427
    Abstract: A green laminated body is subjected to heat treatment in a pressurized atmosphere at a gauge pressure exceeding 0.1 MPa to thereby remove binder. The resulting green laminated body is fired and thereby yields an laminated body including internal electrodes made of a metal film.
    Type: Application
    Filed: August 23, 2002
    Publication date: March 6, 2003
    Inventor: Koji Hattori
  • Patent number: 6523235
    Abstract: A method of manufacturing a ceramic capacitor relates to a ceramic capacitor having metal plate terminals that absorb thermal stress and mechanical stress caused by flexure of the substrate. A ceramic capacitor element is provided with terminal electrodes at the two side end surfaces facing opposite each other. The metal plate terminals are each connected to one of the terminal electrodes at one end thereof, are each provided with a folded portion in a middle area and a terminal portion to be connected to the outside toward the other end from the folded portion.
    Type: Grant
    Filed: October 27, 2000
    Date of Patent: February 25, 2003
    Assignee: TDK Corporation
    Inventors: Takaya Ishigaki, Masatoshi Ishikawa, Takashi Kamiya, Shunji Itakura, Yuji Aiba, Masanori Yamamoto
  • Publication number: 20030033701
    Abstract: Supercapacitor cell electrode (13, 17) and separator (15) elements are fabricated from activated carbon fabric and membranes of microporous fibrillar ultra-high molecular weight polyethylene and are laminated with electrically conductive current collector elements (11, 19) to form a flexible, unitary supercapacitor structure (10). The micro-fibrillar laminar structure of the separator membrane material enables direct application of cell lamination temperatures without resulting collapse of separator microporosity and attendant loss of essential electrolyte retention and ionic conductivity. The superior functional materials enable the fabrication of flexible, self-supporting cell structures which yield improved specific energy capacity and increased voltage output for utilization demands.
    Type: Application
    Filed: January 18, 2001
    Publication date: February 20, 2003
    Inventor: Glenn G. Amatucci
  • Publication number: 20030009866
    Abstract: A capacitor manufacturing method is provided in which an underlying noble metal layer is not sputtered during formation of a hole in which a lower electrode is buried, and in which a dummy interlayer film is less apt to peel off. A stopper layer (9) is formed on an underlying noble metal layer (4) and a dummy interlayer film (5) is formed on the stopper layer (9). Therefore the underlying noble metal layer (4) is not sputtered by overetch during formation of holes (6a ) and (6b). Furthermore, the dummy interlayer film (5) is less apt to peel off since titanium used as the material of the stopper layer (9) has better adhesion to the dummy interlayer film formed of silicon oxide film than platinum used as the material of the underlying noble metal layer (4).
    Type: Application
    Filed: April 1, 2002
    Publication date: January 16, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventor: Keiichiro Kashihara
  • Patent number: 6487064
    Abstract: A bypass circuit includes a planar electrode layer which is mounted between a pair of dielectric layers. The electrode layer generally is centered inwardly with respect to the dielectric layers leaving an outward margin of dielectric material. One of the dielectric layers has two spaced apart contact members, each having a different polarity from the other. A resistive layer is centered on the other dielectric layer. The contact members extend onto end portions of the dielectric layers and electrically connect to opposite ends of the resistive layer. The electrode layer is isolated from electrical contact with any conductor and is buried within the dielectric layers. The electrode layer, in combination with the dielectric layer on which the contact members are mounted and the contact members, allow development of a selected value of capacitance between the contact members.
    Type: Grant
    Filed: September 10, 2001
    Date of Patent: November 26, 2002
    Assignee: American Technical Ceramics Corporation
    Inventor: Richard V. Monsorno
  • Patent number: 6473950
    Abstract: A manufacturing method for multi-layered electronic parts which is characterized in that from a roll of a polyethylene microporous sheet which has an electrode layer forming agent formed on its surface, contains 45 to 80 volume percent of inorganic filler, and has a thickness of 25 &mgr;m or less, tensile strengths of 3 kg/mm2 or more in the longitudinal direction and of 1 kg/mm2 or more in the transverse direction, and an elongation of 30% or less in the MD direction, layered electronic parts are formed via (a) a step of unwinding the sheet, (b) a step of cutting the sheet in a predetermined length, (c) a step of stacking the cut sheets, and (d) a step of cutting the layered structure and efficient production is made possible.
    Type: Grant
    Filed: December 21, 1998
    Date of Patent: November 5, 2002
    Assignee: Teijin Limited
    Inventor: Shiro Kumakawa
  • Patent number: 6470545
    Abstract: Embedded green multi-layer ceramic capacitors in low-temperature co-fired ceramic (LTCC) substrates are provided. A first set of electrodes is printed on a ceramic tape. A first dielectric layer is placed over the first set of electrodes and the ceramic tape. A second set of electrodes is printed on the first dielectric layer. A second dielectric layer is placed over the second set of electrodes and the first dielectric layer. A third set of electrodes is printed on the second dielectric layer. The sheet is then cut to form separate green multi-layer ceramic capacitor chips. The green multi-layer ceramic capacitor chips are then placed in a cavity formed by ceramic tape.
    Type: Grant
    Filed: August 3, 2000
    Date of Patent: October 29, 2002
    Assignee: National Semiconductor Corporation
    Inventor: Shaul Branchevsky
  • Patent number: 6442813
    Abstract: A monolithic ceramic capacitor includes a plurality of dielectric ceramic layers, a plurality of inner electrodes formed between the dielectric ceramic layers in such a manner that one end of each inner electrode is exposed out of either end of the dielectric ceramic layers, and outer electrodes electrically connected with the exposed inner electrodes; in which the inner electrodes each are made of a base metal, and Si oxide layers or layers comprising an Si oxide and at lest one component that constitutes said dielectric ceramic layers and said inner electrodes are formed adjacent to the inner electrodes. The capacitor has excellent thermal impact resistance and wet load resistance characteristics. A producing method includes firing a green sheet laminate including a metal inner electrode at an oxygen partial pressure of about said equilibrium oxygen partial pressure of the metal to the metal oxide.
    Type: Grant
    Filed: April 9, 1998
    Date of Patent: September 3, 2002
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Norihiko Sakamoto, Harunobu Sano, Takaharu Miyazaki
  • Publication number: 20020108221
    Abstract: Flat electrolytic capacitors particularly for use in implantable medical devices having stacked cathode and anode layers particular electrical connections of the capacitor anode and cathode layers with a capacitor connector assembly. Anode terminal means extend through the capacitor case side wall for electrically connecting a plurality of the anode tabs to one another and providing an anode connection terminal at the exterior of the case that is electrically insulated from the case. A cathode terminal extends through or to an encapsulation area of the capacitor case side wall via a cathode terminal passageway for electrically connecting a plurality of the cathode tabs to one another and providing a cathode connection terminal at the exterior of the case. The connector assembly is electrically attached to the anode connection terminal for making electrical connection with the anode tabs and to the cathode connection terminal for making electrical connection with the cathode tabs.
    Type: Application
    Filed: December 18, 2001
    Publication date: August 15, 2002
    Applicant: Medtronic, Inc.
    Inventors: Thomas P. Miltich, Paul A. Pignato, Mark D. Breyen, Kurt J. Casby, William L. Johnson
  • Publication number: 20020095756
    Abstract: A method for manufacturing a capacitor using a tantalum oxy nitride (TaON) film in a process for a semiconductor device. More particularly, a method for manufacturing a capacitor which reduces a number of steps and thus increases yield by in-situ performing P-doping after forming a MPS (Metastable Poly Silicon) on a lower electrode and forming a nitride film before forming a tantalum oxy nitride film to prevent the concentration of phosphor contained in the lower electrode from being reduced by removing the phosphor on the surface of the lower electrode in a cleaning process between the above two steps, for thereby increasing the capacitance of the capacitor.
    Type: Application
    Filed: December 12, 2001
    Publication date: July 25, 2002
    Inventors: Dong-su Park, Kwang-seok Jeon
  • Patent number: 6370014
    Abstract: A method for manufacturing a highly reliable laminated ceramic capacitor that hardly causes an interlayer peeling phenomenon such as delamination and hardly suffers invasion of a plating solution during plating or invasion of water and moisture during use, comprising the steps of: preparing a non-fired ceramic green chip comprising at least one layer of internal electrode containing a metallic compound comprising a metal that forms a solid solution with the internal electrode, or reacts with the internal electrode to form a compound, or segregates on the internal electrode or at the periphery of the internal electrode; firing the green chip to allow the metal in the metallic compound to form a solid solution with the internal electrode, to react with the internal electrode to form a compound, or to segregate the metallic compound on the internal electrode or at the periphery of the metallic compound, thereby enhancing the adhesion between the internal electrode and the ceramic; and forming external electrodes
    Type: Grant
    Filed: August 18, 2000
    Date of Patent: April 9, 2002
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Yasunobu Yoneda
  • Patent number: 6338284
    Abstract: Structures and methods are disclosed in conjunction with the fabrication of electrical lead transfer feedthroughs with respect to a sealed cavity. In some applications such as capacitive pressure sensing, the cavity may include an outer wall, in which case the electrically insulating barrier is preferably U-shaped, with the ends of the U terminating at the outer wall. The feedthrough section may alternatively take the form of an island of conductive material surrounded by the electrically insulating barrier, thus assuming an O-shape. The cavity may be evacuated or filled with specific gases at specific pressures. As such, the invention finds application in the packaging (vacuum or controlled environment) and production of a variety of transducers including but not limited to pressure sensors, flow sensors, optical devices (e.g., infrared detectors, ccd camera, and flat-panel displays) and resonating devices, such as gyroscopes, accelerometers, yaw sensors, telecommunication devices, etc.
    Type: Grant
    Filed: February 12, 1999
    Date of Patent: January 15, 2002
    Assignee: Integrated Sensing Systems (ISSYS) Inc.
    Inventors: Nader Najafi, Yafan Zhang, Terry Hull
  • Patent number: 6331325
    Abstract: A semiconductor device and process for making the same are disclosed which incorporate boron, which has been found to be substantially insoluble in BST, into a BST dielectric film 24. Dielectric film 24 is preferably disposed between electrodes 18 and 26 (which preferably have a Pt layer contacting the BST) to form a capacitive structure with a relatively high dielectric constant and relatively low leakage current. Boron included in a BST precursor may be used to form boron oxide in a second phase 30, which is distributed in boundary regions between BST crystals 28 in film 24. It is believed that the inclusion of boron allows for BST grains of a desired size to be formed at lower temperature, and also reduces the leakage current of the capacitive structure.
    Type: Grant
    Filed: September 30, 1994
    Date of Patent: December 18, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Bernard M. Kulwicki, Robert Tsu
  • Patent number: 6330146
    Abstract: An ionizing bar assembly having a plastic housing with two individual ionizing electrode modules disposed on opposite sides. The ionizing electrode modules each include a plurality of printed circuit boards having signal traces thereon with ionizing electrodes or pins extending therefrom. The printed circuit boards are electrically coupled together by conductive rods or tubing positioned adjacent to the traces on the boards and soldered at various positions along the traces. The ionizing electrode modules are placed at opposing angles and are offset laterally from each other in such a way that the ionizing electrodes or pins extending from one module are located between the ionizing electrodes or pins extending from the opposite module, with the tips of each aligned along a common central linear axis.
    Type: Grant
    Filed: March 6, 2000
    Date of Patent: December 11, 2001
    Assignee: Ion Systems, Inc.
    Inventors: Mark Blitshteyn, Lisle R. Knight, Jr., Petr Gefter, Scott J. S. Gehlke, Ira J. Pitel, Sean J. Quigley, Michael J. Leonard, John K. O'Reilly
  • Patent number: 6320738
    Abstract: A monolithic ceramic electronic component has a ceramic element including a plurality of ceramic layers and a plurality of internal electrode layers. Each internal electrode layer is disposed between two adjacent ceramic layers. The roughness of the interface between each internal electrode layer and each ceramic layer is about 200 nm or less, and the incidence of pores in the ceramic layer is about 1% or less by area at a polished cut cross-section. The monolithic ceramic electronic component can be a monolithic ceramic capacitor, a monolithic ceramic varistor, a monolithic ceramic piezoelectric component or a monolithic substrate.
    Type: Grant
    Filed: October 30, 2000
    Date of Patent: November 20, 2001
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Tsuyoshi Yamana, Takaharu Miyazaki
  • Patent number: 6319542
    Abstract: A preferred embodiment of this invention comprises a conductive lightly donor doped perovskite layer (e.g. lightly La doped BST 34), and a high-dielectric-constant material layer (e.g. undoped BST 36) overlaying the conductive lightly donor doped perovskite layer. The conductive lightly donor doped perovskite layer provides a substantially chemically and structurally stable electrical connection to the high-dielectric-constant material layer. A lightly donor doped perovskite generally has much less resistance than undoped, acceptor doped, or heavily donor doped HDC materials. The amount of donor doping to make the material conductive (or resistive) is normally dependent on the process conditions (e.g. temperature, atmosphere, grain size, film thickness and composition). This resistivity may be further decreased if the perovskite is exposed to reducing conditions.
    Type: Grant
    Filed: May 26, 1995
    Date of Patent: November 20, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Scott R. Summerfelt, Howard R. Beratan, Bruce Gnade
  • Patent number: 6310757
    Abstract: There are provided an electronic component having external electrodes and a method for manufacturing thereof for which treatment of the wastewater is not needed and has electrolytically plated layers which are substantially plated only on the conductive layers but not on the ceramic surfaces. In the method for manufacturing the electronic component, an activation treatment is performed in which palladium is deposited on a conductive layer on the electronic component, and then electrolytic Ni plating and electrolytic solder plating are performed sequentially.
    Type: Grant
    Filed: July 21, 2000
    Date of Patent: October 30, 2001
    Assignee: Taiyo Chemical Industry Co., Ltd.
    Inventors: Kiyoshi Tuzuki, Sachiko Kawamura
  • Patent number: 6308398
    Abstract: A method is disclosed for simultaneously producing a plurality of capacitive electroacoustic transducers. The method comprises forming a plurality of electrically insulative substrates by cutting circular slots to an insulating wafer. Each slot is interrupted by at least two tabs connecting a circular area with the remainder of the wafer. The conductive diaphragms are supported on diaphragm mounting rings disposed upon the substrate, spaced from a first electrode. The mounting rings space the diaphragm from the electrode to define a capacitor operative to convert electrical and acoustical signals.
    Type: Grant
    Filed: December 10, 1999
    Date of Patent: October 30, 2001
    Assignee: Northrop Grumman Corporation
    Inventor: Bob Ray Beavers
  • Publication number: 20010020320
    Abstract: A method to construct a capacitive transducer comprising the steps of forming over and in a planar surface of a substrate at least one rigid electrode of a variable-area capacitor electrically connected to a location on said substrate reserved for electrode attachment; providing a cooperating flexible electrode with a dielectric layer; and bonding said flexible electrode to said substrate in a surface region surrounding said rigid electrode.
    Type: Application
    Filed: April 13, 2001
    Publication date: September 13, 2001
    Inventors: Robert B. McIntosh, Philip E. Mauger, Steven R. Patterson
  • Patent number: 6270835
    Abstract: Thin layer capacitors are formed from a first flexible metal layer, a dielectric layer between about 0.03 and about 2 microns deposited thereon, and a second flexible metal layer deposited on the dielectric layer. The first flexible metal layer may either be a metal foil, such as a copper, aluminum, or nickel foil, or a metal layer deposited on a polymeric support sheet. Depositions of the layers is by or is facilitate by combustion chemical vapor deposition or controlled atmosphere chemical vapor deposition.
    Type: Grant
    Filed: October 7, 1999
    Date of Patent: August 7, 2001
    Assignee: MicroCoating Technologies, Inc.
    Inventors: Andrew T. Hunt, John S. Flanagan, George A. Neuman
  • Patent number: 6256850
    Abstract: A method is provided for producing a capacitor to be embedded in an electronic circuit package comprising the steps of selecting a first conductor foil, selecting a dielectric material, coating the dielectric material on at least one side of the first conductor foil, and layering the coated foil with a second conductor foil on top of the coating of dielectric material. Also claimed is an electronic circuit package incorporating at least one embedded capacitor manufactured in accordance with the present invention.
    Type: Grant
    Filed: February 11, 1998
    Date of Patent: July 10, 2001
    Assignee: International Business Machines Corporation
    Inventors: John M. Lauffer, Konstantinos Papathomas
  • Patent number: 6225133
    Abstract: After an interlayer insulating film is deposited on a silicon substrate, a contact hole or contact holes is or are formed at a desired position(s) and, then, after a polysilicon layer is deposited and the contact hole(s) is (are) embedded, the surface of the polysilicon layer is flattened by chemical and mechanical polishing using at least one of piperazine or colloidal silica slurry, and a barrier metal film 4 and a highly dielectric thin film 5 are deposited and processed to a desired size. Finally, an Al/TiN film 6 adapted for the upper electrode is formed. The leak current of the thin film capacitor which is obtained according to this method can be greatly reduced.
    Type: Grant
    Filed: September 1, 1994
    Date of Patent: May 1, 2001
    Assignee: NEC Corporation
    Inventors: Shintaro Yamamichi, Hirohito Watanabe, Yoichi Miyasaka
  • Patent number: 6170138
    Abstract: A capacitor is described, in particular a vacuum capacitor, comprising two electrodes (1, 1′), at least one insulator (5), and means for fastening (4, 4′). A process is proposed according to which the two electrodes (1, 1′) are each produced as one piece of an electrode material through a cold-flow extrusion process. The electrodes so produced are distinguished by a high surface quality. The result of this, in the capacitors produced from such electrodes, is high quality-factors, low temperature coefficients, a high current-carrying capacity, and an excellent dielectric strength, as well as a compact structure with a simultaneous reduction in the number of components required. Capacitors of this type, in particular vacuum capacitors, find application in HF technology for fixed and variable capacitance values.
    Type: Grant
    Filed: March 6, 1998
    Date of Patent: January 9, 2001
    Assignee: Comet Technik AG
    Inventors: J. Andrea Von Planta, Bernhard Hug
  • Patent number: 6171644
    Abstract: The present invention aims to present an electronic component which is free from the fear of sneaking-in of water etc. from the edge of electrode, by covering the electrode edge with resin. For the purpose, external electrodes (3) are formed at both ends of varistor (1) comprised of ceramic sheet (1a) and internal electrode (2) laminated alternately, and then, a within-the-surface insulation layer (30) is formed by covering the porous surface inside the varistor (1), or filling the Porosity, with silicone resin, and an outside-the-surface insulation layer (31) is formed covering the surface of varistor (1) and the edge of external electrode (3).
    Type: Grant
    Filed: April 22, 1999
    Date of Patent: January 9, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Riho Jinno, Kazuyuki Nakamura