Electric Condenser Making Patents (Class 29/25.41)
  • Patent number: 7818855
    Abstract: Methods of making thin film capacitors formed on foil by forming onto a thin film dielectric in a single deposition event an integrally complete top electrode having a minimum thickness of at least 1 micron.
    Type: Grant
    Filed: October 8, 2007
    Date of Patent: October 26, 2010
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: William Borland, Cengiz Ahmet Palanduz, Olga L. Renovales
  • Patent number: 7810234
    Abstract: An apparatus, and a method for forming, a split thin film capacitor for providing multiple power and reference supply voltage levels to electrical devices such as integrated circuits, may be useful in space restricted applications, and in applications that require very close electrical connections between the power consumer and the power supply. An example of both a space restricted application and a close coupling application may be an integrated circuit (IC) such as a microprocessor. The capacitor supplying and moderating power to the microprocessor needs to be closely coupled in order to respond to instantaneous power demands that may be found in high clock rate microprocessors, and the space inside a microprocessor package is very restricted.
    Type: Grant
    Filed: April 10, 2007
    Date of Patent: October 12, 2010
    Assignee: Intel Corporation
    Inventors: Cengiz A. Palanduz, Larry E. Mosley
  • Publication number: 20100254069
    Abstract: Some embodiments are related to a mesh capacitor, which improves the SER FIT rate. In an embodiment, the capacitor is connected between an input and an output of a latch in a flip-flop, making the flip-flop harder to flip due to radiation (e.g., from neutrons and/or alpha particles). In some embodiments, the capacitor is built directly vertically on top of the flip-flop, saving chip layout areas.
    Type: Application
    Filed: March 31, 2010
    Publication date: October 7, 2010
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ching-Hao SHAW, Subramani KENGERI
  • Patent number: 7805821
    Abstract: A method for manufacturing a capacitance sensor comprises the steps of (a) depositing a film to be a diaphragm forming a moving electrode, (b) heating the film to be the diaphragm to a first temperature, and (c) depositing a film to be a plate forming a fixed electrode opposing to the moving electrode. Stresses of the diaphragm and the plate of the capacitance sensor are optimized.
    Type: Grant
    Filed: August 20, 2007
    Date of Patent: October 5, 2010
    Assignee: Yamaha Corporation
    Inventor: Tamito Suzuki
  • Patent number: 7803421
    Abstract: An element forming an electronic component has a first face and a second face facing each other, and a third face adjacent to each of the first face and the second face. A method of forming an external electrode of the electronic component involves a pre-formation step, first to third formation steps, and an electrode formation step. The pre-formation step is to apply a conductive paste onto the third face and to evaporate at least a part of a liquid contained in the applied conductive paste, to form a precoat portion expected to become a part of a third electrode portion. The first formation step is to apply the conductive paste from a direction opposite to the first face, onto the first face to form a first electrode portion. The second formation step is to apply the conductive paste from a direction opposite to the second face, onto the second face to form a second electrode portion.
    Type: Grant
    Filed: December 11, 2006
    Date of Patent: September 28, 2010
    Assignee: TDK Corporation
    Inventors: Ko Onodera, Satoshi Kurimoto, Yoji Tozawa, Shirou Ootsuki
  • Patent number: 7793396
    Abstract: A manufacturing method includes forming a dielectric part by oxidizing an entire first surface of a valve metal sheet; forming a through hole in the valve metal sheet in which the dielectric part is formed; applying an adhesive conductive material to a surface of a substrate; attaching the valve metal sheet in which the through hole is formed, to the substrate so that the first surface contacts the conductive material on the substrate surface; forming a conductive layer by curing the conductive material; forming a protection layer which covers a second surface of the valve metal sheet which is opposite to the first surface of the valve metal sheet; forming openings in the protection layer, so that the conductive layer in the through hole and the second surface of the valve metal sheet are partially exposed from the openings; and filling up the openings in the protection layer with another conductive material to form electrode terminals.
    Type: Grant
    Filed: September 19, 2007
    Date of Patent: September 14, 2010
    Assignee: Fujitsu Limited
    Inventors: Takeshi Shioga, Kazuaki Kurihara
  • Publication number: 20100219844
    Abstract: A foreign objection detection sensor has a lengthy sensor part having a sensor electrode having a first sensor electrode which detects a proximity of a foreign object and a second sensor electrode which detects a contact of the foreign object, a sensor terminal part provided at one end of the sensor part, a leading wire pulled out from the sensor terminal part, the leading wire being electrically connected to the sensor electrode at the sensor terminal part to provide a proximity detecting function for detecting the proximity of the foreign object to the sensor part and a contact detecting function for detecting the contact of the foreign object to the sensor part. The sensor terminal part has a support member which supports a detection circuit unit electrically connected to the sensor electrode to carry out the proximity detecting function and the contact detecting function together with the sensor electrode. The detection circuit unit is disposed in the support member.
    Type: Application
    Filed: February 24, 2010
    Publication date: September 2, 2010
    Applicants: ASMO CO., LTD., HITACHI CABLE, LTD.
    Inventors: Ryousuke Sakamaki, Akihiro Tanba, Takashi Aoyama, Akio Hattori, Teruji Sato, Tatsuya Ohtaka
  • Patent number: 7771495
    Abstract: A method for manufacturing an electric double layer capacitor comprising polarizable electrodes formed from a carbon material having graphite-like microcrystalline carbon, wherein said carbon material is stored for a predetermined period of time while holding said carbon material in contact with an electrolytic solution, and thereafter, at a temperature higher than room temperature, said capacitor is charged at least once with an end-of-charge voltage higher than an expected operating voltage of said capacitor, while applying to said electrodes, at the start of said charging, a pressure that is necessary to keep said carbon material from expanding in a thickness direction thereof during said charging.
    Type: Grant
    Filed: March 17, 2006
    Date of Patent: August 10, 2010
    Assignee: Japan Gore-Tex Inc.
    Inventors: Kotaro Kobayashi, Kazuhiro Minami
  • Patent number: 7771780
    Abstract: A method of producing a piezoelectric actuator includes the steps of: forming a first electrode layer on a substrate by jetting an aerosol containing particles of a conductive material and ceramic particles onto the substrate to make the particles adhere to the substrate; forming a piezoelectric layer on the first electrode layer by jetting an aerosol containing particles of a piezoelectric material onto the first electrode layer to make the particles adhere to the electrode; performing an annealing treatment for the piezoelectric layer; and forming, on the piezoelectric layer, a second electrode layer paring with the first electrode layer. Accordingly, the adherence between the substrate and the first electrode layer and between the first electrode layer and the piezoelectric layer are improved, thereby hardly causing exfoliation of the layers due to differences in coefficients of thermal expansion between the layers.
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: August 10, 2010
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventors: Motohiro Yasui, Jun Akedo
  • Patent number: 7765661
    Abstract: A method for manufacturing a ceramic electronic component having excellent solderability is provided. In this method, the elution of barium from the ceramic electronic component and the adhesion of ceramic electronic components in tin plating are reduced. The method for manufacturing a ceramic electronic component includes the steps of providing an electronic component of barium-containing ceramic and forming an electrode on the outer surface of the electronic component, the electrode being electroplated with tin. In this method, a plating bath used in the tin plating has a tin ion concentration A in the range of 0.03 to 0.51 mol/L, a sulfate ion concentration B in the range of 0.005 to 0.31 mol/L, a molar ratio B/A of less than one, and a pH in the range of 6.1 to 10.5.
    Type: Grant
    Filed: February 1, 2006
    Date of Patent: August 3, 2010
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Akihiro Motoki, Makoto Ogawa, Seiichi Matsumoto, Yoshihiko Takano, Tatsuo Kunishi
  • Publication number: 20100182017
    Abstract: A drive-by-wire non-contact capacitive throttle control apparatus and method of forming the same. A capacitive position sensor is provided, which includes a stationary electrode and a rotatable electrode. The rotatable electrode can be attached to a throttle lever such that the rotatable electrode rotates as the throttle lever rotates. The capacitance between the rotatable electrode and the stationary electrode varies with the position of the throttle lever. The position of the throttle lever can be measured by measuring the capacitance between the electrodes and a signal can be generated based on the sensed position. The signal can be electrically transmitted to an ECU (Electronic Control Unit) utilizing one or more electrical wires. The signal can be sent in the form of a varying voltage, which in turn controls the throttle of a vehicle.
    Type: Application
    Filed: January 21, 2009
    Publication date: July 22, 2010
    Inventors: Gangi Rajula Reddy, Anand Chandran, Al Cable, Richard Alan Holzmacher, Ravindra Gudi, Deepak Murali, Shakil Moonamkandy
  • Publication number: 20100177458
    Abstract: A filtered feedthrough assembly includes a capacitor comprising a top portion, a bottom portion, an outer diameter portion and an inner diameter portion. The inner diameter portion defines at least one aperture extending from the top portion to the bottom portion. An conductive pad of conductive material is applied to the top portion around the at least one aperture. A feedthrough pin extends through each of the apertures and is soldered to the inner diameter portion of the capacitor by application of a solder preform upon the conductive pad of conductive material.
    Type: Application
    Filed: January 12, 2009
    Publication date: July 15, 2010
    Applicant: Medtronic, Inc.
    Inventor: Rajesh V. Iyer
  • Patent number: 7736397
    Abstract: A method for manufacturing a capacitor embedded in a PCB includes: preparing a copper clad lamination (CCL) substrate having a reinforcement member and copper foils formed on both surfaces of the reinforcement member; planarizing surfaces of the copper foils of the CCL substrate; forming a dielectric layer on the planarized surface of the copper foils; and forming a top electrode on the dielectric layer.
    Type: Grant
    Filed: April 5, 2007
    Date of Patent: June 15, 2010
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Seung Eun Lee, Yul Kyo Chung, Hyung Dong Kang, Hyun Ju Jin
  • Patent number: 7735206
    Abstract: A method for forming a capacitor dielectric includes depositing a zirconium oxide layer, performing a post-treatment on the zirconium oxide layer such that the zirconium oxide layer has a tetragonal phase, and depositing a tantalum oxide layer over the zirconium oxide layer such that the tantalum oxide layer has a tetragonal phase.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: June 15, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jong-Bum Park
  • Publication number: 20100142115
    Abstract: Provided are a buried capacitor, a method of manufacturing the same, and a method of changing a capacitance thereof. The buried capacitor includes an upper electrode including at least one first hole, a lower electrode including at least one second hole, and a dielectric interposed between the upper electrode and the lower electrode.
    Type: Application
    Filed: July 8, 2009
    Publication date: June 10, 2010
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Hyun-Cheol Bae, Kwang-Seong Choi, Ju Yeon Hong, Jong Tae Moon, Yong il Jun
  • Publication number: 20100136414
    Abstract: An apparatus for storing energy may include: a plurality of nanowire cells electrically connected to each other; and a storage for storing electrical energy generated from the nanowire cells. Each of the plurality of nanowire cells may include: first and second electrodes disposed at an interval; and a nanowire, which is disposed between the first and the second electrodes and made of a piezoelectric material. The plurality of nanowire cells may be electrically connected, so that voltage or current may be increased. Therefore, wireless recharging of the storage connected to the nanowire cells with electrical energy may be enabled.
    Type: Application
    Filed: March 20, 2009
    Publication date: June 3, 2010
    Applicants: SAMSUNG ELECTRONICS CO., LTD., KUMOH NATIONAL INSTITUTE OF TECHNOLOGY
    Inventors: Dukhyun Choi, Sang Yoon Lee, Jaeyoung Choi, Hansu Kim, Sangwoo Kim
  • Patent number: 7729811
    Abstract: The use of electrical energy storage unit (EESU) technology can provide power averaging for utility grids. Such EESUs can also be used to construct a system capable of storing electrical energy over specified periods (e.g., 24 hours) to provide peak power to homes, commercial sites, and industrial sites. By charging these power averaging units during non-peak times and then delivering the energy during peak-demands times, more efficient utilization of the present utility-grid power-generating plants and the already existing power transmission lines will be accomplished. These systems also have the capability of isolating users from utility-grid power failures, transients, and AC noise.
    Type: Grant
    Filed: August 4, 2006
    Date of Patent: June 1, 2010
    Assignee: EEStor, Inc.
    Inventors: Richard D. Weir, Carl W. Nelson
  • Publication number: 20100107391
    Abstract: A micro-electromechanical device includes a semiconductor substrate, in which a first microstructure and a second microstructure of reference are integrated. The first microstructure and the second microstructure are arranged in the substrate so as to undergo equal strains as a result of thermal expansions of the substrate. Furthermore, the first microstructure is provided with movable parts and fixed parts with respect to the substrate, while the second microstructure has a shape that is substantially symmetrical to the first microstructure but is fixed with respect to the substrate. By subtracting the changes in electrical characteristics of the second microstructure from those of the first, variations in electrical characteristics of the first microstructure caused by changes in thermal expansion or contraction can be compensated for.
    Type: Application
    Filed: January 7, 2010
    Publication date: May 6, 2010
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Ernesto Lasalandra, Angelo Merassi, Sarah Zerbini
  • Patent number: 7707701
    Abstract: A method for manufacturing a piezoelectric element includes the steps of forming a first electrode above a substrate, forming above the first electrode a piezoelectric layer composed of a piezoelectric material having a perovskite structure, and forming a second electrode above the piezoelectric layer, wherein the step of forming the first electrode includes forming a lanthanum nickelate layer that is oriented to a cubic (100) by a sputter method, and a ratio of nickel to lanthanum (Ni/La) in a target used for the sputter method is greater than 1 but smaller than 1.5.
    Type: Grant
    Filed: February 20, 2006
    Date of Patent: May 4, 2010
    Assignee: Seiko Epson Corporation
    Inventors: Setsuya Iwashita, Koji Ohashi, Takamitsu Higuchi
  • Publication number: 20100099232
    Abstract: Some embodiments include methods of forming capacitors. Storage nodes are formed within a material. The storage nodes have sidewalls along the material. Some of the material is removed to expose portions of the sidewalls. The exposed portions of the sidewalls are coated with a substance that isn't wetted by water. Additional material is removed to expose uncoated regions of the sidewalls. The substance is removed, and then capacitor dielectric material is formed along the sidewalls of the storage nodes. Capacitor electrode material is then formed over the capacitor dielectric material. Some embodiments include methods of utilizing a silicon dioxide-containing masking structure in which the silicon dioxide of the masking structure is coated with a substance that isn't wetted by water.
    Type: Application
    Filed: October 16, 2008
    Publication date: April 22, 2010
    Inventors: Niraj Rana, Nishant Sinha, Prashant Raghu, Jim Hofmann, Neil Greeley
  • Patent number: 7698793
    Abstract: A method of producing an electret condenser microphone capable of reflow mounting includes a first step of providing a backplate substrate having a backplate; a second step of providing an adhesive-backed fluorine-containing resin film formed by stacking an adhesive on a film-shaped fluorine-containing resin material having a surface treated by wet or dry chemical etching; a third step of stacking the adhesive-backed fluorine-containing resin sheet on the backplate of the backplate substrate with the adhesive interposed therebetween; a fourth step of setting the adhesive to firmly secure the fluorine-containing resin material to the backplate of the backplate substrate; and a fifth step of implanting electric charges into the fluorine-containing resin film firmly secured onto the backplate.
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: April 20, 2010
    Assignee: Citizen Electronics Co., Ltd.
    Inventor: Yuki Tsuchiya
  • Patent number: 7694397
    Abstract: A mirror for a piezoelectric resonator consisting of alternately arranged layers of high and low acoustic impedance is manufactured by at first producing a first layer on which a second layer is produced, so that the second layer partially covers the first layer. Then, a planarization layer is applied on the first layer and on the second layer. Subsequently, a portion of the second layer is exposed by structuring the planarization layer, wherein the portion is associated with an active region of the piezoelectric resonator. Finally, the resulting structure is planarized by removing the portions of the planarization layer remaining outside the portion.
    Type: Grant
    Filed: February 24, 2006
    Date of Patent: April 13, 2010
    Assignee: Avago Technologies Wireless IP (Singapore) Pte. Ltd.
    Inventors: Robert Thalhammer, Stephan Marksteiner, Gernot Fattinger
  • Patent number: 7685687
    Abstract: Methods of making metal/dielectric/metal structures include casting copper slurry onto a fugitive substrate to form the first electrode and subsequently casting dielectric and copper slurries onto the first electrode, removing the fugitive substrate and co-firing the structure, wherein the dielectric comprises glass in an amount that is less than 20% by weight of the total inorganic composition and the dielectric achieves substantially complete densification. Alternatively, a metal tape and a dielectric tape, comprising glass in the above amount, may be formed and laminated together to form a metal/dielectric/metal green tape structure, which is co-fired, such that the structure achieves substantially complete densification.
    Type: Grant
    Filed: January 22, 2007
    Date of Patent: March 30, 2010
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: William Borland, Lorri Drozdyk
  • Publication number: 20100073319
    Abstract: A capacitive sensor may include a flex circuit, a substrate facing the flex circuit, and conductive electrodes configured to sense an input applied to the substrate. At least one of the conductive electrodes is associated with a surface of the substrate and an at least one of the electrodes is associated with a surface of the flex circuit.
    Type: Application
    Filed: September 25, 2008
    Publication date: March 25, 2010
    Applicant: Apple Inc.
    Inventors: Benjamin Lyon, Joseph Fisher, Lakshman Rathnam
  • Patent number: 7676914
    Abstract: In an exemplary embodiment, a method for a magnetic sensor includes forming a first conductive layer over a substrate containing circuitry, forming a dielectric layer over the first conductive layer, forming a second conductive layer over the dielectric layer such that the first conductive layer, the dielectric layer, and the second conductive layer form a first capacitor, and providing first and second terminals, wherein the first terminal is coupled to the first conductive layer and the second terminal is coupled to the second conductive layer.
    Type: Grant
    Filed: October 23, 2007
    Date of Patent: March 16, 2010
    Assignee: Allegro Microsystems, Inc.
    Inventor: William P. Taylor
  • Patent number: 7653973
    Abstract: A production method of a multilayer electronic device, comprising the steps of forming an electrode layer 12a on a first support sheet 20; forming a green sheet 10a on a surface of the electrode layer 12a to obtain a green sheet 10a having an electrode layer 12a; stacking the green sheets 10a, each having the electrode layer 12a, to form a green chip; and firing the green chip: wherein before stacking the green sheet 10a having the electrode layer 12a, an adhesive layer 28 is formed on a surface on the opposite side of the electrode layer side of the green sheet 10a having the electrode layer 12a; and the green sheet 10a having the electrode layer 12a formed thereon is stacked via the adhesive layer 28.
    Type: Grant
    Filed: June 24, 2005
    Date of Patent: February 2, 2010
    Assignee: TDK Corporation
    Inventor: Shigeki Sato
  • Publication number: 20100022045
    Abstract: Sensor platforms and methods of making them are described. A platform having a non-horizontally oriented sensor element comprising one or more nanostructures such as nanotubes is described. Under certain embodiments, a sensor element has or is made to have an affinity for an analyte. Under certain embodiments, such a sensor element comprises one or more pristine nanotubes. Under certain embodiments, the sensor element comprises derivatized or functionalized nanotubes. Under certain embodiments, a sensor is made by providing a support structure; providing one or more nanotubes on the structure to provide material for a sensor element; and providing circuitry to electrically sense the sensor element's electrical characterization. Under certain embodiments, the sensor element comprises pre-derivatized or pre-functionalized nanotubes. Under other embodiments, sensor material is derivatized or functionalized after provision on the structure or after patterning.
    Type: Application
    Filed: May 20, 2009
    Publication date: January 28, 2010
    Applicant: Nantero, Inc.
    Inventors: BRENT M. SEGAL, THOMAS RUECKES, BERNHARD VOGELI, DARREN K. BROCK, VENKATACHALAM C. JAIPRAKASH, CLAUDE L. BERTIN
  • Patent number: 7644479
    Abstract: A lower electrode 3 including a low-temperature melting layer 3A and a high-temperature melting layer 3B having mutually different melting-start temperatures is provided between a vibration plate 2 and a piezoelectric layer 4. In a calcination step of calcinating the lower electrode 3, the calcination is performed at a low temperature at which only the low-temperature melting layer 3A melts, and in an annealing-process step of the piezoelectric layer 4, the annealing process is performed at a high temperature at which the high-temperature melting layer 3B melts. At this time, in the calcination step, the melting of platinum nano-particles occurs in the low-temperature melting layer 3A, rendering the adhesion and diffusion-preventive effect. Further, in the annealing step, in the high-temperature melting layer 3B, platinum particles are melted, rendering the adhesion and diffusion-preventive effect.
    Type: Grant
    Filed: February 21, 2006
    Date of Patent: January 12, 2010
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventor: Motohiro Yasui
  • Patent number: 7641933
    Abstract: A single layer capacitive device including a portion of pre-fired ceramic material and one or more terminations is formed with manufacturing steps that are easily modified to customize size and other aspects of such devices. The single layer devices may be utilized by themselves or selectively combined with MLCs to form integrated capacitor assemblies yielding many desirable performance characteristics in a monolithic assembly. An exemplary integrated capacitor assembly advantageously provides customized frequency response and capacitance in limited real estate. Predictable and generally constant or “flat” impedance versus frequency is afforded mainly by the properties of the single layer device, while higher capacitance is provided mainly from features of one or more associated MLCs. High structural integrity of exemplary integrated capacitor assemblies is achieved due to the disclosed attachment methods.
    Type: Grant
    Filed: June 5, 2006
    Date of Patent: January 5, 2010
    Assignee: AVX Corporation
    Inventors: Robert Purple, Marilynn Young, Larry Eisenberger
  • Patent number: 7636994
    Abstract: The present invention provides an electronic device with improved characteristics and a method of making the electronic device. In a method of making an electronic device (piezoelectric device) 74 according to the present invention, an outer edge R1 of a piezoelectric film 52A formed on an electrode film 46A of a laminate 60 is located inside an outer edge R2 of the electrode film 46A. For this reason, in removal of a monocrystalline Si substrate 14 from a multilayer board 61, where an etching solution permeates between polyimide 72 and laminate 60, the etching solution circumvents the electrode film 46A before it reaches the piezoelectric film 52A. Namely, a route A of the etching solution to the piezoelectric film 52A is significantly extended by the electrode film 46A. In the method of making the electronic device 74, therefore, the etching solution is less likely to reach the piezoelectric film 52A.
    Type: Grant
    Filed: February 24, 2006
    Date of Patent: December 29, 2009
    Assignee: TDK Corporation
    Inventors: Kenichi Tochi, Masahiro Miyazaki, Takao Noguchi, Hiroshi Yamazaki, Ken Unno, Hirofumi Sasaki
  • Publication number: 20090314531
    Abstract: The invention concerns a method of making multilayered constructions useful in forming capacitors and resistors, which may be used in the manufacture of printed circuit boards and microelectronic devices. According to the inventive method, a thermosetting polymer layer or layers are attached directly onto a heat resistant film layer, specifically on the side(s) of the heat resistant film to be attached to an electrically conductive layer having an electrical resistance material layer thereon. Attaching the adhesive to the heat resistant film rather than the electrically conductive layer streamlines the manufacturing process, particularly in the formation of the electrical resistance material layer onto the electrically conductive layer. This also results in better precision and uniformity of the multilayered construction.
    Type: Application
    Filed: August 26, 2009
    Publication date: December 24, 2009
    Inventors: JOHN A. ANDRESAKIS, Pranabes K. Pramanik
  • Publication number: 20090316329
    Abstract: A chip component having external electrodes that allow both connection by an interlayer connection conductor and connection by soldering and a component built-in module containing the chip component therein are produced and provided. A metal of electrode parts on at least one principal surface of the external electrodes at the ends of the chip component is different from a metal of electrode parts at the remaining portion of the external electrodes. With such a structure, both a metal suitable for connection to an interlayer connection conductor, such as a via hole conductor or a through hole conductor of the component built-in module and, a metal suitable for soldering can be used for the external electrodes. Thus, the component built-in module can be reduced in the height and size.
    Type: Application
    Filed: June 19, 2009
    Publication date: December 24, 2009
    Applicant: Murata Manufacturing Co., Ltd.
    Inventor: Masato Nomura
  • Publication number: 20090314105
    Abstract: Embodiments for a capacitive sensing apparatus with attenuated electrical interference across a plurality of routing traces are provided. One embodiment forms a first sensor electrode on a substrate. In addition, a first routing trace is formed on the substrate, the first routing trace coupled with the first sensor electrode. One embodiment additionally forms a second sensor electrode on the substrate. A second routing trace differing in length from the first routing trace is also formed on the substrate, the second routing trace coupled with the second sensor electrode. To attenuate electrical interference, the second routing trace is formed having an approximately equal RC time constant characteristic as the first routing trace.
    Type: Application
    Filed: June 24, 2008
    Publication date: December 24, 2009
    Inventors: Tracy Scott Dattalo, Bob Lee Mackey, Calvin Wang, JOHN J BRADY
  • Publication number: 20090296311
    Abstract: A ceramic electronic component has a ceramic element assembly, external electrodes, and metal terminals. The external electrodes are arranged on the surface of the ceramic element assembly. The external electrodes contain a sintered metal. The metal terminals are electrically connected to the external electrodes, respectively. The external electrode and the metal terminal are directly diffusion-bonded by diffusion of metal in the metal terminals into the external electrodes. The above arrangement provides a ceramic electronic component having highly reliable metal particle bonding and a method for manufacturing the same.
    Type: Application
    Filed: April 28, 2009
    Publication date: December 3, 2009
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Hideki OTSUKA, Kazuhiro YOSHIDA, Jun SONOYAMA, Yoji ITAGAKI, Akihiko NAKATA
  • Publication number: 20090288280
    Abstract: An EMI filtered terminal assembly includes at least one conductive terminal pin, a feedthrough capacitor, and a counter-bore associated with a passageway through the capacitor and the lead wire. Preferably, the feedthrough capacitor having counter-drilled holes on its top side is first bonded to a hermetic insulator. The counter-bore in the capacitor provides greater volume for the electro-mechanical attachment between the capacitor and the lead wire, permitting robotic dispensing of, for example, thermal-setting conductive adhesive.
    Type: Application
    Filed: May 7, 2009
    Publication date: November 26, 2009
    Applicant: GREATBATCH LTD.
    Inventors: Richard L. Brendel, Jason Woods, Jose Luis Lorente-Adame, Robert A. Stevenson, John Roberts, Buehl E. Truex
  • Publication number: 20090288279
    Abstract: Methods of fabricating an array capacitor are disclosed, in which via structures of the array capacitor have increased uniformity in their transverse areas. One method involves perforating a capacitor body to form first holes extending from a first surface and partially through the capacitor body. The capacitor body may be further perforated to form second holes extending from a second opposed surface of the capacitor body. The second holes are to connect to the first holes to provide through holes extending across a thickness of the capacitor body. An appropriate conductive material may then be filled in the through holes to form via structures with increased uniformity in their transverse areas.
    Type: Application
    Filed: May 21, 2008
    Publication date: November 26, 2009
    Inventor: Sriram Dattaguru
  • Patent number: 7621041
    Abstract: The present invention relates to methods of forming multilayer structures and the structures themselves. In one embodiment, a method of forming a multilayer structure comprises: providing a dielectric composition comprising paraelectric filler and polymer wherein the paraelectric filler has a dielectric constant between 50 and 150; applying the dielectric composition to a carrier film thus forming a multilayer film comprising a dielectric layer and carrier film layer; laminating the multilayer film to a circuitized core wherein the dielectric layer of the multilayer film is facing the circuitized core; and removing the carrier film layer from the dielectric layer prior to processing; applying a metallic layer to the dielectric layer wherein the circuitized core, dielectric layer and metallic layer form a planar capacitor; and processing the planar capacitor to form a multilayer structure.
    Type: Grant
    Filed: June 13, 2006
    Date of Patent: November 24, 2009
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: Sounak Banerji, G. Sidney Cox, Karl Hartmann Dietz
  • Publication number: 20090284895
    Abstract: An embodiment of the present invention provides a method, comprising manufacturing capacitors by creating a wafer using a substrate as a sacrificial carrier for the construction of said capacitor; and removing said sacrificial carrier wafer once said capacitor processing is complete.
    Type: Application
    Filed: May 14, 2008
    Publication date: November 19, 2009
    Inventors: Greg Mendolia, Bill Macropoulos
  • Publication number: 20090266172
    Abstract: Described herein is the sense element assembly for a capacitive pressure sensor and method for creating same that has increased sensitivity without additional size. The sense element assembly and method includes fabricating an off-centered elliptically shaped center electrode, at least one elliptical annular-like electrode around the center electrode, a ground electrode and a method for fusing the layers together to optimize sensitivity.
    Type: Application
    Filed: April 24, 2008
    Publication date: October 29, 2009
    Applicant: CUSTOM SENSORS & TECHNOLOGIES, INC.
    Inventors: Gary L. Casey, Marcos Nassar, Nhan Nguyen
  • Publication number: 20090268371
    Abstract: This invention relates to a capacitor electrode which includes porous layers made of a fiber and/or a whisker containing crystal tungsten oxides. The tungsten oxide fiber and/or whisker contain W18O49 as a main ingredient. The tungsten oxide fiber and/or whisker are made on a substrate. When manufacturing the capacitor electrode the substrate or its precursor is heated in vacuo or in an inactive containing a minute amount of oxygen, thereby completing the fiber and/or whisker.
    Type: Application
    Filed: September 14, 2007
    Publication date: October 29, 2009
    Inventors: Yoshiko Hishitani, Hidetoshi Nojiri, Didier Hamm, Masaharu Hatano, Makoto Uchiyama
  • Patent number: 7596842
    Abstract: The invention concerns a method of making multilayered constructions useful in forming capacitors and resistors, which may be used in the manufacture of printed circuit boards and microelectronic devices. According to the inventive method, a thermosetting polymer layer or layers are attached directly onto a heat resistant film layer, specifically on the side(s) of the heat resistant film to be attached to an electrically conductive layer having an electrical resistance material layer thereon. Attaching the adhesive to the heat resistant film rather than the electrically conductive layer streamlines the manufacturing process, particularly in the formation of the electrical resistance material layer onto the electrically conductive layer. This also results in better precision and uniformity of the multilayered construction.
    Type: Grant
    Filed: February 22, 2005
    Date of Patent: October 6, 2009
    Assignee: Oak-Mitsui Inc.
    Inventors: John A. Andresakis, Pranabes K. Pramanik
  • Publication number: 20090238954
    Abstract: Disclosed are a method of making a dielectric on a metal foil, and a method of making a large area capacitor that includes a dielectric on a metal foil. A dielectric precursor layer and the base metal foil are prefired at a prefiring temperature in the range of 350 to 650° C. in a moist atmosphere that also comprises a reducing gas. The prefired dielectric precursor layer and base metal foil are subsequently fired at a firing temperature in the range of 700 to 1200° C. in an atmosphere having an oxygen partial pressure of less than about 10?6 atmospheres to produce a dielectric. The area of the capacitor made according to the disclosed method may be greater than 10 mm2, and subdivided to create a multiple individual capacitor units that may be embedded in printed wiring boards. The dielectric is typically comprised of crystalline barium titanate or crystalline barium strontium titanate.
    Type: Application
    Filed: March 20, 2008
    Publication date: September 24, 2009
    Inventors: SEIGI SUH, Esther Kim, William Borland, Cengiz Ahmet Palanduz
  • Publication number: 20090230507
    Abstract: Structures and methods of forming an ideal MIM capacitor are disclosed. The single capacitor includes a first and a second metal structure overlying a substrate, a first dielectric material disposed between a first portion of the first metal structure and a first portion of the second metal structure. A second dielectric material is disposed between a second portion of the first metal structure and a second portion of the second metal structure. No first dielectric material is disposed between the second portion of the first and second metal structures, and no second dielectric material is disposed between the first portion of the first and second metal structures. The first and second dielectric material layers include materials with opposite coefficient of capacitance.
    Type: Application
    Filed: March 13, 2008
    Publication date: September 17, 2009
    Inventors: Philipp Riess, Armin Fischer
  • Publication number: 20090223706
    Abstract: A method for manufacturing a printed circuit board with a capacitor embedded therein which has a dielectric film using laser lift off, and a capacitor manufactured thereby. In the method, a dielectric film is formed on a transparent substrate and heat-treated. A first conductive layer is formed on the heat-treated dielectric film. A laser beam is irradiated onto a stack formed, from below the transparent substrate, to separate the transparent substrate from the stack. After the transparent substrate is separated from the stack, a second conductive layer is formed with a predetermined pattern on the dielectric film. Also, an insulating layer and a third conductive layer are formed on the first and second conductive layers to alternate with each other in a predetermined number.
    Type: Application
    Filed: May 15, 2009
    Publication date: September 10, 2009
    Applicant: SAMSUNG ELECTRO-MECHANICS CO.,LTD
    Inventors: Jung Won LEE, Yul Kyo Chung, In Hyung Lee
  • Publication number: 20090209080
    Abstract: The invention includes methods of forming pluralities of capacitors. In one implementation, a method of forming a plurality of capacitors includes providing a plurality of capacitor electrodes within a capacitor array area over a substrate. The capacitor electrodes comprise outer lateral sidewalls. The plurality of capacitor electrodes is supported at least in part with a retaining structure which engages the outer lateral sidewalls. The retaining structure is formed at least in part by etching a layer of material which is not masked anywhere within the capacitor array area to form said retaining structure. The plurality of capacitor electrodes is incorporated into a plurality of capacitors. Other aspects and implementations are contemplated.
    Type: Application
    Filed: April 27, 2009
    Publication date: August 20, 2009
    Inventors: Gurtej S. Sandhu, D. Mark Durcan
  • Patent number: 7575148
    Abstract: A plurality of anode foils (7) and a plurality of cathode foils (8) respectively having connecting portions (12a, 12b) are alternately arranged with insulating separators (9) interposed therebetween. The connecting portions (12a, 12b) of the stacked electrode foils (7, 8) are respectively connected and united electrically and mechanically by friction stir welding, thereby forming a capacitor element (5). The capacitor element (5) is housed in a case (2), and the connecting portions (12a, 12b) are respectively connected to a positive electrode external terminal (4) and a negative electrode external terminal (4).
    Type: Grant
    Filed: March 19, 2004
    Date of Patent: August 18, 2009
    Assignee: Nippon Chemi-Con Corporation
    Inventors: Tatsuo Kubouchi, Hitoshi Iwasaki, Makoto Shimizu
  • Patent number: 7564116
    Abstract: A printed circuit board having embedded capacitors includes a double-sided copper-clad laminate including first circuit layers formed in the outer layers thereof, the first circuit layers including bottom electrodes and circuit patterns; dielectric layers formed by depositing alumina films on the first circuit layers by atomic layer deposition; second circuit layers formed on the dielectric layers and including top electrodes and circuit patterns; one-sided copper-clad laminates formed on the second circuit layers; blind via-holes and through-holes formed in predetermined portions of the one-sided copper-clad laminates; and plating layers formed in the blind via-holes and the through-holes. The manufacturing method of the printed circuit board is also disclosed.
    Type: Grant
    Filed: January 18, 2008
    Date of Patent: July 21, 2009
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jin Yong Ahn, Cheol Seong Hwang, Sung Kun Kim, Chang Sup Ryu, Suk-Hyeon Cho, Ho Sik Jeon
  • Publication number: 20090180235
    Abstract: A circuit component has an elastically deformable first structure, a second structure, and a support structure coupling the first and second structures, wherein the first structure can be variably deformed in response to a variable force, to provide either a variable capacitor or a variable tank circuit having a variable capacitor and an inductor. In one particular embodiment, a piezoelectric element is laminated to the surface of the first elastically deformable structure thereby providing the capability to deform the first structure. A method of making a circuit component includes forming an elastically deformable first structure, forming a second structure, and joining the first and second structures, to provide either a variable capacitor or a variable tank circuit having a variable capacitor and an inductor.
    Type: Application
    Filed: February 21, 2009
    Publication date: July 16, 2009
    Inventors: James Robert White, Christopher John White, Alexander Henry Slocum
  • Patent number: 7553738
    Abstract: A microelectronic device, a method of fabricating the device, and a system including the device. The method includes: providing a substrate including an underlying conductive layer and a polymer build-up layer overlying the underlying conductive layer; providing a passive microelectronic structure; embedding the passive structure in the polymer build-up layer of the substrate; and patterning the passive structure after embedding, patterning including over-etching the bottom electrode layer. The passive microelectronic structure being embedded includes an unpatterned bottom electrode layer; an unpatterned capacitor dielectric layer overlying the bottom electrode layer; and an unpatterned top electrode layer overlying the capacitor dielectric layer.
    Type: Grant
    Filed: December 11, 2006
    Date of Patent: June 30, 2009
    Assignee: Intel Corporation
    Inventors: Yongki Min, Huankiat Seh
  • Publication number: 20090160462
    Abstract: A system and methods of a microelectromechanical capacitor based device are disclosed. In one embodiment, a system of a microelectromechanical capacitive device includes a housing formed when a nonconductive material is deposited on a substrate, and a conductive plate mechanically coupled to the housing. The system further includes an additional housing coupled to the housing and an additional conductive plate that is substantially parallel to the conductive plate. The additional conductive plate is coupled to the additional conductive plate. The additional housing may be formed when an additional nonconductive material is deposited on an additional substrate. The substrate and the additional substrate may be dissolved using a chemical etching process when the housing and the additional housing are coupled.
    Type: Application
    Filed: December 23, 2008
    Publication date: June 25, 2009
    Inventor: DIVYASIMHA HARISH