Electric Condenser Making Patents (Class 29/25.41)
  • Patent number: 6849292
    Abstract: The present invention concerns the field of solid state capacitors and relates particularly to massed production methods for manufacturing solid state capacitors.
    Type: Grant
    Filed: August 9, 2000
    Date of Patent: February 1, 2005
    Assignee: AVX Limited
    Inventor: David Huntington
  • Patent number: 6850405
    Abstract: New designs that provide two anodes and their associated feedthroughs incorporated into one capacitor are described. The feedthrough wires can be in their own glass-to-metal seal or, they can be combined into one glass-to-metal seal as long as they are electrically insulated from each other. One embodiment has the anode feedthroughs left unconnected, while in other embodiments; they are joined externally of the capacitor casing. Several interconnect designs are described.
    Type: Grant
    Filed: December 16, 2003
    Date of Patent: February 1, 2005
    Assignee: Wilson Greatbatch Technologies, Inc.
    Inventors: Richard Mileham, Eric Stemen, Laurie O'Connor, William Elliott, Joseph E. Spaulding, Barry C. Muffoletto, Douglas Eberhard
  • Publication number: 20040250393
    Abstract: There is disclosed herein a high voltage and high temperature power electronics capacitor which comprises one or more insulator layers of mica paper, and one or more metal conductor layers, all dispersed in a pressurized environment of a nonreactive and high voltage strength gas maintained at near ambient to about 405.2 kPa of pressure. The insulator and conductor layers are isolated and separated from one another by the alternating placement of conductor layers between said insulator layers. These capacitors are readily packaged for commercial use in containers or housings of almost any geometric form and any material of construction. Moreover, low inductance ceramic bushings can be employed on these containers for establishing external electrical contacts. These capacitors can be economically manufactured and used in large commercial volumes with currently available materials and production methods.
    Type: Application
    Filed: June 12, 2003
    Publication date: December 16, 2004
    Applicant: The United States of America as represented by the Secretary of the Army
    Inventors: Lyon Mandelcorn, John S. Bowers, Eugene R. Danielson, Stephen R. Gurkovich, Kenneth C. Radford
  • Patent number: 6829814
    Abstract: A process of forming a capacitive audio transducer, preferably having an all-silicon monolithic construction that includes capacitive plates defined by doped single-crystal silicon layers. The capacitive plates are defined by etching the single-crystal silicon layers, and the capacitive gap therebetween is accurately established by wafer bonding, yielding a transducer that can be produced by high-volume manufacturing practices.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: December 14, 2004
    Assignee: Delphi Technologies, Inc.
    Inventors: John E. Freeman, William J. Baney, Timothy M. Betzner, Dan W. Chilcott, John C. Christenson, Timothy A. Vas, George M Queen, Stephen P Long
  • Publication number: 20040227429
    Abstract: A method is described for making a composite, such as a piezoelectric composite, having a predetermined volume ratio. Initially, a pair of base slabs are diced to form slot having uniform pitch spacing such that a material portion of one diced base slab may be received within the slots of another diced base slab. The diced base slabs are interdigitated and joined to form a first piezoelectric composite that can subsequently be diced to form slots having a uniform pitch spacing that are spaced from the first slots. Two diced first piezoelectric composites are interdigitated and joined to form a second piezoelectric composite of reduced volume ratio and finer pitch.
    Type: Application
    Filed: December 3, 2003
    Publication date: November 18, 2004
    Inventors: Jainhua Yin, Francis Stuart Foster, Katarzyna Anna Harasiewicz
  • Patent number: 6813137
    Abstract: A chip shaped electronic device comprising an element body including zinc oxide material layers and internal electrode layers, wherein when assuming a minimum distance from an outermost side of the internal electrode layer in the stacking direction to a surface of the element body is 1 and measuring an ion intensity ratio of Li and Zn, (Li/Zn), in a range from the surface of the element body to a depth of (0.9×1) by a secondary ion mass spectrometry (SIMS), 0.001≦(Li/Zn)≦500. According to the invention, it is possible to provide a chip shaped electronic device, such as a multilayer chip varistor, not requiring glass coating or other insulative protective layer, being tolerant of temperature changes, capable of maintaining high resistance of an element surface even by reflow soldering, being highly reliable, and capable of being easily produced, and a method of producing the same.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: November 2, 2004
    Assignee: TDK Corporation
    Inventors: Dai Matsuoka, Hidetaka Kitamura, Tadashi Ogasawara
  • Publication number: 20040187281
    Abstract: A method for fabricating piezoelectric workpieces with augmenting surface electrodes is disclosed for improving fabrication and operation reliability of the workpieces. The fabrication method forms a plurality of function electrodes on the surface of the body of the workpiece and the function electrodes being connected in the electric circuit of the piezoelectric system. At least one of the function electrodes has a shape with a contour of at least one acute angle. At least one polarization augmenting electrode is then formed on the surface of the body proximate to the acute angle, the polarization augmenting electrode and the proximate function electrode thereof constituting a gross electrode when connected electrically together. Electric dipoles of grain molecules of the body are then polarized utilizing the gross electrode, the gross electrode substantially cancels the acute angle when paired with one of the function electrodes and connected to a polarization voltage for implementing the polarization.
    Type: Application
    Filed: April 26, 2004
    Publication date: September 30, 2004
    Inventors: Yu-Hsiang Hsu, Wen-Hsin Hsiao, Wen-Jong Wu, Chih-Kung Lee
  • Patent number: 6798640
    Abstract: A method for constructing a capacitor having an increased equivalent series resistance (ESR) is disclosed. In one embodiment, a capacitor includes a plurality of capacitor plates comprised of a conductive material and first and second capacitor terminals. At least one of the capacitor plates is coupled to the first terminal and at least one of the capacitor plates is coupled to the second terminal. At least one of the plurality of capacitor plates includes a pattern, wherein the pattern is void of conductive material. The void in the conductive material formed by the pattern may cause a path of current flow through the capacitor plate to be substantially altered in comparison to a capacitor plate that is continuous. By using capacitor plates having voids of conductive material that cause the current path to be altered in comparison to continuous capacitor plates, a capacitor can be constructed having a higher ESR.
    Type: Grant
    Filed: September 3, 2003
    Date of Patent: September 28, 2004
    Assignee: Sun Microsystems, Inc.
    Inventor: Istvan Novak
  • Patent number: 6795296
    Abstract: A method for making, and a dielectric material is provided. A capacitor is provided that includes a lossy dielectric layer that is also not leaky. The lossy behavior dampens unwanted oscillations in power supplies or other electrical systems. A capacitor is further provided is tunable for an amount of lossy behavior over a broad range. A core dopant concentration can be varied, and a doped core grain fraction can be varied to control the extent of a desired lossy property in a capacitor. Dielectric materials having grains with doped shells reduce leakiness. Additionally in selected embodiments, undoped core grains mixed with doped core grains reduce leakiness.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: September 21, 2004
    Inventors: Cengiz A. Palanduz, Victor Prokofiev
  • Patent number: 6785941
    Abstract: A method of manufacturing a multi-layer ceramic electronic part involves the steps of preparing an unbaked laminated body containing a ceramic layer and internal electrodes laminated on one another, applying and drying a conductor, into which is added a material common with a ceramic forming the ceramic layer of the laminated body, on edge portions of the unbaked laminated body, forming external electrodes in contact with the internal electrodes at end surfaces of the laminated body, and baking the laminated body.
    Type: Grant
    Filed: November 8, 2001
    Date of Patent: September 7, 2004
    Assignee: Taiyo Yuden Co., Ltd.
    Inventor: Toshiya Nakamura
  • Publication number: 20040163225
    Abstract: A piezoelectric/electrostrictive device (10) includes a pair of thin plates (12a, 12b) confronting each other, a fixing member (14) supporting the thin plates (12a, 12b) thereon, and movable portions (22a, 22b) disposed on end portions of the pair of thin plates (12a, 12b). The piezoelectric/electrostrictive device (10) is manufactured by the following steps. Protrusions (72) are formed on principal surfaces of first ceramic green sheets (60A, 60B) according to at least a single thick film forming process. The protrusions (72) will subsequently serve as the movable portions (22a, 22b), and the first ceramic green sheets (60A, 60B) will subsequently serve as the thin plates (12a, 12b). The first ceramic green sheets (60A, 60B) and a second ceramic green sheet (64) which will subsequently serve as the fixing member (14) are stacked into a ceramic green laminated body (50). The ceramic green laminated body (50) is baked into an integral ceramic laminated body (52).
    Type: Application
    Filed: February 23, 2004
    Publication date: August 26, 2004
    Applicant: NGK Insulators, Ltd.
    Inventors: Koji Ikeda, Kazuyoshi Shibata, Tomoki Ito
  • Patent number: 6769159
    Abstract: A method for producing a ceramic electronic part includes forming a plurality of internal electrodes arranged in a ceramic sintered compact, superimposed via a ceramic layer. The free ends of the internal electrodes are formed to have a wedge-like cross-sectional shape, with the length L of the wedge and the internal thickness t of the electrode at the base of the wedge satisfying the relationship L>2t so that there is no risk of generating inter-layer peel-off or delamination in the ceramic layers.
    Type: Grant
    Filed: June 6, 2001
    Date of Patent: August 3, 2004
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Tatsuo Haratani, Yasunobu Yoneda, Kyoshin Asakura
  • Publication number: 20040139589
    Abstract: The present invention relates to a method for producing an electrical subassembly comprising a circuit carrier and at least one passive component which is integrated into the circuit carrier and comprises an electrically functional material.
    Type: Application
    Filed: December 8, 2003
    Publication date: July 22, 2004
    Applicant: FRIWO Geratebau GmbH
    Inventors: Michael Bothe, Stefan Morbe
  • Patent number: 6764712
    Abstract: A method for increasing the surface area of foil electrodes of electrolytic capacitors. A valve metal is deposited by evaporation on a valve metal foil in a low pressure inert atmosphere including oxygen at a pressure one to two orders of magnitude lower than the pressure of the inert gas. The resulting surface is fractal-like. The foil thus treated is suitable as such for use as a cathode. Prior to anodization to produce an anode, a discontinuous layer of a valve metal oxide is deposited on the foil, to preserve the high surface area of the fractal-like surface and otherwise promote the formation of a dielectric coating whose interface with the metal foil has a high surface area.
    Type: Grant
    Filed: December 21, 2000
    Date of Patent: July 20, 2004
    Assignee: Acktar Ltd
    Inventors: Dina Katsir, Iris Tartakovsky, Israel Tartakovsky
  • Patent number: 6762925
    Abstract: A ceramic electronic component includes a ceramic sintered compact containing about 35 to 80 volume percent pores and an electrode provided inside the ceramic sintered compact. The pores are filled with resin or glass. This ceramic electronic component is formed by forming a green compact which includes an electrode therein with a ceramic compound having a ceramic raw material, a binder and a spherical or granular combustible material having adhesiveness to the binder. The green compact is fired to form the ceramic sintered compact including the electrode and containing about 35 to 80 volume percent pores. The pores of the ceramic sintered compact are filled with resin or glass.
    Type: Grant
    Filed: April 1, 2003
    Date of Patent: July 13, 2004
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Katsuyuki Uchida, Toshio Kawabata, Takehiko Otsuki, Masami Sugitani, Motoi Nishii, Yukio Sakamoto, Kaoru Tachibana
  • Patent number: 6757963
    Abstract: A surface of a first ceramic component is joined to a surface of a second ceramic component using a silver-based composition. The silver-based composition is a mixture of silver metal and a metal oxide and the metal in the metal oxide is a metal other than silver. The silver-based composition is applied to the surface of the first ceramic component and to the surface of the second ceramic component. The silver-based composition applied to the first ceramic component is contacted to the silver-based composition applied to the second ceramic component. The surfaces of the first and second ceramic components are heated to melt the applied silver-based compositions. The surfaces of the first and second ceramic components are cooled to form a bond between the first and second ceramic components.
    Type: Grant
    Filed: January 23, 2002
    Date of Patent: July 6, 2004
    Assignee: McGraw-Edison Company
    Inventors: Alan M. Meier, David R. Miller, Kevin R. Dickson, Roger S. Perkins, Michael M. Ramarge
  • Patent number: 6751833
    Abstract: A method of manufacturing a laminated electrolytic capacitor by forming a dielectric made of organic polymer or a composite dielectric made of organic polymer and an oxide of a conductive metal is disclosed. An insulating layer is formed on the conductor, and an electrode is formed on the dielectric layer to complete the capacitive element. Plural capacitor elements are laminated and bonded to outside connection terminals.
    Type: Grant
    Filed: April 23, 2001
    Date of Patent: June 22, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshiharu Saito, Motoi Kitano, Mutsuaki Murakami
  • Patent number: 6751832
    Abstract: A method of manufacturing a piezoelectric/electrostrictive device includes the following steps. An integrated layered body is obtained by laminating at least one green sheet that is to be a thin plate, at least one green sheet having at least one rectangular-shaped hole portion, and at least one green sheet that is to be another thin plate. A piezoelectric/electrostrictive element is formed on a surface of the green sheets that form the thin plates by one of a thick film method or a thin film method. The layered body is cut in the laminating direction of the green sheets such that the rectangular-shaped hole portion is open on the side of the layered body after sintering the layered body.
    Type: Grant
    Filed: September 24, 2001
    Date of Patent: June 22, 2004
    Assignee: NGK Insulators, Ltd.
    Inventors: Toshikazu Hirota, Koji Kimura, Yukihisa Takeuchi
  • Patent number: 6749890
    Abstract: The invention provides an electrode forming method with steps of arraying chip-style electronic components on an arraying flat bed thereby positioning and aligning the components, lowering a film coated with an adhesive in relative manner together with an adhering top plate parallel to the arraying flat bed thereby adhering ends of the positioned and aligned chip-style electronic components to the adhesive, then lowering the first film to which the chip-style electronic components are adhered in relative manner together with a coating top plate parallel to a coating flat bed provided with a conductive paste layer of a constant thickness thereby pressing the other ends of the chip-style electronic components to the coating flat bed and coating the ends of the electronic components with the conductive paste.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: June 15, 2004
    Assignee: TDK Corporation
    Inventors: Ko Onodera, Satoshi Kurimoto
  • Publication number: 20040107555
    Abstract: A method for making a monolithic ceramic capacitor ceramic capacitor includes preparing a conductive film on a carrier film by a thin-film forming method; preparing high-binder-content first ceramic green sheets and low-binder-content second ceramic green sheets; transferring the conductive film on a first main surface of the first ceramic green sheet; stacking the second ceramic green sheets on a second main surface of the first ceramic green sheet with the conductive film and stacking another first ceramic green sheet on the second ceramic green sheet so as to form a ceramic green layer; preparing a green composite containing the ceramic green layer; sintering green composite to prepare a compact; and forming external electrodes onto side faces of the compact.
    Type: Application
    Filed: November 18, 2003
    Publication date: June 10, 2004
    Inventors: Koji Hattori, Teppei Akiyoshi
  • Patent number: 6739028
    Abstract: A high impedance surface and a method of making same. The surface includes a molded structure having a repeating pattern of holes therein and a repeating pattern of sidewall surfaces, the holes penetrating the structure between first and second major surfaces thereof and the sidewall surfaces joining the first major surface. A metal layer is put on said molded structure, the metal layer being in the holes, covering at least a portion of the second major surface, covering the sidewalls and portions of the first major surface to interconnect the sidewalls with other sidewalls via the metal layer on the second major surface and in the holes.
    Type: Grant
    Filed: July 13, 2001
    Date of Patent: May 25, 2004
    Assignee: HRL Laboratories, LLC
    Inventors: Daniel F. Sievenpiper, Joseph L. Pikulski, James H. Schaffner, Tsung-Yuan Hsu
  • Patent number: 6740351
    Abstract: For manufacturing a multi-layer structure with repeating layer sequences, a band-shaped carrier material is first partially separated into individual sections of a same size with connections capable of bearing remaining between the individual sections. After continuously applying at least one further material layer on the surface of the carrier material, the individual sections are completely separated by cutting or punching. The multi-layer structure is obtained by stacking the individual sections obtained in this way on top of one another, whereby intermediate layers can also be potentially inserted between two individual sections.
    Type: Grant
    Filed: June 20, 2002
    Date of Patent: May 25, 2004
    Assignee: Epcos AG
    Inventors: Klaus Schoch, Werner Erhardt, Hartmut Michel
  • Patent number: 6739027
    Abstract: A method is provided for producing a capacitor to be embedded in an electronic circuit package comprising the steps of selecting a first conductor foil, selecting a dielectric material, coating the dielectric material on at least one side of the first conductor foil, and layering the coated foil with a second conductor foil on top of the coating of dielectric material. Also claimed is an electronic circuit package incorporating at least one embedded capacitor manufactured in accordance with the present invention.
    Type: Grant
    Filed: April 20, 2000
    Date of Patent: May 25, 2004
    Assignee: International Business Machines Corporation
    Inventors: John M. Lauffer, Konstantinos Papathomas
  • Patent number: 6735845
    Abstract: A method of manufacturing a pressure sensor house assembly which contains a reference cavity, in which a vacuum exists, and a getter capable of being thermally activated. The getter is activated by directly contacting the getter with an exterior heated body, conducting heat from the exterior heated body, maintaining the exterior heated body in direct contact with the getter for a predetermined period of time, and removing the exterior heated body.
    Type: Grant
    Filed: August 20, 1999
    Date of Patent: May 18, 2004
    Assignee: MKS Instruments Inc.
    Inventor: Staffan Jonsson
  • Patent number: 6735851
    Abstract: Superconducting birdcage coil with low-pass and high-pass coil configurations are formed by using strips each with an elongated sapphire substrate with a layer of a high temperature superconductor (HTS) material grown in a wavy pattern over its entire length on one of its main surfaces. A low-pass coil is formed with a pair of ring elements made of an electrically conductive metal and a plurality of such strips arranged parallel to one another and interconnecting these ring elements at junctions which are spaced peripherally along each of the rings. At each of the junctions, the ring element and the HTS layer form a capacitance. A high-pass coil is formed by a plurality of such strips each with electrodes of the HTS material also grown at two end positions separated from each other on the other main surface of its sapphire substrates. These strips are arranged parallel to each other and sequentially around a central axis, each lying in a plane which includes the center axis.
    Type: Grant
    Filed: January 8, 2002
    Date of Patent: May 18, 2004
    Assignee: Varian, Inc.
    Inventors: Marco A. Romo, Wai Ha Wong
  • Publication number: 20040090752
    Abstract: A combination run capacitor/positive temperature coefficient resistor/overload (CAP/PTCR/OL) module is described. The cover of the combination housing includes a capacitor compartment and terminal openings for receiving blade terminals of a run capacitor. The terminal openings in the cover align with blade receiving receptacles coupled to the PTCR start circuit. The blade terminals of a run capacitor are inserted into the receptacle openings and into electrical engagement with the blade receiving receptacles. The capacitor is supported and protected by a potting mixture filling the capacitor compartment.
    Type: Application
    Filed: November 7, 2002
    Publication date: May 13, 2004
    Inventors: Alan Joseph Janicek, Kennett Ray Fuller, Mark Alan Heflin
  • Patent number: 6735071
    Abstract: During molding of a brush holder which is a resin-molded part in an alternator, a capacitor component is molded integrally with a capacitor positive electrode terminal and a capacitor negative electrode terminal joined by crimping to a positive terminal and a negative terminal, respectively. The capacitor component is thereby embedded in a first resin portion.
    Type: Grant
    Filed: July 8, 2002
    Date of Patent: May 11, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Atsushi Oohashi, Yoshihito Asao, Hideki Morikaku
  • Publication number: 20040084207
    Abstract: A high impedance surface and a method of making same. The surface includes a molded structure having a repeating pattern of holes therein and a repeating pattern of sidewall surfaces, the holes penetrating the structure between first and second major surfaces thereof and the sidewall surfaces joining the first major surface. A metal layer is put on said molded structure, the metal layer being in the holes, covering at least a portion of the second major surface, covering the sidewalls and portions of the first major surface to interconnect the sidewalls with other sidewalls via the metal layer on the second major surface and in the holes.
    Type: Application
    Filed: December 5, 2003
    Publication date: May 6, 2004
    Applicant: HRL Laboratories, LLC
    Inventors: Daniel F. Sievenpiper, Joseph L. Pikulski, James H. Schaffner, Tsung-Yuan Hsu
  • Patent number: 6729003
    Abstract: A process of producing a ceramic electronic component comprises external electrodes having first electrode layers containing at least a noble metal, cuprous oxide, and glass ingredient electrically connected to internal electrodes comprising a noble metal. As the ceramic electronic components, for example, a multi-layer ceramic capacitor, multi-layer varistor, multi-layer dielectric resonator, multi-layer piezoelectric element, etc. may be mentioned.
    Type: Grant
    Filed: November 8, 2001
    Date of Patent: May 4, 2004
    Assignee: TDK Corporation
    Inventors: Hideki Yokoyama, Takaya Ishigaki, Akira Sasaki, Shintarou Kon, Tetuji Maruno
  • Patent number: 6718605
    Abstract: A high sensitivity, Z-axis, capacitive microaccelerometer having stiff sense/feedback electrodes and a method of its manufacture on a single-side of a semiconductor wafer are provided. The microaccelerometer is manufactured out of a single silicon wafer and has a silicon-wafer-thick proof mass, small and controllable damping, large capacitance variation and can be operated in a force-rebalanced control loop. One of the electrodes moves with the proof mass relative to the other electrode which is fixed. The multiple, stiffened electrodes have embedded therein damping holes to facilitate force-rebalanced operation of the device and to control the damping factor. Using the whole silicon wafer to form the thick large proof mass and using thin sacrificial layers to form narrow uniform capacitor air gaps over large areas provide large-capacitance sensitivity. The manufacturing process is simple and thus results in low cost and high yield manufacturing.
    Type: Grant
    Filed: June 21, 2001
    Date of Patent: April 13, 2004
    Assignee: The Regents of the University of Michigan
    Inventors: Navid Yazdi, Khalil Najafi, Arvind Salian
  • Patent number: 6694583
    Abstract: An apparatus and method for creating multi-layer embedded ceramic capacitors in low-temperature co-fired ceramic (LTCC) substrates. In order to create multiple layers of electrodes, the individual electrode layers must be connected electrically. According to the present invention, a multi-layer capacitor is formed on a first ceramic tape layer. A second tape layer having an opening is placed on top of the first layer. The opening in the second layer is formed such that exposed vias are present on at least two sides of the opening to electrically connect to the electrodes. When the tape layers are pressed and fired, the exposed vias and electrodes form common electrical connections. A third layer having a terminal via may be placed on top of the second layer.
    Type: Grant
    Filed: February 16, 2001
    Date of Patent: February 24, 2004
    Assignee: National Semiconductor Corporation
    Inventor: Shaul Branchevsky
  • Patent number: 6694032
    Abstract: The present invention relates to an electret condenser microphone including the vibratory diaphragm which is comprised of an electret film into which an electric charge is charged; a conductive film formed on one side of the electret film and a polar ring disposed at a peripheral edge of the underside of the conductive film. Also, this microphone includes a vibratory diaphragm support member which is disposed on the vibratory diaphragm and has a concave groove and a concave portion. On the vibratory diaphragm support member is attached an integrated circuit serving to receive and amplify a transformed electrical signal from the vibratory diaphragm.
    Type: Grant
    Filed: December 27, 2001
    Date of Patent: February 17, 2004
    Assignee: BSE Co., Ltd.
    Inventors: Du-Yeong Yun, Sung-Ho Park
  • Publication number: 20040016094
    Abstract: A method of forming a capacitor comprises: providing a first metallic thin-film layer; forming a dielectric thin-film layer of an anodized metal on a side of said first metallic layer; providing a second metallic thin-film layer on a side of the dielectric layer opposite the first metallic layer; and excising an area of the resulting structure to obtain at least one capacitor having a pair of electrode plate structures constituted by portions of said first and second metallic layers separated by a portion of said dielectric layer, and having connection points at adjacent electrode plate edges which are accessible from a same side of the capacitor and effective for operatively connecting the capacitor such that the capacitor does not exhibit an inductive resonance below a frequency of at least 1 GHz.
    Type: Application
    Filed: January 13, 2003
    Publication date: January 29, 2004
    Applicant: The Board of Trustees of the University of Arkansas
    Inventor: Leonard W. Schaper
  • Patent number: 6682772
    Abstract: A platinum deposition method uses a combination of an oxide adhesion layer and a high temperature thin film deposition process to produce platinum bottom electrodes for ferroelectric capacitors. The platinum bottom electrode is deposited onto a TiOx layer at temperatures between about 300 and 800° C. Deposition at high temperatures changes the platinum stress from compressive to tensile, increases platinum grain size, and provides a more thermally stable substrate for subsequent PZT deposition.
    Type: Grant
    Filed: April 24, 2000
    Date of Patent: January 27, 2004
    Assignees: Ramtron International Corporation, Ulvac Japan, Ltd.
    Inventors: Glen R. Fox, KouKou Suu
  • Publication number: 20040012942
    Abstract: A capacitive vacuum measuring cell includes first and second ceramic housing bodies (1, 4) joined by an edge seal (3). A thin ceramic membrane (2) is supported between first and second housing bodies (1, 4) by the edge seal (3) at a small distance from the first housing body (1) creating a reference vacuum chamber (25) therebetween. An electrically conductive material (7) coats opposing surfaces of the first housing body (1) and the membrane (2) to form a capacitor. A measurement vacuum chamber (26) is provided between the membrane (2) and the second housing body (4). A port (5) communicates with the second housing body (4) to connect the measurement vacuum chamber (26) of the measuring cell to the medium to be measured. The membrane (2) is made from an Al2O3 slurry that is sintered in a first heating step, cooled, and then reheated to smooth the membrane.
    Type: Application
    Filed: July 11, 2003
    Publication date: January 22, 2004
    Applicant: INFICON GmbH
    Inventors: Per Bjoerkman, Ray Olsson
  • Patent number: 6678383
    Abstract: A capacitor microphone includes a case having an end wall defining an opening for a sound hole, a capacitor portion comprising a diaphragm, a back plate and a spacer, the diaphragm opposing to the back plate via the spacer, the capacitor portion being accommodated in the case in such an manner as the diaphragm is placed on the side of the end wall, and a substrate accommodated in the case farther from the end wall than the capacitor portion, the substrate having an impedance conversion element mounted on a surface thereof facing the capacitor portion. A communicating opening is provided around the back plate in a position opposing to the impedance conversion element for communicating spaces on the front and back sides of the back plate. The communicating opening has a larger area than that of the top of the impedance conversion element to allow the spaces on both sides of the back plate to communicate with each other.
    Type: Grant
    Filed: October 29, 2001
    Date of Patent: January 13, 2004
    Assignee: Star Micronics Co., Ltd.
    Inventors: Motoaki Ito, Yoshio Imahori
  • Patent number: 6678148
    Abstract: An electrode for an electrolytic capacitor and a method for producing the electrodes including a conducting electrode material, in particular a foil, such as an aluminum foil. The conducting electrode material, for the purpose of increasing the surface, is exposed to a chemical or an electrochemical etching process. During the etching process, in an etching cell, at least one zone of the surface of the electrode material is covered with an etch-resistant coating and/or a separate protective shielding. After the etching process, the electrode is cut out, punched out or the like worked out of the electrode material such that the etched zone forms at least one margin region, in particular, a margin strip of the electrode.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: January 13, 2004
    Assignee: Becromal S.p.A.
    Inventor: Giovanni Pietro Chiavarotti
  • Patent number: 6673389
    Abstract: The present invention concerns the field of solid state capacitors and relates particularly to massed production methods for manufacturing solid state capacitors. The present invention seeks to provide a process simplification in order to provide an economic advantage.
    Type: Grant
    Filed: August 19, 2002
    Date of Patent: January 6, 2004
    Assignee: AVX Limited
    Inventor: David Huntington
  • Publication number: 20030224568
    Abstract: A capacitor fabricating method of the present invention includes the steps of: selectively forming a positive photosensitive resin layer on a first conductive layer; exposing the positive photosensitive resin layer, thereby obtaining an exposed positive photosensitive resin layer; immersing the exposed positive photosensitive resin layer in a solution in which dielectric particles are dispersed to diffuse the dielectric particles into the positive photosensitive resin layer; forming an insulating resin layer so as to cover side faces of the positive photosensitive resin layer; and forming a second conductive layer on the positive photosensitive resin layer. According to the method, a very reliable capacitor having excellent electric characteristics such as dielectric strength characteristic can be cheaply and easily fabricated in a wiring layer.
    Type: Application
    Filed: November 26, 2002
    Publication date: December 4, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Toshiyuki Toyoshima, Hirofumi Fujioka
  • Patent number: 6643903
    Abstract: A process for manufacturing an EMI filter feedthrough terminal assembly is provided for mating a feedthrough filter capacitor with an hermetic terminal assembly including a ferrule and one or more lead wires which extend through the ferrule in non-conductive relation. The process includes the steps of placing the hermetic terminal assembly, having a capture flange, into a holding fixture, and forming a seat of non-conductive thermal-setting material onto the terminal assembly within the capture flange. A feedthrough filter capacitor is loaded into the capture flange on top of the seat, and then the seat is cured. A conductive thermal-setting material is dispensed between an outer diameter of the feedthrough filter capacitor and the capture flange. The assembly is then centrifuged to pack the conductive thermal-setting material. The conductive thermal-setting material is then cured between the outer diameter of the feedthrough filter capacitor and the capture flange.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: November 11, 2003
    Assignee: Greatbatch-Sierra, Inc.
    Inventors: Robert A. Stevenson, Donald K. Haskell, Richard L. Brendel
  • Patent number: 6643116
    Abstract: An RF security element has a capacitor (8) and a spiral-wound coil (4) with at least two windings (6), in which the coil has at least one winding of straight wire (12) and at least one winding of undulated wire (14). The coil is produced by alternately winding at least one turn of straight wire (12) and at least one turn of undulated wire (14) onto a winding spindle (22), with the undulated wire being formed by passing a portion of straight wire (12) through at least two mating gears (26). The capacitor (8) is produced by intertwining first and second pieces of wire (16, 18) on the two ends of the coil (4).
    Type: Grant
    Filed: November 5, 2002
    Date of Patent: November 4, 2003
    Assignee: Checkpoint Systems International GmbH
    Inventor: Rainer Nolte
  • Patent number: 6640403
    Abstract: A method for forming a dielectric-constant-enhanced capacitor is provided. A wafer in a reaction chamber is provided, wherein said wafer comprises a first conductive layer. Then, a first dielectric layer is formed above said first conductive layer to prevent said first conductive layer from growing silicon oxide and to diminish leakage current. Next a precursor is transmitted to a vaporizer. Then said precursor is transformed to a gas and said gas is transmitted to said reaction chamber. Next, a second dielectric layer is deposited above said first dielectric layer. Then a heat treatment is proceeded and a second conductive layer is formed on said second dielectric layer.
    Type: Grant
    Filed: May 29, 2001
    Date of Patent: November 4, 2003
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Wong-Cheng Shih, Lan Lin Chao, Tai-Bor Wu, Chich-Shang Chang
  • Publication number: 20030200652
    Abstract: A method for improving the EMI compatibility of the keyboard soft board is disclosed. A low-pass filter is installed on the scan lines of the keyboard soft board to remove high-frequency noise signals produced by the soft board circuit, achieving the EMC requirement. The low-pass filter is formed between the input terminal of the scan line and the touch pad. An inductance is selectively installed and between the touch pads. A capacitance is formed between the touch pad of the scan line and a ground network. The method of forming the capacitance is to form ground pads on the ground network corresponding the scan line touch pads. The method of forming the inductance may be achieved through a reversed U-shaped inductor.
    Type: Application
    Filed: August 30, 2002
    Publication date: October 30, 2003
    Inventor: Bright Huang
  • Patent number: 6631540
    Abstract: A method of forming a capacitor with low inductance connection terminals, comprising a first surface including a first electrode of porous metal, forming a dielectric layer on the first electrode, forming a second electrode on the dielectric layer, attaching a plurality of electrically coupled connection terminals to the first electrode on the first surface and attaching a plurality of electrically coupled connection terminals to the second electrode on the first surface.
    Type: Grant
    Filed: December 19, 2000
    Date of Patent: October 14, 2003
    Assignee: Intel Corporation
    Inventor: Larry E. Mosley
  • Patent number: 6631070
    Abstract: The invention relates to a ceramic capacitor having at least two electrodes and a ceramic dielectric of a dielectric, ceramic preparation which is essentially composed of an oxide-ceramic dielectric substance and a sintering agent including zinc borate Zn4B6O13.
    Type: Grant
    Filed: July 1, 2002
    Date of Patent: October 7, 2003
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Peter Schmidt, Detlev Hennings
  • Patent number: 6622368
    Abstract: A method of manufacturing a transducer of the type having a diaphragm (11) with a predetermined tension. After the transducer has been manufactured with its basic structure the diaphragm is adjusted to have a predetermined tension, which is preferably low in order to obtain a high sensitivity. Two embodiments are disclosed. One embodiment includes heating the transducer to a temperature above the glass transition temperature of the material (12, 14) retaining the diaphragm. Another embodiment includes measuring the actual tension of the diaphragm, which can be used to calculate an adjustment of the thickness of the diaphragm resulting in the desired tension.
    Type: Grant
    Filed: January 5, 2001
    Date of Patent: September 23, 2003
    Assignee: SonionMEMS A/S
    Inventors: Matthias Müllenborn, Pirmin Rombach
  • Publication number: 20030154583
    Abstract: A method for manufacturing large capacitance solid electrolytic capacitors that can be connected direct with semiconductor component, and offer a superior high frequency characteristic. An aluminum foil 3 is made porous in one of the surfaces, a dielectric layer 2 is formed on the porous portion, a through hole 4 is provided in the aluminum foil 3 at a certain specific location. An insulation layer 5 is formed to cover the other surface, viz. non-porous surface, of the aluminum foil 3 and the inner wall surface of through hole 4, a solid electrolytic layer 6 is provided on the dielectric layer 2, and a through hole electrode 7 is formed in the through hole 4, and then a collector layer 8 is formed on the solid electrolytic layer 6. The insulation layer 5 disposed on aluminum foil 3 is provided with an opening 9 at a certain specific location, and a connection terminal 10 is provided at the opening 9 of insulation layer 5 and the exposed surface of the through hole electrode 7, respectively.
    Type: Application
    Filed: February 21, 2003
    Publication date: August 21, 2003
    Inventors: Tatsuo Fujii, Katsumasa Miki, Makoto Nakano, Suzushi Kimura, Yuji Mido
  • Patent number: 6604276
    Abstract: A ceramic chip-type device having a glass coating film and a fabricating method thereof are provided, in which a coating film having an excellent acid-resistant property is formed on the surface of the ceramic chip device. Thus, the ceramic chip-type device having a glass coating film stands an attack due to a flux at the time of reflow soldering, to thereby maintain an initial insulation resistance. The ceramic chip-type device is made of a ceramic passive device chip including a pair of external electrode terminals on either end of the ceramic chip-type device, and a glass coating film of an excellent acid-resistant property formed on the surface of a ceramic body located between the pair of external electrode terminals.
    Type: Grant
    Filed: April 23, 2001
    Date of Patent: August 12, 2003
    Assignee: Amotech Co., Ltd.
    Inventors: Jun Hwan Jeong, Seung Chul Lee, Hyun Choi
  • Publication number: 20030123215
    Abstract: A feedthrough device and brazing process for joining the constituent parts of the feedthrough device, while allowing a lead to pass therethrough in a nonconductive manner. The feedthrough comprises at least one lead, a ferrule defining a capacitor recess and defining an insulator recess, an insulator disposed in the insulator recess of the ferrule, the insulator defining a passageway sized to allow the lead to pass therethrough. The feedthrough further comprises a capacitor disposed in the capacitor recess and defining a capacitor passageway sized to allow the lead to pass threrethrough, and the capacitor comprises first and second sets of plates, wherein the first set of plates is conductively coupled to the ferrule and the second set of plates is conductively coupled to the lead. Brazing is a two step process wherein the braze joints between the insulator and the lead and between the insulator and ferrule are formed first at a first temperature using an insulator braze material.
    Type: Application
    Filed: August 2, 2002
    Publication date: July 3, 2003
    Inventors: Kevin M. Allen, Thomas W. Shipman, Allan S. Gelb
  • Publication number: 20030110865
    Abstract: A compact pressure sensor of capacitive type includes a pressure sensor housing assembly, which contains a reference cavity in which a high vacuum exists and which has a minimum volume. The pressure sensor housing comprises an upper base plate, a thinner shielding plate and a movable diaphragm, and a small cavity formed between the shielding plate and movable diaphragm. A narrow channel extends from the cavity to the outside and they form a reference cavity. At the mouth of the channel a recess is provided containing an elastically mounted getter body which is capable of being thermally activated, so that a portion of the surface of the getter body is a wall surface in the reference cavity. A closing lid having a low projecting profile is placed in a gastight way in the recess and engages the getter body. When simultaneously closing the reference cavity and activating the getter body, the lid is attached to a heating probe at a distance from the sensor housing and the getter body is placed in the recess.
    Type: Application
    Filed: August 20, 1999
    Publication date: June 19, 2003
    Inventor: STAFFAN JOHSSON